2nd forward unit - 58MHz with 31bit shift...

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index d0b5b3388cf2f3ab7d3191001588b69616fb51ef..e16bb857b6dd0b3fa991a52f341b8955ea6bee79 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -55,6 +55,7 @@ add wave  -radix hexadecimal /pipeline_tb/decode_st/instr_spl
 add wave  -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
+add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec_nxt
 add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data

diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd
index 99b4655047b699dc4be8a2afad494800359523d5..13285d9eb3e461f2463018c83a39a030f6ff986d 100755 (executable)
--- a/cpu/src/alu_pkg.vhd
+++ b/cpu/src/alu_pkg.vhd
@@ -42,7 +42,7 @@ package alu_pkg is
                
        end record alu_result_rec;
        
-       constant SHIFT_WIDTH : integer := log2c(gp_register_t'length);
+       constant SHIFT_WIDTH : integer := 4; --log2c(gp_register_t'length);
        
        constant COND_ZERO : condition_t := "0001";
        constant COND_NZERO : condition_t := "0000";

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 06e376956e20cad9acf52e656a572b3219fffddf..afb729434501c09a9ae8ba144025b9de30362315 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -91,6 +91,8 @@ package common_pkg is
                rtw_reg2 : std_logic;
                immediate : gp_register_t;
                imm_set : std_logic;
+               reg1_addr : gp_addr_t;
+               reg2_addr : gp_addr_t;
 
        end record;
 

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index b613dcba1ea7f9e954a73d8d7592e75a9b49c337..820a16aeff57f8f6c41501a2fb32a1ba478ca7d7 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -88,7 +88,9 @@ package core_pkg is
                        clk : in std_logic;
                        reset : in std_logic;
                         dec_instr : in dec_op;
-
+                       regfile_val : in gp_register_t;
+                       reg_we : in std_logic;
+                       reg_addr : in gp_addr_t;
                 --System output
                         result : out gp_register_t;--reg
                         result_addr : out gp_addr_t;--reg

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 7a604074b208e1c238bfd9e77452975bc0fa2ac4..8892f758df4bf27b9627c3b61049770f6af59cbe 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -99,7 +99,7 @@ begin
 
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk, sys_res,to_next_stage, result_pin, result_addr_pin,addr_pin,
+                port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
 
           writeback_st : writeback_stage

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index d5ea6474bc1895a83ec620ac6784799030548d63..7d42e8fdf9f56a829512f8072e8e163d331bdcad 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -114,22 +114,22 @@ begin
        dec_op_inst_nxt.src2 <= (others => '0');
        dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr;
        dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
-       dec_op_inst_nxt.daddr <= (others => '0');
+       dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
        dec_op_inst_nxt.op_group <= instr_spl.op_group;
 
 end process;
 
 -- async process: decides between memory and read-through-write buffer on output
-output: process(rtw_rec, reg1_mem_data, reg2_mem_data)
+output: process(rtw_rec, rtw_rec_nxt, reg1_mem_data, reg2_mem_data)
 
 begin
-       if (rtw_rec.rtw_reg1 = '1') then
+       if ((rtw_rec.rtw_reg1) = '1') then
                reg1_rd_data <= rtw_rec.rtw_reg;
        else
                reg1_rd_data <= reg1_mem_data;
        end if;
 
-       if (rtw_rec.rtw_reg2 = '1') then
+       if ((rtw_rec.rtw_reg2) = '1') then
                reg2_rd_data <= rtw_rec.rtw_reg;
        else
                reg2_rd_data <= reg2_mem_data;
@@ -138,6 +138,7 @@ begin
        if (rtw_rec.imm_set = '1') then
                reg2_rd_data <= rtw_rec.immediate;
        end if;
+
 end process;
 
 
@@ -151,6 +152,8 @@ begin
        rtw_rec_nxt.rtw_reg2 <= '0';
        rtw_rec_nxt.immediate <= (others => '0');
        rtw_rec_nxt.imm_set <= '0';
+       rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
+       rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
 
        if (instr_spl.op_detail(IMM_OPT) = '1') then
                rtw_rec_nxt.immediate <= instr_spl.immediate;
@@ -161,7 +164,7 @@ begin
                rtw_rec_nxt.rtw_reg1 <= ('1' and reg_we);
        end if;
 
-       if (reg_w_addr = instr_spl.reg_src2_addr) then
+       if (reg_w_addr = instr_spl.reg_src1_addr) then
                rtw_rec_nxt.rtw_reg2 <= ('1' and reg_we);
        end if;
 

diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd
index c5d6817aa9c957c84bba51182291a0cc2fc9944d..afcf986d20fb60bb5c898edef34d1139309936e7 100644 (file)
--- a/cpu/src/execute_stage.vhd
+++ b/cpu/src/execute_stage.vhd
@@ -20,7 +20,9 @@ entity execute_stage is
                        clk : in std_logic;
                        reset : in std_logic;
                         dec_instr : in dec_op;
-
+                       regfile_val : in gp_register_t;
+                       reg_we : in std_logic;
+                       reg_addr : in gp_addr_t;
                 --System output
                         result : out gp_register_t;--reg
                         result_addr : out gp_addr_t;--reg

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 5979a8b048b917574ddc48f5ac5a6efb3ee51e2f..4d69cee026749452d225597e6c1d981d33d5934f 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -51,14 +51,13 @@ begin
        
 end process;
 
-asyn: process(reset,dec_instr, alu_nxt, psw, reg)
+asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
 begin
 
         condition <= dec_instr.condition;
         op_group <= dec_instr.op_group;
         op_detail <= dec_instr.op_detail;
-        left_operand <= dec_instr.src1;
-        right_operand <= dec_instr.src2;
+        
 
 
         alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); 
@@ -78,6 +77,21 @@ begin
 
 end process asyn;
 
+forward: process(regfile_val, reg_we, reg_addr, dec_instr.src1,dec_instr.src2)
+begin
+       left_operand <= dec_instr.src1;
+        right_operand <= dec_instr.src2;
+
+       if reg_we = '1' then
+               if dec_instr.saddr1 = reg_addr then
+                       left_operand <= regfile_val;
+               end if;
+               if (dec_instr.saddr2 = reg_addr)  and  (dec_instr.op_detail(IMM_OPT) = '0') then
+                       right_operand <= regfile_val;
+               end if;
+       end if;
+end process forward;
+
 result <= reg.result;
 result_addr <= reg.res_addr;
 alu_jump <= reg.alu_jump;

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index 0f1949504fd3f8c59361ffa5b24d169ef15871eb..d51196b00deb2a3869dd20630babf00b6a31b700 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -116,7 +116,7 @@ begin
                );
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin, result_pin, result_addr_pin,addr_pin,
+                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
 
           writeback_st : writeback_stage

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index 9f227364370ad7fa3fcd2658f26553fb1527f73b..c20c8b14ef5ed12e87e6f2b625f993b8ec3e3996 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -13,7 +13,7 @@ architecture behaviour of r2_w_ram is
        signal ram : RAM_TYPE := (
                                0 => x"00000000",
                                1 => x"00000001",
-                               2 => x"FFFFFFFF",
+                               2 => x"0000000A",
                                3 => x"00000003",
                                others=> (others => '0'));
 

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index db886c4f0d076cb08352187a3f2436478b8b9ebe..45779da81a912c35414cb7517c0f4dbe3d5249df 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -10,11 +10,15 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
-                                 1 => "11100101000000001000100000000010",  -- r0 = r1 << 0 (always)
-                                 2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
-                                 3 => "11100000101000000001000000000000",
-                                 4 => "11100001000110010111011001101100", 
+       signal ram : RAM_TYPE := (--0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
+                               --  1 => "11100101000000001000100000000000",  -- r0 = r1 << 0 (always)
+                               --  2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
+                               --  3 => "11100000101000000001000000000000",
+                               --  4 => "11100001000110010111011001101100", 
+                                 0 => "11101100000000001000000000000000", -- cmp r0 , r1 
+                                 1 => "00000000000100000000100000000000",
+                                 2 => "00000000001110000001000000000000",
+                                 3 => "11100001000110010000011001101100", 
                                  others => x"F0000000");
 
 begin