new testbench

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
new file mode 100644 (file)
index 0000000..e32ebbc
--- /dev/null
+++ b/cpu/sim/testcore1.do
@@ -0,0 +1,110 @@
+vlib work
+vmap work work
+
+vcom -work work ../src/mem_pkg.vhd
+vcom -work work ../src/r_w_ram.vhd
+vcom -work work ../src/r_w_ram_b.vhd
+vcom -work work ../src/r2_w_ram.vhd
+vcom -work work ../src/r2_w_ram_b.vhd
+vcom -work work ../src/common_pkg.vhd
+vcom -work work ../src/core_pkg.vhd
+vcom -work work ../src/decoder.vhd
+vcom -work work ../src/decoder_b.vhd
+vcom -work work ../src/fetch_stage.vhd
+vcom -work work ../src/fetch_stage_b.vhd
+vcom -work work ../src/decode_stage.vhd
+vcom -work work ../src/decode_stage_b.vhd
+
+vcom -work work ../src/alu_pkg.vhd
+vcom -work work ../src/extension_pkg.vhd
+vcom -work work ../src/gpm_pkg.vhd
+
+vcom -work work ../src/exec_op.vhd
+vcom -work work ../src/exec_op/add_op_b.vhd
+vcom -work work ../src/exec_op/and_op_b.vhd
+vcom -work work ../src/exec_op/or_op_b.vhd
+vcom -work work ../src/exec_op/xor_op_b.vhd
+vcom -work work ../src/exec_op/shift_op_b.vhd
+
+vcom -work work ../src/alu.vhd
+vcom -work work ../src/alu_b.vhd
+
+vcom -work work ../src/gpm.vhd
+vcom -work work ../src/gpm_b.vhd
+
+vcom -work work ../src/execute_stage.vhd
+vcom -work work ../src/execute_stage_b.vhd
+
+
+vcom -work work ../src/writeback_stage.vhd
+vcom -work work ../src/writeback_stage_b.vhd
+
+vcom -work work ../src/pipeline_tb.vhd
+
+vsim work.pipeline_conf_beh -t ns
+
+add wave  -group system -format logic /pipeline_tb/sys_clk_pin
+add wave  -group system -format logic /pipeline_tb/sys_res_n_pin
+
+add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
+add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
+add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/instr_rd_data
+add wave  -group fetchstageregister -radix hexadecimal /pipeline_tb/fetch_st/instruction
+add wave  -group fetchstage -format logic /pipeline_tb/fetch_st/branch_prediction_bit
+add wave  -group fetchstage -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
+
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instruction
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_dest_addr
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src1_addr
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/instr_spl.reg_src2_addr
+
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_we
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
+add wave  -group decodestage -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
+
+
+
+
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg1
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/rtw_rec.rtw_reg2
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src1
+add wave  -group decodestageregister -radix hexadecimal /pipeline_tb/decode_st/to_next_stage.src2
+
+
+
+
+
+
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.daddr
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr1
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.saddr2
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src1
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/dec_instr.src2
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_we
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_addr
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/regfile_val
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/left_operand
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/alu_inst/right_operand
+add wave  -group execstage -radix hexadecimal /pipeline_tb/exec_st/reg_nxt
+
+
+add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/gpm_inst/psw
+add wave  -group execstageregister -radix hexadecimal /pipeline_tb/exec_st/reg
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/result_addr
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/alu_jmp
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/br_pred
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/write_en
+add wave  -group writebackstage -radix hexadecimal /pipeline_tb/writeback_st/address
+
+add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_we
+add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
+add wave  -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
+
+run 5000 ns

diff --git a/cpu/sim/wave.do b/cpu/sim/wave.do
new file mode 100644 (file)
index 0000000..f56415f
--- /dev/null
+++ b/cpu/sim/wave.do
@@ -0,0 +1,36 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -expand -group system -format Logic /pipeline_tb/sys_clk_pin
+add wave -noupdate -expand -group system -format Logic /pipeline_tb/sys_res_n_pin
+add wave -noupdate -expand -group fetchstage -format Literal -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
+add wave -noupdate -expand -group fetchstage -format Literal -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
+add wave -noupdate -expand -group fetchstage -format Logic /pipeline_tb/fetch_st/branch_prediction_bit
+add wave -noupdate -expand -group fetchstage -format Literal -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/instruction
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/instr_spl
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/rtw_rec_nxt
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
+add wave -noupdate -expand -group decodestage -format Literal -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
+add wave -noupdate -expand -group decodestage -format Logic -radix hexadecimal /pipeline_tb/decode_st/reg_we
+add wave -noupdate -expand -group execstage -format Literal -radix hexadecimal /pipeline_tb/exec_st/gpm_inst/psw
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {0 ns} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {4050 ns} {5050 ns}

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 14846b227dc9cf202181500064fa0dc3c5049968..de4b162427b4b21122656830fb60b70644651a45 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -152,6 +152,7 @@ begin
        rtw_rec_nxt.rtw_reg2 <= '0';
        rtw_rec_nxt.immediate <= (others => '0');
        rtw_rec_nxt.imm_set <= '0';
+--- ???? wieso
        rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
        rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
 

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 45779da81a912c35414cb7517c0f4dbe3d5249df..1c8b21209708acf65e31297b7a2629941c5ad074 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -10,17 +10,29 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := (--0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
-                               --  1 => "11100101000000001000100000000000",  -- r0 = r1 << 0 (always)
-                               --  2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
-                               --  3 => "11100000101000000001000000000000",
-                               --  4 => "11100001000110010111011001101100", 
-                                 0 => "11101100000000001000000000000000", -- cmp r0 , r1 
-                                 1 => "00000000000100000000100000000000",
-                                 2 => "00000000001110000001000000000000",
-                                 3 => "11100001000110010000011001101100", 
+       signal ram : RAM_TYPE := (  0 => "11100000000100001000000000000000", --add r2, r1, r0
+                                   1 => "11100000000110001000000000000000", --add r3, r1, r0
+                                   2 => "11100000001000011001000000000000", --add r4, r3, r2
+                                   3 => "11100000000100001000000000000000", --add r2, r1, r0
+                                   4 => "11100000000110001000000000000000", --add r3, r1, r0
+                                   5 => "11100000001000011001000000000000", --add r4, r3, r2
+                                   6 => "11101100000000001000000000000000", --cmp r0 , r1 
+                                   7 => "00000000001010101010000000000001", --addnqd r5, r5, r4
+                                   8 => "00000000001010101010000000000000", --addnq r5, r5, r4
+                                   9 => "11101100001000100000000000000000", --cmp r4 , r4 
+                                  10 => "00000001001100001000000001010000", --addinq r5, r1, 10
+                                  11 => "00010001001100001000000001010000", --addieq r5, r1, 10 
+                                  12 => "00010001101100110000000001010000", --subieq r5, r5, 10
+                                  13 => "11100000000100001000000000000000", --add r2, r1, r0
+                                  14 => "11100010000100001000000000000000", --and r2, r1, r0
+                                  15 => "11101100000000001000000000000000", --cmp r0 , r1 
+                                  16 => "10000000001010101010000000000001", --addabd r5, r5, r4
+                                  17 => "10110011101110001000010000110001", --orxltd r7, 1086
+                                  18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1
+                                  19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2
                                  others => x"F0000000");
 
+
 begin
        process(clk)
        begin