exec impl.

diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd
index b94421acee0b5df956606d73b5914eca019cb654..8928ece1cc6a76f220f83bc4b028632cb8de1db5 100755 (executable)
--- a/cpu/src/alu.vhd
+++ b/cpu/src/alu.vhd
@@ -13,7 +13,7 @@ entity alu is
                        clk : in std_logic;\r
                        reset : in std_logic;\r
        --operation inputs\r
-                       condition       :       condition_t;\r
+                       condition : in condition_t;\r
                        op_group : in op_info_t;\r
                        left_operand : in gp_register_t;\r
                        right_operand : in gp_register_t;\r

diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd
index 05e040d1a8873303a02b259c5213b37292018ea7..088565bd28342f3d18c6aa04e1353e79367ce38a 100755 (executable)
--- a/cpu/src/alu_pkg.vhd
+++ b/cpu/src/alu_pkg.vhd
@@ -26,14 +26,14 @@ package alu_pkg is
                result_addr : gp_addr_t;\r
                \r
                status : status_rec;\r
-               stackpointer : gp_register_t;\r
+               --stackpointer : gp_register_t;\r
 \r
                alu_jmp : std_logic;\r
-               brpr_bit : std_logic;\r
+               brpr : std_logic;\r
                reg_op : std_logic;\r
                mem_op  : std_logic;\r
                \r
-               new_val : std_logic;\r
+               --new_val : std_logic;\r
                mem_en : std_logic;\r
                \r
                hw_op   : std_logic;\r
@@ -71,7 +71,24 @@ package alu_pkg is
        -- function xor_op(left_operand, right_operand : gp_register_t; alu_result : alu_result_rec) return alu_result_rec;\r
        \r
        -- function shift_op(left_operand, right_operand : gp_register_t; arith,sleft,carry : std_logic ;alu_result : alu_result_rec) return alu_result_rec;\r
-       \r
+       
+        component alu is
+        --some modules won't need all inputs\r
+       port(\r
+       --System inputs\r
+       \r
+                       clk : in std_logic;\r
+                       reset : in std_logic;\r
+       --operation inputs\r
+                       condition : in condition_t;\r
+                       op_group : in op_info_t;\r
+                       left_operand : in gp_register_t;\r
+                       right_operand : in gp_register_t;\r
+                       op_detail : in op_opt_t;\r
+                       alu_state  : in alu_result_rec;\r
+                       alu_result : out alu_result_rec\r
+               );
+        end component alu;\r
        \r
 end package alu_pkg;\r
 \r

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index 1dca19632fab15a7625d759cf73a44a7c598eb4d..30466513ec0404b5574ec8f5f7dd36ffcd5470df 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -49,11 +49,11 @@ package common_pkg is
        constant IMM_OPT : integer := 0; -- no sharing
        
        constant SUB_OPT : integer := 1;
-       constant LOG_OPT : integer := 1;
+       constant ARITH_OPT : integer := 1;
        
        constant CARRY_OPT : integer := 2;
        
-       constant LEFT_OPT : integer := 3;
+       constant RIGHT_OPT : integer := 3;
        
        constant NO_PSW_OPT : integer := 4;--no sharing
        constant NO_DST_OPT : integer := 5; --no sharing

diff --git a/cpu/src/exec_op/shift_op_b.vhd b/cpu/src/exec_op/shift_op_b.vhd
index 0b5a73cb80bc72677b6bb8dedb511f0b2d509d31..2d5311d5ef40b15eeac940dd8861c5857304acb3 100755 (executable)
--- a/cpu/src/exec_op/shift_op_b.vhd
+++ b/cpu/src/exec_op/shift_op_b.vhd
@@ -11,30 +11,29 @@ architecture shift_op of exec_op is
 
 begin
 
-       logic <=  op_detail(LOG_OPT);
-       ls      <=  op_detail(LEFT_OPT);
+       arith <=  op_detail(ARITH_OPT);
+       rs      <=  op_detail(RIGHT_OPT);
        carry <= op_detail(CARRY_OPT);
 
-calc: process(left_operand, right_operand, logic,ls, carry, alu_state)
+calc: process(left_operand, right_operand, arith,rs, carry, alu_state)
                variable alu_result_v : alu_result_rec;
                variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
                variable tmp_sb : std_logic;
-       begin
+begin
                alu_result_v := alu_state;
                
-               if ls = '1' then
-                       tmp_sb := (carry and alu_state.status.carry and logic);
-                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
-                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
-                       
-                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
-                       
-               else
-                       tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));
+                if rs = '1' then   
+                       tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));
                        tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
                        tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
                        
                        alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
+               else 
+                       tmp_sb := (carry and alu_state.status.carry and not(arith));
+                       tmp_shift :=  to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
+                       tmp_shift :=  tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+                       
+                       alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
                end if;
                
                alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);

diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd
index d69fdc05c9a8481d21bf3f8e4f318bed19dafeea..925c579ff6526fafbf2cefb44c3758193057aaa0 100644 (file)
--- a/cpu/src/execute_stage.vhd
+++ b/cpu/src/execute_stage.vhd
@@ -15,6 +15,7 @@ entity execute_stage is
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+                        dec_instr : in dec_op
                );
                
 end execute_stage;

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 6b6b6215aa79f3ff22518d3566529e26bde35ce8..095d4dc5e813bc1a00a3be9882ca5d49261199cc 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -2,24 +2,60 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
-use work.core_pkg.all;
+use work.common_pkg.all;
+use work.alu_pkg.all;
 
 architecture behav of execute_stage is
 
+signal condition : condition_t;
+signal op_group : op_info_t;
+signal op_detail : op_opt_t;
+signal left_operand, right_operand : gp_register_t;
+signal alu_state, alu_nxt : alu_result_rec;
+
+signal psw : status_rec;
 
 begin
 
+alu_inst : alu
+port map(clk, reset, condition, op_group, 
+        op_detail, left_operand, right_operand, alu_state, alu_nxt);
+
 syn: process(sys_clk, reset)
 
 begin
 
        if (reset = RESET_VALUE) then
-                               
+               condition <=                    
        elsif rising_edge(sys_clk) then
                
        end if;
        
-end process; 
+end process;
+
+asyn: process(reset,condition)
+begin
+
+        condition <= dec_instr.condition;
+        op_group <= dec_instr.op_group;
+        op_detail <= dec_instr.op_detail;
+        left_operand <= dec_instr.src1;
+        right_operand <= dec_instr.src2;
+
+        alu_state.status <= psw;
+        alu_state.result_addr <= dec_instr.daddr;
+        alu_state.brpr <= brpr;
+        alu_state.reg_op <= '0';
+        alu_state.mem_op <= '0';
+        alu_state.
+
+        if reset = RESET_VALUE then
+                condition <= COND_NEVER;
+        else
+                
+        end if;
+
+end process asyn;
 
 end behav;
 

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
new file mode 100644 (file)
index 0000000..bf58a27
--- /dev/null
+++ b/cpu/src/extension_pkg.vhd
@@ -0,0 +1,23 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+
+
+package extension_pkg is
+
+        type extmod_rec is record
+                clk : std_logic;
+                reset : std_logic;
+                sel   : std_logic;
+                
+                wr_en : std_logic;
+                byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
+                data : data_ram_word_t;
+                addr : data_addr_t;          
+        end record; 
+       
+       
+end package extension_pkg;

diff --git a/cpu/src/gpm.vhd b/cpu/src/gpm.vhd
new file mode 100644 (file)
index 0000000..7bba400
--- /dev/null
+++ b/cpu/src/gpm.vhd
@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+use work.extension_pgk.all;
+
+entity gpm is
+
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic;
+                       -- active logic value
+                       LOGIC_ACT : std_logic
+                       
+                       );
+       port(
+               --System inputs
+                clk : in std_logic;
+               reset : in std_logic;
+
+                exti : in extmod_rec;
+                --alu outpus
+                alu_nxt : in alu_result_rec;
+                --input
+                
+                --output
+                psw     : out status_rec;
+                --to memcnt
+                addr : out gp_register_t;
+                mem_en : out std_logic;
+                ldst : out std_logic;
+                --, hw,byte: std_logic;
+                --to output bus
+                exto : out data_ram_word_t
+                        
+        );
+               
+end gpm;