nop insertion added

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 13ac38243997008feb252339661fa1bd8eea3c1b..b613dcba1ea7f9e954a73d8d7592e75a9b49c337 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -52,6 +52,7 @@ package core_pkg is
                        reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                        reg_wr_data : in gp_register_t;
                        reg_we : in std_logic;
+                       nop : in std_logic;
 
                --Data outputs
 --                     reg1_rd_data : out gp_register_t;

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index f146d8d4855b42b36a6c7889fcdf834255efecb5..7a604074b208e1c238bfd9e77452975bc0fa2ac4 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -44,6 +44,7 @@ architecture behav of core_top is
                  signal dmem_wr_en_pin : std_logic;
                  signal hword_pin  : std_logic;
                  signal byte_s_pin : std_logic;
+                signal nop_pin : std_logic;
 
 
 begin
@@ -88,6 +89,7 @@ begin
                        reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                        reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
                        reg_we => reg_we_pin, --: in std_logic;
+                       nop => nop_pin,
 
                --Data outputs
                        branch_prediction_res => prediction_result_pin, --: instruction_word_t;
@@ -119,5 +121,6 @@ begin
 --end process;
        
        result <= result_pin;
+       nop_pin <= (alu_jump_bit_pin xor brpr_pin);
 
 end behav;

diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd
index 103822cb0463fef2d39433f637a01e5db047bede..e99825d0b9e5bd207929b439c68cc7556225b45a 100644 (file)
--- a/cpu/src/decode_stage.vhd
+++ b/cpu/src/decode_stage.vhd
@@ -25,6 +25,7 @@ entity decode_stage is
                        reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                        reg_wr_data : in gp_register_t;
                        reg_we : in std_logic;
+                       nop : in std_logic;
 
                --Data outputs
 --                     reg1_rd_data : out gp_register_t;

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index b0ae0dd787eba34a5effccd7011d6ec2684fafa0..c045d6a8ce2e46d3c7e78ab2f7c82a8f0595b48c 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -311,6 +311,9 @@ begin
 
                        instr_s.op_detail(IMM_OPT) := '1';
                end if;
+               instr_s.op_detail(NO_DST_OPT) := '1';
+               instr_s.op_group := ADDSUB_OP;
+               instr_s.op_detail(SUB_OPT) := '1';
 
        end if;
 

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index c1c6b0c79f978416379359ce24f45f9a995a5f47..0f1949504fd3f8c59361ffa5b24d169ef15871eb 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -47,6 +47,7 @@ architecture behavior of pipeline_tb is
                  signal dmem_wr_en_pin : std_logic;
                  signal hword_pin  : std_logic;
                  signal byte_s_pin : std_logic;
+                signal nop_pin : std_logic;
 
 begin
 
@@ -105,6 +106,7 @@ begin
                        reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                        reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
                        reg_we => reg_we_pin, --: in std_logic;
+                       nop => nop_pin,
 
                --Data outputs
                        branch_prediction_res => prediction_result_pin, --: instruction_word_t;
@@ -124,6 +126,7 @@ begin
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 
 
+       nop_pin <= (alu_jump_bit_pin xor brpr_pin);
 
 -------------------------------------------------------------------------------
 -- generate simulation clock

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index a0b163939bd2667f73fc2311d1a82e5211a62d50..9f227364370ad7fa3fcd2658f26553fb1527f73b 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -15,7 +15,7 @@ architecture behaviour of r2_w_ram is
                                1 => x"00000001",
                                2 => x"FFFFFFFF",
                                3 => x"00000003",
-                               others=> x"00000000");
+                               others=> (others => '0'));
 
 begin
        process(clk)

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 3664ea109adc72d064b8d5dedf146f016eee0683..db886c4f0d076cb08352187a3f2436478b8b9ebe 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -15,7 +15,7 @@ architecture behaviour of r_w_ram is
                                  2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
                                  3 => "11100000101000000001000000000000",
                                  4 => "11100001000110010111011001101100", 
-                                 others => x"E0000000");
+                                 others => x"F0000000");
 
 begin
        process(clk)