ldi add finished

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 1bb83deb477674721e073482c8e639a1aedd5f36..634c7d1605504d5127b136c82c8828fc3fbcdb9a 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -102,7 +102,7 @@ begin
                result_v := shift_result;
         when LDST_OP =>
                 if op_detail(IMM_OPT) = '1' then
-                        result_v := right_operand;
+                        result_v.result := right_operand;
                 end if;\r
        end case;\r
        \r

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index ab0ee7e075d533ef3482b9a59c2506dd62d6ac34..d1b49c1da4a6e5d4ad6a28ae0aee51b4d2be2b01 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -225,8 +225,8 @@ begin
                        if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
                                instr_s.immediate(31 downto 16) := (others => '1');
                        end if;
-                       instr_s.immediate(14 downto 0) := instruction(14 downto 0);
-                       instr_s.immediate(WORD_WIDTH-1 downto 15) := (others => '0');
+                       instr_s.immediate(11 downto 0) := instruction(14 downto 3);
+                       instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0');
                        instr_s.op_detail(IMM_OPT) := '1';
                end if;
        end if;

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 4f1a0e0e8d8080bf4ea0e40e91ca9e46c06873fb..6db0659bae58fa5baa8f7ac2a2f20d9db6ddf7ac 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -12,9 +12,9 @@ architecture behaviour of r_w_ram is
        
                                                                        -- r0 = 0, r1 = 1, r2 = 3, r3 = A
 
-       signal ram : RAM_TYPE := (  0 => "11100001000010001000000000111000", -- r1 = 7
-                                   1 => "11100001000100010000000000101000", -- r2 = 5
-                                   2 => "11100001000110011000000000100000", -- r3 = 4
+       signal ram : RAM_TYPE := (  0 => "11101101000010000000000000111000", -- r1 = 7
+                                   1 => "11101101000100000000000000101000", -- r2 = 5
+                                   2 => "11101101000110000000000000100000", -- r3 = 4
                                    3 => "11100000001000010001100000000000", -- r4 = r2 + r3
                                    4 => "11100010001010100000100000000000", -- r5 = r4 and r1
                                  others => x"F0000000");