Remove lib/ramtest.c-include from all CAR boards.

Remove many more .c-includes from i945 based boards.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 26ab1a7d73d76f14052de21e8643f8872615fdb6..ed52ea940cfe867fe6889160e729b9ff6d8634d3 100644 (file)
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -21,6 +21,7 @@ romstage-y += memcpy.c
 romstage-y += memcmp.c
 romstage-y += cbfs.c
 romstage-y += lzma.c
+romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 #romstage-y += lzmadecode.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c

diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index abda1065aa3b1defe9e1d3d9fbfc46a85b29953f..3f4657fa8f2b5b8f9773e199ee25cb63c7dfa758 100644 (file)
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -1,4 +1,6 @@
+#include <stdint.h>
 #include <lib.h> /* Prototypes */
+#include <console/console.h>
 
 static void write_phys(unsigned long addr, u32 value)
 {

diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index 48b3ede433b55addd3e56079dc96d5c13473ac07..0f2ec7fce0b0f66ffc84f70a4d1e8af4376812c6 100644 (file)
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -25,7 +25,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index ad0d741762b8292930df8d4328db4f7883243bf2..d5a907c64ed6d2aafabbecacaf5c5aa5f45580c5 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -45,10 +45,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index ff6621964f2894e45bdb307373d09d00fcadc5d8..841c8a246e6771cbdc2a0851d4ee88a138a81c46 100644 (file)
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -25,7 +25,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index 4a68859fd21dcfda25288a31e89c77c94dac58d2..8ff4ac46a788691810cdf3b0e9cd95dd5198641a 100644 (file)
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -4,7 +4,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index b0a0f088296be9a0b2de763554ba38b510d4c8d4..910c9633a32337d687432f8c7e71771245c3d14b 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -45,11 +45,11 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 536fe54c121e983a609cc81eb53463651c14a39b..1e331fe7170f8897b5475a28bc75aa353d0c54d0 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -45,10 +45,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c
index 78332f838a92ad55865bf3796a415443b787e2c0..f5c738745acb41081b22f116e9f9f57f10cb5a50 100644 (file)
--- a/src/mainboard/arima/hdama/romstage.c
+++ b/src/mainboard/arima/hdama/romstage.c
@@ -7,7 +7,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 4e9c9788f731242b0121323520374dcceb05fe06..dc4e3ffe26d254dcc3b7365e804fd7af7b27072b 100644 (file)
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 4b101d1c9cb50b0d31d786b102de28ce327d788e..0f2a5c888ac5486d03631420e20799f4e82e9be6 100644 (file)
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -48,7 +48,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 3df523cec6f3629b293165d91457e16cdf4333aa..cae04485a62d2fbdca09e60bc0a2a89169362188 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -45,10 +45,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 4695f4e1cd6d3e428ffd16e885716d2fee9125c7..fea599b2a63a2361ead22005f36342437cf28948 100644 (file)
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -27,11 +27,11 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
+#include <lib.h>
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)

diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index 47b9fd24d749f13c222105de2991a5f48d991a67..5a9b3ebeba610783126c4218efd8c27dfc893d0d 100644 (file)
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -13,7 +13,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index 097ecde8f1b8c24c5445f7027474736443dda27d..40a06264013e66ca55299d25174c64e8d2b440a5 100644 (file)
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -8,7 +8,6 @@
 #include "pc80/udelay_io.c"
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"

diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 07c4c4d43875f0463d051c8b192aaf2b9514e976..3b2d8f1dbb1dd6a6f742f01152ebaa34e4d99449 100644 (file)
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -6,7 +6,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 8a39d997fa2599aeee08319d97fa30d98b5ec659..bf11cb5227d013610219ab392c5c9945330c9afc 100644 (file)
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -26,24 +26,20 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <lib.h>
 
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
-#include "northbridge/intel/i945/udelay.c"
+void enable_smbus(void);
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
 {
        u32 gpios;
 
@@ -87,18 +83,6 @@ static void setup_ich7_gpios(void)
        outl(gpios, DEFAULT_GPIOBASE + 0x0c);   /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index cf5c6bda264c20b8c0ea4194006ffc925e9b1054..7692c08bcf07f6d9ed3b7dea17ab7ce4a9efbb0b 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -55,7 +55,6 @@
 #include "southbridge/sis/sis966/sis966_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index be5e46ba1a44013864f4b93eb519b1f57e13e9d1..59174d7e5642484f8fd0614a42bbe36ba6e1b13b 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -53,7 +53,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 55e1b624920e57346ad1f15a4e6347cdcbdcee9a..c97f275027401a04b57bdb9c15aec422ff7af943 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -41,10 +41,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 9569556228104c20de4e71e712d4ad0c79895b41..9225e2616e7b8eaabacf7359190205e64169fe49 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -45,10 +45,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 9c126af36db58a81b0f889a6a5b59e3d4c5058df..37a820ba37465455d78ac105caa0caea2112ec38 100644 (file)
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -13,7 +13,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 8f3e21ddbe496f08e88b865fe9a635aa5c3d0d59..f3555b63f857eeacb76856a224ca795ef67db793 100644 (file)
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -55,7 +55,6 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 74ded075e9774ded9ec2be8b3f8af754973aa6a4..41c151e4237162d5043e55c09d3cfaa0c7dbe093 100644 (file)
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -49,11 +49,11 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/amd/model_10xxx/apic_timer.c"
 #include "lib/delay.c"

diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 53750dfc080a2ff1efb8204b8b7daba22c27ddbe..cd131705b9b4aa47989235db8b33f5978a6bbf6e 100644 (file)
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <lib.h>
 
 #include "superio/winbond/w83627ehg/w83627ehg.h"
 
@@ -34,21 +35,17 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 
-#include "northbridge/intel/i945/udelay.c"
-
 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
 
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+
+void enable_smbus(void);
+
+void setup_ich7_gpios(void)
 {
        printk(BIOS_DEBUG, " GPIOS...");
        /* General Registers */
@@ -64,18 +61,6 @@ static void setup_ich7_gpios(void)
        outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ

diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c
index a05feea6b8e31e97ff8d342156680edfe7464baa..f43a69ffc044d5f5bc46f1508a0ecceb76e98116 100644 (file)
--- a/src/mainboard/ibm/e325/romstage.c
+++ b/src/mainboard/ibm/e325/romstage.c
@@ -9,7 +9,6 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index 859368962027a7d2aba1549a055cf89d9dd84684..9656abaabcc2f3cd6503066822944c4683f420a7 100644 (file)
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -9,7 +9,6 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 96a4595cb6b66130521a0de06d87f439b4875e40..d9790b37cd33298dc65194d087ec209c72d35e81 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -48,10 +48,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index 35d16eaac2558fab583570397de63ddc9f8f2a67..e3351f12949f978b8c0182e5b675a56a46dcee2d 100644 (file)
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -25,7 +25,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c
index 1cfe50554feb4fe76f62f38e2c94ad8691356152..34371f5834f00046b43ee749bcf3bc0cb2a55693 100644 (file)
--- a/src/mainboard/intel/d810e2cb/romstage.c
+++ b/src/mainboard/intel/d810e2cb/romstage.c
@@ -26,7 +26,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801bx/i82801bx.h"
 #include "southbridge/intel/i82801bx/i82801bx_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
@@ -36,6 +35,7 @@
 #include "cpu/x86/bist.h"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "gpio.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index dd6f3836b8cadc5f37cea8921a092755cf85ea5c..9b7f2deeee9550c6a3e1e8ec5d7f7f36c098fac6 100644 (file)
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <lib.h>
 
 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
 
@@ -34,21 +35,17 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
 #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
 
-#include "northbridge/intel/i945/udelay.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+
+void enable_smbus(void);
+
+void setup_ich7_gpios(void)
 {
        /* TODO: This is highly board specific and should be moved */
        printk(BIOS_DEBUG, " GPIOS...");
@@ -65,18 +62,6 @@ static void setup_ich7_gpios(void)
        outl(0x000300fd, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 0c29984049603f314144619ebcf8ebfdb620e09c..fe981d6c0a48dc9f0328c167498979330b77d8a6 100644 (file)
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -34,7 +34,6 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "reset.c"

diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 510f1ed609358179e91e6a22b094108416eec5f3..89fb5439efa4158ef168615c4050c856480c9229 100644 (file)
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -28,7 +28,6 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "northbridge/intel/i3100/raminit.h"

diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 8fea9d9abffeb3041f1ce2b2539c1f9d34b42fb5..7d22ad204e210d9ad2c25088eed31e9c63713a25 100644 (file)
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -91,7 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "lib/ramtest.c"
 
  /* tyan does not want the default */
 #include "resourcemap.c"

diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 77691a6ce2cc0e2c5b6e3865399ddf52832ee42a..43079accf85698fff6adc976011484a04d287720 100644 (file)
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -91,7 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "lib/ramtest.c"
 
  /* tyan does not want the default */
 #include "northbridge/amd/amdk8/resourcemap.c"

diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 77691a6ce2cc0e2c5b6e3865399ddf52832ee42a..43079accf85698fff6adc976011484a04d287720 100644 (file)
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -91,7 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "lib/generic_sdram.c"
-#include "lib/ramtest.c"
 
  /* tyan does not want the default */
 #include "northbridge/amd/amdk8/resourcemap.c"

diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index ee2dd97772286708aaf498bb6955f1a044746a48..1fa2f0857b72809b29f896c942cc9fc817d577e1 100644 (file)
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -27,13 +27,13 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/fintek/f71805f/f71805f_early_serial.c"
+#include <lib.h>
 
 #if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2)

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index f96797d8c05d139924e765c8d28260850aad1a3c..fc18ba98875d5612b8b375251b25557f2fca99aa 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -46,10 +46,10 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"

diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index c6ea1b10d6945878f61293180bd12bbb7b04a566..201d90378fe28f5c0cc6cccb7b3751f6fb22b90d 100644 (file)
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -21,6 +21,7 @@
 
 #include <stdint.h>
 #include <string.h>
+#include <lib.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 #include <device/pci_def.h>
@@ -35,21 +36,17 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
 
-#include "northbridge/intel/i945/udelay.c"
+void enable_smbus(void);
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
 
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
 #include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+
+void setup_ich7_gpios(void)
 {
        printk(BIOS_DEBUG, " GPIOS...");
        /* General Registers */
@@ -65,18 +62,6 @@ static void setup_ich7_gpios(void)
        outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ

diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index 9a33fa881220064a4f62a901448dfb1f851ed89b..6d79e0b3e52ec29a31e00c595b6436cd40d766f3 100644 (file)
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -30,7 +30,6 @@
 #include "pc80/udelay_io.c"
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"

diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index 64f1d7b6dc4d26bd91ce8c46dab268b72db69542..df301fcaddf52005b3a729597d51d502ca56179c 100644 (file)
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -4,7 +4,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 92f0f0f6f1d6ddf8da0b1185126235c0178b6ceb..018f353fd021ee345c2418b3304944465e124685 100644 (file)
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -28,7 +28,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 8ef9fc651a5bea1c6fc62a597f113a1ec14816eb..9052cb39c283b510049f225e4fa9cf6162467a85 100644 (file)
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -29,7 +29,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 7429e4682cc70116b5adea36aac5e6ca7402808a..11524c4f4c5a38a2922e46842d80004a937abccd 100644 (file)
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -28,7 +28,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 66d92b34eb9d05fba34490ed2f17e393dabd7589..2992bcc9db2d9f0c9a7e68faa6baa39f77566816 100644 (file)
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -29,7 +29,6 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 50e75285aa34766a32cb14d84bdd75b08f8f6e85..25c42014b4639b5ab5067f7ce002a49cf5e788d7 100644 (file)
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -49,7 +49,6 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 2605a16c3fc30cf2081c3778f234942bb4056d92..53a6aae241a9bbc8a895267376ffcb809e718577 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -56,12 +56,12 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
+#include <lib.h>
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 2c448bd2042bab38a1fd6343cdf286e792e00f74..0bc38368095352e12c331a1ed2f2f54dbcc1d5e4 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -46,7 +46,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>
 

diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index 72761f3907921bcb4e99215242cd755414b88f8c..b1ec136fde2e472f7efeae8b5e721523fa2a9994 100644 (file)
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -14,7 +14,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index bdc681008606fade732316034aabb94fd65d8582..7917a3db014afff1fab7e7a4f52814427eda7894 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -53,7 +53,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 6ec9557aac16d184e53c6e9ef6ac0396ef3fc9e4..f0c4ed63254bc984bcd46b40f8cc79cf7b130078 100644 (file)
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 1c00f8781edb0903ce60cf378b2b94e5079e3393..aa5f7a0fc40ed58b0549876360f420bdbf2b91cb 100644 (file)
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index 908722a55f1dab10a6e564e5cbed0a4048627102..c838da1f1a73ac52b053a022767f573d0d94f71d 100644 (file)
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/hlt.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"

diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 98ebadbc22bcc80ac6d34602de5f4ca5782c684d..4942788420b025bf4fdf377f578ffd2414bde792 100644 (file)
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -28,24 +28,20 @@
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
+#include <lib.h>
 
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 
-#if CONFIG_USBDEBUG
-#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
-
-#include "lib/ramtest.c"
-#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
+#include "northbridge/intel/i945/i945.h"
+#include "northbridge/intel/i945/raminit.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
 
-#include "northbridge/intel/i945/udelay.c"
+void enable_smbus(void);
 
-#include "southbridge/intel/i82801gx/i82801gx.h"
-static void setup_ich7_gpios(void)
+void setup_ich7_gpios(void)
 {
        printk(BIOS_DEBUG, " GPIOS...");
        /* General Registers */
@@ -61,18 +57,6 @@ static void setup_ich7_gpios(void)
        outl(0x00010030, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
 }
 
-#include "northbridge/intel/i945/early_init.c"
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i945/raminit.h"
-#include "northbridge/intel/i945/raminit.c"
-#include "northbridge/intel/i945/errata.c"
-#include "northbridge/intel/i945/debug.c"
-
 static void ich7_enable_lpc(void)
 {
        // Enable Serial IRQ

diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index 9139e78a02f14ab5fa2bbfa1c72d476fe99db374..86a194c73507008ee72068bc33e4b7f4c5f99b18 100644 (file)
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -16,7 +16,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index b55ebc275c3f7ffbbebcd997fa01f45a7d45d977..0d687032f16b7d0eeb81156af644fcb8c2721fea 100644 (file)
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -46,7 +46,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index ca4c8eec74af6026a0ae174ebb358e126de898a0..3a3140d10667d697ca09f3c4e9f4600c132b12a6 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -49,7 +49,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index f14ae5f1ad52270aa8b7117b1b90c14668126dce..61340cf2c654f57b9a44ed73b1c545e6c81168d3 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -43,7 +43,7 @@
 #include <cpu/x86/lapic.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>
 

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index b400279653a7f89c26aea8e2639bb2fc194d7127..4c1c4861877ae52f6186f038150678664c104c9b 100644 (file)
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -43,7 +43,7 @@
 #include <cpu/x86/lapic.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>
 

diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
index 9d37e00adccdce43a6539bf291e379075f5d2c48..515059ac0971afa67bf25bc2fd7d6e281f17b88c 100644 (file)
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ b/src/mainboard/thomson/ip1000/romstage.c
@@ -28,7 +28,7 @@
 #include <arch/llshell.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"
 #include "northbridge/intel/i82830/memory_initialized.c"

diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index 36c1e2c071c1fefde39632e4347e378a12531e15..d3832702855accb7f8d3b7a7229ad2ead671533d 100644 (file)
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -25,7 +25,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c
index ddbc03d2a6e17ba6e9200637b372b6e392686ab3..d117112c3dda4bc4995b157f52a9019b1101a417 100644 (file)
--- a/src/mainboard/tyan/s2735/romstage.c
+++ b/src/mainboard/tyan/s2735/romstage.c
@@ -8,7 +8,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"

diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index 434e85d58ccaa39b351772c4b66ab5b2e4a35e1e..582f9841f81cd3dff61b13748ccc81647fe4f149 100644 (file)
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 85f365eaeed9e76e12f88a1d3657debf27e1c0b7..340362a72c24cddda92eaa4864c6fbdde27c3a7f 100644 (file)
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index 0e6612aa8c1a011e87aeade465276fbed031ecb7..98818a83001b3952fed100ec80577a6942a0920a 100644 (file)
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index 517ffe4302f6df73692b978640cc6c933d6ef960..61515281e90f9d06b6260d2e48af56400962ce42 100644 (file)
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -13,7 +13,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index ca12a0794fb0000b7a4f28f9102cd2977950a770..92c1a93aecade638b24b6e5ceef17a7befed7212 100644 (file)
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index 8ebd9cdb5e0f4764b2c5d88ba8e337d28edddd2a..816b49e6970d1c5e478bcec37706efe0e4fe5789 100644 (file)
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -8,7 +8,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index 4fce367322fcf7758b7688a46d152e889239c5d9..7270384c7f440234c44f7ab6b0113c712258dc70 100644 (file)
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -14,7 +14,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
index 7edbf3b9271ef5070227e2350acd7202fdb5dd15..cf601cc050852c83e7aa71d2853c274f6691e113 100644 (file)
--- a/src/mainboard/tyan/s2892/romstage.c
+++ b/src/mainboard/tyan/s2892/romstage.c
@@ -14,7 +14,7 @@
 #include <pc80/mc146818rtc.h>
 
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index a8efb908ff0f2088ad1b801f1a6f2460cd9d2038..be170802b84de6b60fffaaee50379141c8684676 100644 (file)
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -15,7 +15,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"

diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 695d2cbe8a19b3f961e4ac1c51c5b78ac028eada..2d3e12643e427d7ec48b23609e3c228541d0f075 100644 (file)
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -53,7 +53,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index ed79299e8c62033927293fda5b47af98acbbfde9..b294c7e51c5ac232124d9050bc6c5d2abd935e4f 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -46,7 +46,7 @@
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
 #include "pc80/usbdebug_serial.c"
 #endif
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_10xxx_rev.h>
 

diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 7328cb4a267f45cdaffc81b12542184113e8bbcd..c5cc6b1ad2336a72f3420b308edcf173cb6b1cbb 100644 (file)
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -9,7 +9,7 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index 10537565e053705cf533b47252233706f8105dd1..f32941a9ba25421caefeec0ad003df3820332991 100644 (file)
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -8,7 +8,7 @@
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"

diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 063fd1afa36aa2ed21992edabedf5c980e80e42a..06562176d00fbdf0e5d5ba98402943c212bc97da 100644 (file)
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"

diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 479305fa2e92875c078f13e1600e811627677965..caee4574a859d38bd731c54e552cff246e8ac39a 100644 (file)
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -33,7 +33,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "northbridge/via/vx800/vx800.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"

diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index 5da421c7e600f9119e8c7f04be640fdf8e982340..5f4c67b33d35d498117c8ba8e082ae0462e9c8f3 100644 (file)
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"

diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index ba96cdb5170841c8923376bf382cb8861109a697..e7361b7f73dec36e84aa889d0a1292ee32287660 100644 (file)
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -27,7 +27,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "northbridge/via/cx700/raminit.h"
 #include "cpu/x86/bist.h"
 

diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 12945e3fddffe698cbab5cd61b38c2fa9af7e96a..76428c5357be33d7cfabada53d7b5ddbd842d42d 100644 (file)
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -26,7 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/lxdef.h>

diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index 9b884ec833fce45c3c7230d9fce97fae2aaaeee4..d36173cee15fcb7fc263441d5efe8b3e042a0262 100644 (file)
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -25,7 +25,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
+#include <lib.h>
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
 #include <cpu/amd/gx2def.h>

diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 57362c6c478aff6072a4b57bece0f154bc0146fe..1dd8d117eab256fa99376ef04b8a939e459d3a12 100644 (file)
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -20,3 +20,9 @@
 driver-y += northbridge.c
 driver-y += gma.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+romstage-y += udelay.c
+romstage-y += raminit.c
+romstage-y += early_init.c
+romstage-y += errata.c
+romstage-y += debug.c

diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index dd095ca7b37f1c6a896fcff96b5422355837bde6..8dc76fe44755fb9102b9355ba2a33d40c98edaa3 100644 (file)
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -19,11 +19,18 @@
  * MA 02110-1301 USA
  */
 
+#include <lib.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
+#include "i945.h"
+
 #define SMBUS_MEM_DEVICE_START 0x50
 #define SMBUS_MEM_DEVICE_END 0x53
 #define SMBUS_MEM_DEVICE_INC 1
 
-static inline void print_pci_devices(void)
+void print_pci_devices(void)
 {
        device_t dev;
        for(dev = PCI_DEV(0, 0, 0);
@@ -42,7 +49,7 @@ static inline void print_pci_devices(void)
        }
 }
 
-static inline void dump_pci_device(unsigned dev)
+void dump_pci_device(unsigned dev)
 {
        int i;
 
@@ -61,7 +68,7 @@ static inline void dump_pci_device(unsigned dev)
        }
 }
 
-static inline void dump_pci_devices(void)
+void dump_pci_devices(void)
 {
        device_t dev;
        for(dev = PCI_DEV(0, 0, 0);
@@ -78,7 +85,7 @@ static inline void dump_pci_devices(void)
        }
 }
 
-static inline void dump_spd_registers(void)
+void dump_spd_registers(void)
 {
         unsigned device;
         device = SMBUS_MEM_DEVICE_START;
@@ -103,7 +110,7 @@ static inline void dump_spd_registers(void)
        }
 }
 
-static inline void dump_mem(unsigned start, unsigned end)
+void dump_mem(unsigned start, unsigned end)
 {
         unsigned i;
        print_debug("dump_mem:");

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index c892216dea9cf1459319ad4b1f35efd46de72099..e301f8a019c13d56fe0e0bfc8b488262036aeac1 100644 (file)
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -17,10 +17,16 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
 #include "i945.h"
 #include "pcie_config.c"
 
-static int i945_silicon_revision(void)
+int i945_silicon_revision(void)
 {
        return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION);
 }
@@ -856,7 +862,7 @@ static void ich7_setup_pci_express(void)
        pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
 }
 
-static void i945_early_initialization(void)
+void i945_early_initialization(void)
 {
        /* Print some chipset specific information */
        switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) {
@@ -879,7 +885,7 @@ static void i945_early_initialization(void)
        RCBA32(0x2010) |= (1 << 10);
 }
 
-static void i945_late_initialization(void)
+void i945_late_initialization(void)
 {
        i945_setup_egress_port();
 

diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c
index d6623c5e351c428ed3ef502b20cd9f4703e9fdbe..ad157dcb43dfc4d0f20634a343a679f2b876472d 100644 (file)
--- a/src/northbridge/intel/i945/errata.c
+++ b/src/northbridge/intel/i945/errata.c
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
+#include "i945.h"
 #include "raminit.h"
 
 int fixup_i945_errata(void)

diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 0d6f0246738d6630321eebb5f9e7433117d03249..477c4a559d2805b7d8c825aa625247a168b7de50 100644 (file)
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -333,5 +333,22 @@
 
 static inline void barrier(void) { asm("" ::: "memory"); }
 
+int i945_silicon_revision(void);
+void i945_early_initialization(void);
+void i945_late_initialization(void);
+
+/* provided by southbridge code */
+int smbus_read_byte(unsigned device, unsigned address);
+
+/* provided by mainboard code */
+void setup_ich7_gpios(void);
+
+/* debugging functions */
+void print_pci_devices(void);
+void dump_pci_device(unsigned dev);
+void dump_pci_devices(void);
+void dump_spd_registers(void);
+void dump_mem(unsigned start, unsigned end);
+
 #endif
 #endif

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 1595b8b3bc092ceb87f037aa1c6d2074270a7fab..c23fa64dbb84fb67424c614cb72097a1bfb99f48 100644 (file)
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -17,10 +17,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <pc80/mc146818rtc.h>
 #include <spd.h>
+#include <string.h>
+#include <arch/romcc_io.h>
 #include "raminit.h"
 #include "i945.h"
 
@@ -45,6 +48,11 @@
 #define RAM_EMRS_2                     (0x1 << 21)
 #define RAM_EMRS_3                     (0x2 << 21)
 
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+       return smbus_read_byte(device, address);
+}
+
 static __attribute__((noinline)) void do_ram_command(u32 command)
 {
        u32 reg32;

diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index eecfe241fe0cee8296f9bfab77168bb78519c1cb..026d7150479531e2755dc8aa242cda1d416e1dca 100644 (file)
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -71,4 +71,6 @@ void receive_enable_adjust(struct sys_info *sysinfo);
 void sdram_initialize(int boot_path);
 unsigned long get_top_of_ram(void);
 int fixup_i945_errata(void);
+void udelay(u32 us);
+
 #endif                         /* RAMINIT_H */

diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index d5349c937e0abafa99d1f552f9a50e68f935fc43..6b3882bc18532a0b3487d7f21c2c75cdd09cfb62 100644 (file)
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -18,6 +18,7 @@
  */
 
 #include <delay.h>
+#include <stdint.h>
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
 

diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index 01ad0dca16617ef347d91d00522c8cc004e2e27e..2ca5f3dcaaa15fa5c9ac084b91e974df829c3e0b 100644 (file)
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -6,6 +6,7 @@ ramstage-y += keyboard.c
 
 romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c
 romstage-$(CONFIG_CACHE_AS_RAM) += serial.c
+romstage-$(CONFIG_USBDEBUG) += usbdebug_serial.c
 subdirs-y += vga
 
 $(obj)/pc80/mc146818rtc.ramstage.o : $(OPTION_TABLE_H)

diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index a49c1b37605c07b8995156968e9e6e29c3c17758..dfc9c4d3b64d0759e7f4f9ee0bd7c2b786196236 100644 (file)
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -35,3 +35,7 @@ ramstage-y += i82801gx_watchdog.c
 
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += i82801gx_smihandler.c
+
+romstage-y += i82801gx_early_smbus.c
+romstage-$(CONFIG_USBDEBUG) += i82801gx_usb_debug.c
+

diff --git a/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c b/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
index 7d3c80e8a7fcb00df549809064b2af2dc450a05f..658b4831652b8c337fc4871dea0ffb404b0c3bff 100644 (file)
--- a/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
@@ -18,11 +18,17 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
 #include <device/pci_ids.h>
+#include <device/pci_def.h>
 #include "i82801gx.h"
 #include "i82801gx_smbus.h"
 
-static void enable_smbus(void)
+int smbus_read_byte(unsigned device, unsigned address);
+
+void enable_smbus(void)
 {
        device_t dev;
 
@@ -52,7 +58,7 @@ static void enable_smbus(void)
        print_debug("SMBus controller enabled.\n");
 }
 
-static inline int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned device, unsigned address)
 {
        return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }

diff --git a/src/southbridge/intel/i82801gx/i82801gx_smbus.h b/src/southbridge/intel/i82801gx/i82801gx_smbus.h
index c27eadb651a60d7422ebbf5af721d3450b00216a..d1aaf5b517086ab0ad6acebe616c90dcb20b732f 100644 (file)
--- a/src/southbridge/intel/i82801gx/i82801gx_smbus.h
+++ b/src/southbridge/intel/i82801gx/i82801gx_smbus.h
@@ -20,6 +20,8 @@
 
 #include <device/smbus_def.h>
 
+void enable_smbus(void);
+
 static void smbus_delay(void)
 {
        inb(0x80);

diff --git a/util/abuild/abuild b/util/abuild/abuild
index 5a17e5e328e06c4ff2579cc1089bd27d65e04006..9601e83f585c609befea1b33c79f6f2297f67b2d 100755 (executable)
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -203,6 +203,7 @@ function create_config
                        echo "CONFIG_SCANBUILD_ENABLE=y" >> .config
                        echo "CONFIG_SCANBUILD_REPORT_LOCATION=\"$TARGET/scan-build-results-tmp\"" >> .config
                fi
+               echo "CONFIG_USBDEBUG=y" >> .config
        fi
 
        #yes "" | $MAKE oldconfig -j $cpus obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log