src/mainboard/iwill/dk8x/romstage.c

   1 #define RAMINIT_SYSINFO 1
   2
   3 #define SET_NB_CFG_54 1
   4
   5 //used by raminit
   6 #define QRANK_DIMM_SUPPORT 1
   7
   8 //used by incoherent_ht
   9 //#define K8_ALLOCATE_IO_RANGE 1
  10
  11 //used by init_cpus and fidvid
  12 #define SET_FIDVID 0
  13 //if we want to wait for core1 done before DQS training, set it to 0
  14 #define SET_FIDVID_CORE0_ONLY 1
  15
  16 #if CONFIG_K8_REV_F_SUPPORT == 1
  17 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  18 #endif
  19
  20 #include <stdint.h>
  21 #include <string.h>
  22 #include <device/pci_def.h>
  23 #include <device/pci_ids.h>
  24 #include <arch/io.h>
  25 #include <device/pnp_def.h>
  26 #include <arch/romcc_io.h>
  27 #include <cpu/x86/lapic.h>
  28 #include <pc80/mc146818rtc.h>
  29
  30 #include <console/console.h>
  31 #include <cpu/amd/model_fxx_rev.h>
  32 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  33 #include "northbridge/amd/amdk8/raminit.h"
  34 #include "cpu/amd/model_fxx/apic_timer.c"
  35
  36 #include "cpu/x86/lapic/boot_cpu.c"
  37 #include "northbridge/amd/amdk8/reset_test.c"
  38
  39 #include "cpu/x86/bist.h"
  40
  41 #include "lib/delay.c"
  42
  43 #include "northbridge/amd/amdk8/debug.c"
  44 #include "cpu/x86/mtrr/earlymtrr.c"
  45 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  46
  47 #include "northbridge/amd/amdk8/setup_resource_map.c"
  48
  49 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  50
  51 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  52
  53 /*
  54  * GPIO28 of 8111 will control H0_MEMRESET_L
  55  * GPIO29 of 8111 will control H1_MEMRESET_L
  56  */
  57 static void memreset_setup(void)
  58 {
  59         if (is_cpu_pre_c0()) {
  60                 /* Set the memreset low */
  61                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  62                 /* Ensure the BIOS has control of the memory lines */
  63                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  64         } else {
  65                 /* Ensure the CPU has controll of the memory lines */
  66                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  67         }
  68 }
  69
  70 static void memreset(int controllers, const struct mem_controller *ctrl)
  71 {
  72         if (is_cpu_pre_c0()) {
  73                 udelay(800);
  74                 /* Set memreset_high */
  75                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  76                 udelay(90);
  77         }
  78 }
  79
  80 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  81 {
  82 }
  83
  84 static inline int spd_read_byte(unsigned device, unsigned address)
  85 {
  86         return smbus_read_byte(device, address);
  87 }
  88
  89 #include "northbridge/amd/amdk8/amdk8.h"
  90 #include "northbridge/amd/amdk8/incoherent_ht.c"
  91 #include "northbridge/amd/amdk8/coherent_ht.c"
  92 #include "northbridge/amd/amdk8/raminit.c"
  93 #include "lib/generic_sdram.c"
  94
  95  /* tyan does not want the default */
  96 #include "northbridge/amd/amdk8/resourcemap.c"
  97
  98 #include "cpu/amd/dualcore/dualcore.c"
  99
 100 #define DIMM0 0x50
 101 #define DIMM1 0x51
 102 #define DIMM2 0x52
 103 #define DIMM3 0x53
 104 #define DIMM4 0x54
 105 #define DIMM5 0x55
 106 #define DIMM6 0x56
 107 #define DIMM7 0x57
 108
 109 #include "cpu/amd/car/post_cache_as_ram.c"
 110
 111 #include "cpu/amd/model_fxx/init_cpus.c"
 112
 113 #include "cpu/amd/model_fxx/fidvid.c"
 114
 115 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 116 #include "northbridge/amd/amdk8/early_ht.c"
 117
 118 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 119 {
 120         static const uint16_t spd_addr[] = {
 121                         // first node
 122                         DIMM0, DIMM2, 0, 0,
 123                         DIMM1, DIMM3, 0, 0,
 124
 125                         // second node
 126                         DIMM4, DIMM6, 0, 0,
 127                         DIMM5, DIMM7, 0, 0,
 128         };
 129
 130         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 131                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 132
 133         int needs_reset;
 134         unsigned bsp_apicid = 0;
 135
 136         if (!cpu_init_detectedx && boot_cpu()) {
 137                 /* Nothing special needs to be done to find bus 0 */
 138                 /* Allow the HT devices to be found */
 139
 140                 enumerate_ht_chain();
 141
 142                 /* Setup the rom access for 4M */
 143                 amd8111_enable_rom();
 144         }
 145
 146         if (bist == 0) {
 147                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 148         }
 149
 150         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 151         uart_init();
 152         console_init();
 153
 154         /* Halt if there was a built in self test failure */
 155         report_bist_failure(bist);
 156
 157         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 158
 159         setup_default_resource_map();
 160
 161         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 162
 163 #if CONFIG_MEM_TRAIN_SEQ == 1
 164         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 165 #endif
 166         setup_coherent_ht_domain(); // routing table and start other core0
 167
 168         wait_all_core0_started();
 169 #if CONFIG_LOGICAL_CPUS==1
 170         // It is said that we should start core1 after all core0 launched
 171         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 172          * So here need to make sure last core0 is started, esp for two way system,
 173          * (there may be apic id conflicts in that case)
 174          */
 175         start_other_cores();
 176         wait_all_other_cores_started(bsp_apicid);
 177 #endif
 178
 179         /* it will set up chains and store link pair for optimization later */
 180         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 181
 182 #if SET_FIDVID == 1
 183
 184         {
 185                 msr_t msr;
 186                 msr=rdmsr(0xc0010042);
 187                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 188
 189         }
 190
 191         enable_fid_change();
 192
 193         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 194
 195         init_fidvid_bsp(bsp_apicid);
 196
 197         // show final fid and vid
 198         {
 199                 msr_t msr;
 200                 msr=rdmsr(0xc0010042);
 201                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 202
 203         }
 204 #endif
 205
 206         needs_reset = optimize_link_coherent_ht();
 207         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 208
 209         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 210         if (needs_reset) {
 211                 print_info("ht reset -\n");
 212                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 213         }
 214
 215         allow_all_aps_stop(bsp_apicid);
 216
 217         //It's the time to set ctrl in sysinfo now;
 218         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 219
 220         enable_smbus();
 221
 222 #if 0
 223         dump_smbus_registers();
 224 #endif
 225
 226         memreset_setup();
 227
 228         //do we need apci timer, tsc...., only debug need it for better output
 229         /* all ap stopped? */
 230         init_timer(); // Need to use TMICT to synconize FID/VID
 231         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 232
 233 #if 0
 234         dump_pci_devices();
 235 #endif
 236
 237         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 238
 239 }
 240