src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <cpu/x86/mtrr.h>
  21 #include <cpu/x86/cache.h>
  22 #include <pc80/mc146818rtc.h>
  23 #include <spd.h>
  24 #include "raminit.h"
  25 #include "i945.h"
  26
  27 /* Debugging macros. */
  28 #if CONFIG_DEBUG_RAM_SETUP
  29 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  30 #else
  31 #define PRINTK_DEBUG(x...)
  32 #endif
  33
  34 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  35
  36 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  37 #define RAM_COMMAND_NOP                 (0x1 << 16)
  38 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  39 #define RAM_COMMAND_MRS                 (0x3 << 16)
  40 #define RAM_COMMAND_EMRS                (0x4 << 16)
  41 #define RAM_COMMAND_CBR                 (0x6 << 16)
  42 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  43
  44 #define RAM_EMRS_1                      (0x0 << 21)
  45 #define RAM_EMRS_2                      (0x1 << 21)
  46 #define RAM_EMRS_3                      (0x2 << 21)
  47
  48 static __attribute__((noinline)) void do_ram_command(u32 command)
  49 {
  50         u32 reg32;
  51
  52         reg32 = MCHBAR32(DCC);
  53         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  54         reg32 |= command;
  55
  56         /* Also set Init Complete */
  57         if (command == RAM_COMMAND_NORMAL)
  58                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  59
  60         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  61
  62         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  63
  64         PRINTK_DEBUG("...done\n");
  65
  66         udelay(1);
  67 }
  68
  69 static void ram_read32(u32 offset)
  70 {
  71         PRINTK_DEBUG("   ram read: %08x\n", offset);
  72
  73         read32(offset);
  74 }
  75
  76 #if CONFIG_DEBUG_RAM_SETUP
  77 static void sdram_dump_mchbar_registers(void)
  78 {
  79         int i;
  80         printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
  81
  82         for (i=0; i<0xfff; i+=4) {
  83                 if (MCHBAR32(i) == 0)
  84                         continue;
  85                 printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
  86         }
  87 }
  88 #endif
  89
  90 static int memclk(void)
  91 {
  92         int offset = 0;
  93 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
  94         offset++;
  95 #endif
  96         switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
  97         case 1: return 400;
  98         case 2: return 533;
  99         case 3: return 667;
 100         default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
 101         }
 102         return -1;
 103 }
 104
 105 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
 106 static u16 fsbclk(void)
 107 {
 108         switch (MCHBAR32(CLKCFG) & 7) {
 109         case 0: return 400;
 110         case 1: return 533;
 111         case 3: return 667;
 112         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 113         }
 114         return 0xffff;
 115 }
 116 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
 117 static u16 fsbclk(void)
 118 {
 119         switch (MCHBAR32(CLKCFG) & 7) {
 120         case 0: return 1066;
 121         case 1: return 533;
 122         case 2: return 800;
 123         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 124         }
 125         return 0xffff;
 126 }
 127 #endif
 128
 129 static int sdram_capabilities_max_supported_memory_frequency(void)
 130 {
 131         u32 reg32;
 132
 133 #if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
 134         return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
 135 #endif
 136
 137         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
 138         reg32 &= (7 << 0);
 139
 140         switch (reg32) {
 141         case 4: return 400;
 142         case 3: return 533;
 143         case 2: return 667;
 144         }
 145         /* Newer revisions of this chipset rather support faster memory clocks,
 146          * so if it's a reserved value, return the fastest memory clock that we
 147          * know of and can handle
 148          */
 149         return 667;
 150 }
 151
 152 /**
 153  * @brief determine whether chipset is capable of dual channel interleaved mode
 154  *
 155  * @return 1 if interleaving is supported, 0 otherwise
 156  */
 157 static int sdram_capabilities_interleave(void)
 158 {
 159         u32 reg32;
 160
 161         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 162         reg32 >>= 25;
 163         reg32 &= 1;
 164
 165         return (!reg32);
 166 }
 167
 168 /**
 169  * @brief determine whether chipset is capable of two memory channels
 170  *
 171  * @return 1 if dual channel operation is supported, 0 otherwise
 172  */
 173 static int sdram_capabilities_dual_channel(void)
 174 {
 175         u32 reg32;
 176
 177         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 178         reg32 >>= 24;
 179         reg32 &= 1;
 180
 181         return (!reg32);
 182 }
 183
 184 static int sdram_capabilities_enhanced_addressing_xor(void)
 185 {
 186         u8 reg8;
 187
 188         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 189         reg8 &= (1 << 7);
 190
 191         return (!reg8);
 192 }
 193
 194 static int sdram_capabilities_two_dimms_per_channel(void)
 195 {
 196         u8 reg8;
 197
 198         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 199         reg8 &= (1 << 0);
 200
 201         return (reg8 != 0);
 202 }
 203
 204 // TODO check if we ever need this function
 205 #if 0
 206 static int sdram_capabilities_MEM4G_disable(void)
 207 {
 208         u8 reg8;
 209
 210         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 211         reg8 &= (1 << 0);
 212
 213         return (reg8 != 0);
 214 }
 215 #endif
 216
 217 #define GFX_FREQUENCY_CAP_166MHZ        0x04
 218 #define GFX_FREQUENCY_CAP_200MHZ        0x03
 219 #define GFX_FREQUENCY_CAP_250MHZ        0x02
 220 #define GFX_FREQUENCY_CAP_ALL           0x00
 221
 222 static int sdram_capabilities_core_frequencies(void)
 223 {
 224         u8 reg8;
 225
 226         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 227         reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
 228         reg8 >>= 1;
 229
 230         return (reg8);
 231 }
 232
 233 static void sdram_detect_errors(struct sys_info *sysinfo)
 234 {
 235         u8 reg8;
 236         u8 do_reset = 0;
 237
 238         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 239
 240         if (reg8 & ((1<<7)|(1<<2))) {
 241                 if (reg8 & (1<<2)) {
 242                         printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 243                         /* Write back clears bit 2 */
 244                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 245                         do_reset = 1;
 246
 247                 }
 248
 249                 if (reg8 & (1<<7)) {
 250                         printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 251                         reg8 &= ~(1<<7);
 252                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 253                         do_reset = 1;
 254                 }
 255
 256                 /* Set SLP_S3# Assertion Stretch Enable */
 257                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 258                 reg8 |= (1 << 3);
 259                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 260
 261                 if (do_reset) {
 262                         printk(BIOS_DEBUG, "Reset required.\n");
 263                         outb(0x00, 0xcf9);
 264                         outb(0x0e, 0xcf9);
 265                         for (;;) asm("hlt"); /* Wait for reset! */
 266                 }
 267         }
 268
 269         /* Set DRAM initialization bit in ICH7 */
 270         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 271         reg8 |= (1<<7);
 272         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 273
 274         /* clear self refresh if not wake-up from suspend */
 275         if (sysinfo->boot_path != 2) {
 276                 MCHBAR8(0xf14) |= 3;
 277         } else {
 278                 /* Validate self refresh config */
 279                 if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
 280                      (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
 281                     !(MCHBAR8(0xf14) & (1<<0))) {
 282                         do_reset = 1;
 283                 }
 284                 if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
 285                      (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
 286                     !(MCHBAR8(0xf14) & (1<<1))) {
 287                         do_reset = 1;
 288                 }
 289         }
 290
 291         if (do_reset) {
 292                 printk(BIOS_DEBUG, "Reset required.\n");
 293                 outb(0x00, 0xcf9);
 294                 outb(0x0e, 0xcf9);
 295                 for (;;) asm("hlt"); /* Wait for reset! */
 296         }
 297 }
 298
 299 /**
 300  * @brief Get generic DIMM parameters.
 301  * @param sysinfo Central memory controller information structure
 302  *
 303  * This function gathers several pieces of information for each system DIMM:
 304  *  o DIMM width (x8 / x16)
 305  *  o DIMM sides (single sided / dual sided)
 306  *
 307  *  Also, some non-supported scenarios are detected.
 308  */
 309
 310 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 311 {
 312         u32 dimm_mask = 0;
 313         int i;
 314
 315         /**
 316          * i945 supports two DIMMs, in two configurations:
 317          *
 318          * - single channel with two dimms
 319          * - dual channel with one dimm per channel
 320          *
 321          * In practice dual channel mainboards have their spd at 0x50, 0x52
 322          * whereas single channel configurations have their spd at 0x50/x51
 323          *
 324          * The capability register knows a lot about the channel configuration
 325          * but for now we stick with the information we gather from the SPD
 326          * ROMs
 327          */
 328
 329         if (sdram_capabilities_dual_channel()) {
 330                 sysinfo->dual_channel = 1;
 331                 printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 332         } else {
 333                 sysinfo->dual_channel = 0;
 334                 printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 335         }
 336
 337         /**
 338          * Since we only support two DIMMs in total, there is a limited number
 339          * of combinations. This function returns the type of DIMMs.
 340          * return value:
 341          *   [0:7]  lower DIMM population
 342          *   [8-15] higher DIMM population
 343          *   [16]   dual channel?
 344          *
 345          * There are 5 different possible populations for a DIMM socket:
 346          * 1. x16 double sided (X16DS)
 347          * 2. x8 double sided  (X8DS)
 348          * 3. x16 single sided (X16SS)
 349          * 4. x8 double stacked (X8DDS)
 350          * 5. not populated (NC)
 351          *
 352          * For the return value we start counting at zero.
 353          *
 354          */
 355
 356         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 357                 u8 reg8, device = DIMM_SPD_BASE + i;
 358
 359                 /* Initialize the socket information with a sane value */
 360                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 361
 362                 /* Dual Channel not supported, but Channel 1? Bail out */
 363                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 364                         continue;
 365
 366                 /* Two DIMMs per channel not supported, but odd DIMM number? */
 367                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 368                         continue;
 369
 370                 printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 371
 372                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 373                         printk(BIOS_DEBUG, "N/A\n");
 374                         continue;
 375                 }
 376
 377                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 378                 if (reg8 == ERROR_SCHEME_ECC)
 379                         die("Error: ECC memory not supported by this chipset\n");
 380
 381                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 382                 if (reg8 & MODULE_BUFFERED)
 383                         die("Error: Buffered memory not supported by this chipset\n");
 384                 if (reg8 & MODULE_REGISTERED)
 385                         die("Error: Registered memory not supported by this chipset\n");
 386
 387                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 388                 case 0x08:
 389                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 390                         case 1:
 391                                 printk(BIOS_DEBUG, "x8DDS\n");
 392                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 393                                 break;
 394                         case 0:
 395                                 printk(BIOS_DEBUG, "x8DS\n");
 396                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 397                                 break;
 398                         default:
 399                                 printk(BIOS_DEBUG, "Unsupported.\n");
 400                         }
 401                         break;
 402                 case 0x10:
 403                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 404                         case 1:
 405                                 printk(BIOS_DEBUG, "x16DS\n");
 406                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 407                                 break;
 408                         case 0:
 409                                 printk(BIOS_DEBUG, "x16SS\n");
 410                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 411                                 break;
 412                         default:
 413                                 printk(BIOS_DEBUG, "Unsupported.\n");
 414                         }
 415                         break;
 416                 default:
 417                         die("Unsupported DDR-II memory width.\n");
 418                 }
 419
 420                 dimm_mask |= (1 << i);
 421         }
 422
 423         if (!dimm_mask) {
 424                 die("No memory installed.\n");
 425         }
 426
 427         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 428                 printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 429         }
 430 }
 431
 432 /**
 433  * @brief determine if any DIMMs are stacked
 434  *
 435  * @param sysinfo central sysinfo data structure.
 436  */
 437 static void sdram_verify_package_type(struct sys_info * sysinfo)
 438 {
 439         int i;
 440
 441         /* Assume no stacked DIMMs are available until we find one */
 442         sysinfo->package = 0;
 443         for (i=0; i<2*DIMM_SOCKETS; i++) {
 444                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 445                         continue;
 446
 447                 /* Is the current DIMM a stacked DIMM? */
 448                 if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 449                         sysinfo->package = 1;
 450         }
 451 }
 452
 453 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 454 {
 455         int i;
 456         u8 cas_mask;
 457
 458         /* Setup CAS mask with all supported CAS Latencies */
 459         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 460                    SPD_CAS_LATENCY_DDR2_4 |
 461                    SPD_CAS_LATENCY_DDR2_5;
 462
 463         for (i=0; i<2*DIMM_SOCKETS; i++) {
 464                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 465                         cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 466         }
 467
 468         if(!cas_mask) {
 469                 die("No DDR-II modules with accepted CAS latencies found.\n");
 470         }
 471
 472         return cas_mask;
 473 }
 474
 475 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 476 {
 477         int i, j, idx;
 478         int lowest_common_cas = 0;
 479         int max_ram_speed = 0;
 480
 481         const u8 ddr2_speeds_table[] = {
 482                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 483                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 484                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 485         };
 486
 487         const u8 spd_lookup_table[] = {
 488                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 489                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 490                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 491         };
 492
 493         switch (sdram_capabilities_max_supported_memory_frequency()) {
 494         case 400: max_ram_speed = 0; break;
 495         case 533: max_ram_speed = 1; break;
 496         case 667: max_ram_speed = 2; break;
 497         }
 498
 499         if (fsbclk() == 533)
 500                 max_ram_speed = 1;
 501
 502         sysinfo->memory_frequency = 0;
 503         sysinfo->cas = 0;
 504
 505         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 506                 lowest_common_cas = 3;
 507         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 508                 lowest_common_cas = 4;
 509         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 510                 lowest_common_cas = 5;
 511         }
 512         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 513
 514         for (j = max_ram_speed; j>=0; j--) {
 515                 int freq_cas_mask = cas_mask;
 516
 517                 PRINTK_DEBUG("Probing Speed %d\n", j);
 518                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 519                         int current_cas_mask;
 520
 521                         PRINTK_DEBUG("  DIMM: %d\n", i);
 522                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 523                                 continue;
 524                         }
 525
 526                         current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 527
 528                         while (current_cas_mask) {
 529                                 int highest_supported_cas = 0, current_cas = 0;
 530                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 531                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 532                                         highest_supported_cas = 5;
 533                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 534                                         highest_supported_cas = 4;
 535                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 536                                         highest_supported_cas = 3;
 537                                 }
 538                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 539                                         current_cas = 3;
 540                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 541                                         current_cas = 4;
 542                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 543                                         current_cas = 5;
 544                                 }
 545
 546                                 idx = highest_supported_cas - current_cas;
 547                                 PRINTK_DEBUG("idx=%d, ", idx);
 548                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
 549                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
 550
 551                                 if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 552                                                 spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 553                                         PRINTK_DEBUG(":    OK\n");
 554                                         break;
 555                                 }
 556
 557                                 PRINTK_DEBUG(":    Not fast enough!\n");
 558
 559                                 current_cas_mask &= ~(1 << (current_cas));
 560                         }
 561
 562                         freq_cas_mask &= current_cas_mask;
 563                         if (!current_cas_mask) {
 564                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 565                                 break;
 566                         }
 567                 }
 568                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 569                 if (freq_cas_mask) {
 570                         switch (j) {
 571                         case 0: sysinfo->memory_frequency = 400; break;
 572                         case 1: sysinfo->memory_frequency = 533; break;
 573                         case 2: sysinfo->memory_frequency = 667; break;
 574                         }
 575                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 576                                 sysinfo->cas = 3;
 577                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 578                                 sysinfo->cas = 4;
 579                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 580                                 sysinfo->cas = 5;
 581                         }
 582                         break;
 583                 }
 584         }
 585
 586         if (sysinfo->memory_frequency && sysinfo->cas) {
 587                 printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 588                                 sysinfo->memory_frequency, sysinfo->cas);
 589         } else {
 590                 die("Could not find common memory frequency and CAS\n");
 591         }
 592 }
 593
 594 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 595 {
 596         int i;
 597         int tRAS_time;
 598         int tRAS_cycles;
 599         int freq_multiplier = 0;
 600
 601         switch (sysinfo->memory_frequency) {
 602         case 400: freq_multiplier = 0x14; break; /* 5ns */
 603         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 604         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 605         }
 606
 607         tRAS_cycles = 4; /* 4 clocks minimum */
 608         tRAS_time = tRAS_cycles * freq_multiplier;
 609
 610         for (i=0; i<2*DIMM_SOCKETS; i++) {
 611                 u8 reg8;
 612
 613                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 614                         continue;
 615
 616                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 617                 if (!reg8) {
 618                         die("Invalid tRAS value.\n");
 619                 }
 620
 621                 while ((tRAS_time >> 2) < reg8) {
 622                         tRAS_time += freq_multiplier;
 623                         tRAS_cycles++;
 624                 }
 625         }
 626         if(tRAS_cycles > 0x18) {
 627                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 628         }
 629
 630         printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 631         sysinfo->tras = tRAS_cycles;
 632 }
 633
 634 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 635 {
 636         int i;
 637         int tRP_time;
 638         int tRP_cycles;
 639         int freq_multiplier = 0;
 640
 641         switch (sysinfo->memory_frequency) {
 642         case 400: freq_multiplier = 0x14; break; /* 5ns */
 643         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 644         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 645         }
 646
 647         tRP_cycles = 2; /* 2 clocks minimum */
 648         tRP_time = tRP_cycles * freq_multiplier;
 649
 650         for (i=0; i<2*DIMM_SOCKETS; i++) {
 651                 u8 reg8;
 652
 653                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 654                         continue;
 655
 656                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
 657                 if (!reg8) {
 658                         die("Invalid tRP value.\n");
 659                 }
 660
 661                 while (tRP_time < reg8) {
 662                         tRP_time += freq_multiplier;
 663                         tRP_cycles++;
 664                 }
 665         }
 666
 667         if(tRP_cycles > 6) {
 668                 die("DDR-II Module does not support this frequency (tRP error)\n");
 669         }
 670
 671         printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 672         sysinfo->trp = tRP_cycles;
 673 }
 674
 675 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 676 {
 677         int i;
 678         int tRCD_time;
 679         int tRCD_cycles;
 680         int freq_multiplier = 0;
 681
 682         switch (sysinfo->memory_frequency) {
 683         case 400: freq_multiplier = 0x14; break; /* 5ns */
 684         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 685         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 686         }
 687
 688         tRCD_cycles = 2; /* 2 clocks minimum */
 689         tRCD_time = tRCD_cycles * freq_multiplier;
 690
 691         for (i=0; i<2*DIMM_SOCKETS; i++) {
 692                 u8 reg8;
 693
 694                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 695                         continue;
 696
 697                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
 698                 if (!reg8) {
 699                         die("Invalid tRCD value.\n");
 700                 }
 701
 702                 while (tRCD_time < reg8) {
 703                         tRCD_time += freq_multiplier;
 704                         tRCD_cycles++;
 705                 }
 706         }
 707         if(tRCD_cycles > 6) {
 708                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 709         }
 710
 711         printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 712         sysinfo->trcd = tRCD_cycles;
 713 }
 714
 715 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 716 {
 717         int i;
 718         int tWR_time;
 719         int tWR_cycles;
 720         int freq_multiplier = 0;
 721
 722         switch (sysinfo->memory_frequency) {
 723         case 400: freq_multiplier = 0x14; break; /* 5ns */
 724         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 725         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 726         }
 727
 728         tWR_cycles = 2; /* 2 clocks minimum */
 729         tWR_time = tWR_cycles * freq_multiplier;
 730
 731         for (i=0; i<2*DIMM_SOCKETS; i++) {
 732                 u8 reg8;
 733
 734                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 735                         continue;
 736
 737                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
 738                 if (!reg8) {
 739                         die("Invalid tWR value.\n");
 740                 }
 741
 742                 while (tWR_time < reg8) {
 743                         tWR_time += freq_multiplier;
 744                         tWR_cycles++;
 745                 }
 746         }
 747         if(tWR_cycles > 5) {
 748                 die("DDR-II Module does not support this frequency (tWR error)\n");
 749         }
 750
 751         printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 752         sysinfo->twr = tWR_cycles;
 753 }
 754
 755 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 756 {
 757         int i, index = 0;
 758
 759         const u8 tRFC_cycles[] = {
 760              /* 75 105 127.5 */
 761                 15, 21, 26,     /* DDR2-400 */
 762                 20, 28, 34,     /* DDR2-533 */
 763                 25, 35, 43      /* DDR2-667 */
 764         };
 765
 766         for (i=0; i<2*DIMM_SOCKETS; i++) {
 767                 u8 reg8;
 768
 769                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 770                         continue;
 771
 772                 reg8 = sysinfo->banksize[i*2];
 773                 switch (reg8) {
 774                 case 0x04: reg8 = 0; break;
 775                 case 0x08: reg8 = 1; break;
 776                 case 0x10: reg8 = 2; break;
 777                 case 0x20: reg8 = 3; break;
 778                 }
 779
 780                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 781                         reg8++;
 782
 783                 if (reg8 > 3) {
 784                         /* Can this happen? Go back to 127.5ns just to be sure
 785                          * we don't run out of the array. This may be wrong
 786                          */
 787                         printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 788                         reg8 = 3;
 789                 }
 790
 791                 if (reg8 > index)
 792                         index = reg8;
 793
 794         }
 795         index--;
 796         switch (sysinfo->memory_frequency) {
 797         case 667: index += 3; /* Fallthrough */
 798         case 533: index += 3; /* Fallthrough */
 799         case 400: break;
 800         }
 801
 802         sysinfo->trfc = tRFC_cycles[index];
 803         printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 804 }
 805
 806 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 807 {
 808         int i;
 809
 810         sysinfo->refresh = 0;
 811
 812         for (i=0; i<2*DIMM_SOCKETS; i++) {
 813                 int refresh;
 814
 815                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 816                         continue;
 817
 818                 refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
 819
 820                 /* 15.6us */
 821                 if (!refresh)
 822                         continue;
 823
 824                 /* Refresh is slower than 15.6us, use 15.6us */
 825                 if (refresh > 2)
 826                         continue;
 827
 828                 if (refresh == 2) {
 829                         sysinfo->refresh = 1;
 830                         break;
 831                 }
 832
 833                 die("DDR-II module has unsupported refresh value\n");
 834         }
 835         printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 836 }
 837
 838 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 839 {
 840         int i;
 841
 842         for (i=0; i<2*DIMM_SOCKETS; i++) {
 843                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 844                         continue;
 845
 846                 if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 847                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 848         }
 849 }
 850
 851 static void sdram_program_dram_width(struct sys_info * sysinfo)
 852 {
 853         u16 c0dramw=0, c1dramw=0;
 854         int idx;
 855
 856         if (sysinfo->dual_channel)
 857                 idx = 2;
 858         else
 859                 idx = 1;
 860
 861         switch (sysinfo->dimm[0]) {
 862         case 0: c0dramw = 0x0000; break; /* x16DS */
 863         case 1: c0dramw = 0x0001; break; /* x8DS */
 864         case 2: c0dramw = 0x0000; break; /* x16SS */
 865         case 3: c0dramw = 0x0005; break; /* x8DDS */
 866         case 4: c0dramw = 0x0000; break; /* NC */
 867         }
 868
 869         switch (sysinfo->dimm[idx]) {
 870         case 0: c1dramw = 0x0000; break; /* x16DS */
 871         case 1: c1dramw = 0x0010; break; /* x8DS */
 872         case 2: c1dramw = 0x0000; break; /* x16SS */
 873         case 3: c1dramw = 0x0050; break; /* x8DDS */
 874         case 4: c1dramw = 0x0000; break; /* NC */
 875         }
 876
 877         if ( !sdram_capabilities_dual_channel() ) {
 878                 /* Single Channel */
 879                 c0dramw |= c1dramw;
 880                 c1dramw = 0;
 881         }
 882
 883         MCHBAR16(C0DRAMW) = c0dramw;
 884         MCHBAR16(C1DRAMW) = c1dramw;
 885 }
 886
 887 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 888 {
 889         int i;
 890
 891         for (i=0; i<16; i++)
 892                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 893 }
 894
 895 static const u32 dq2030[] = {
 896         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 897         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 898         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 899         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 900 };
 901
 902 static const u32 dq2330[] = {
 903         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 904         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 905         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 906         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 907 };
 908
 909 static const u32 cmd2710[] = {
 910         0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 911         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 912         0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 913         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 914 };
 915
 916 static const u32 cmd3210[] = {
 917         0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 918         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 919         0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 920         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 921 };
 922
 923 static const u32 clk2030[] = {
 924         0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 925         0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 926         0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 927         0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 928 };
 929
 930 static const u32 ctl3215[] = {
 931         0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 932         0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 933         0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 934         0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 935 };
 936
 937 static const u32 ctl3220[] = {
 938         0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 939         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 940         0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 941         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 942 };
 943
 944 static const u32 nc[] = {
 945         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 946         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 947         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 948         0x00000000, 0x00000000, 0x00000000, 0x00000000
 949 };
 950
 951 enum {
 952         DQ2030,
 953         DQ2330,
 954         CMD2710,
 955         CMD3210,
 956         CLK2030,
 957         CTL3215,
 958         CTL3220,
 959         NC,
 960 };
 961
 962 static const u8 dual_channel_slew_group_lookup[] = {
 963         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 964         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 965         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 966         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 967         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 968
 969         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 970         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 971         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 972         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 973         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 974
 975         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 976         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 977         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 978         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 979         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 980
 981         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 982         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 983         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 984         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 985         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 986
 987         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 988         NC,     NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 989         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 990         NC,     NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD2710
 991 };
 992
 993 static const u8 single_channel_slew_group_lookup[] = {
 994         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 995         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 996         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
 997         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 998         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 999
1000         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1001         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1002         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1003         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1004         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1005
1006         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1007         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1008         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1009         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1010         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
1011
1012         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1013         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1014         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1015         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1016         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1017
1018         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1019         DQ2330, NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
1020         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1021         DQ2330, NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD3210
1022 };
1023
1024 static const u32 *slew_group_lookup(int dual_channel, int index)
1025 {
1026         const u8 *slew_group;
1027         /* Dual Channel needs different tables. */
1028         if (dual_channel)
1029                 slew_group   = dual_channel_slew_group_lookup;
1030         else
1031                 slew_group   = single_channel_slew_group_lookup;
1032
1033         switch (slew_group[index]) {
1034         case DQ2030:    return dq2030;
1035         case DQ2330:    return dq2330;
1036         case CMD2710:   return cmd2710;
1037         case CMD3210:   return cmd3210;
1038         case CLK2030:   return clk2030;
1039         case CTL3215:   return ctl3215;
1040         case CTL3220:   return ctl3220;
1041         case NC:        return nc;
1042         }
1043
1044         return nc;
1045 }
1046
1047 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
1048 /* Strength multiplier tables */
1049 static const u8 dual_channel_strength_multiplier[] = {
1050         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1051         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1052         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1053         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1054         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1055         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1056         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1057         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1058         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1059         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1060         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1061         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1062         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1063         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1064         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1065         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1066         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1067         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1068         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1069         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1070         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1071         0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1072         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1073         0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
1074 };
1075
1076 static const u8 single_channel_strength_multiplier[] = {
1077         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1078         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1079         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1080         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1081         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1082         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1083         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1084         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1085         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1086         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1087         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1088         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1089         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1090         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1091         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1092         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1093         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1094         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1095         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1096         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1097         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1098         0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1099         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1100         0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1101 };
1102 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
1103 static const u8 dual_channel_strength_multiplier[] = {
1104         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1105         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1106         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1107         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1108         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1109         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1110         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1111         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1112         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1113         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1114         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1115         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1116         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1117         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1118         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1119         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1120         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1121         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1122         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1123         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1124         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1125         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1126         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1127         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33
1128 };
1129
1130 static const u8 single_channel_strength_multiplier[] = {
1131         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1132         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1133         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1134         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1135         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1136         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1137         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1138         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1139         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1140         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1141         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1142         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1143         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1144         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1145         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1146         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1147         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1148         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1149         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1150         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1151         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1152         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1153         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1154         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00
1155 };
1156 #endif
1157
1158 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
1159 {
1160         const u8 * strength_multiplier;
1161         int idx, dual_channel;
1162
1163         /* Set Strength Multipliers */
1164
1165         /* Dual Channel needs different tables. */
1166         if (sdram_capabilities_dual_channel()) {
1167                 printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
1168                 strength_multiplier = dual_channel_strength_multiplier;
1169                 dual_channel = 1;
1170                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
1171         } else {
1172                 printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
1173                 strength_multiplier = single_channel_strength_multiplier;
1174                 dual_channel = 0;
1175                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1176         }
1177
1178         printk(BIOS_DEBUG, "Table Index: %d\n", idx);
1179
1180         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1181         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1182         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1183         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1184         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1185         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1186         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1187         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1188
1189         /* Channel 0 */
1190         sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
1191         sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
1192         if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1193
1194                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1195         } else {
1196                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
1197         }
1198         sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
1199         sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
1200         sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
1201
1202         /* Channel 1 */
1203         if (sysinfo->dual_channel) {
1204                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6));
1205                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7));
1206         } else {
1207                 sdram_write_slew_rates(G7SRPUT, nc);
1208                 sdram_write_slew_rates(G8SRPUT, nc);
1209         }
1210 }
1211
1212 static void sdram_enable_rcomp(void)
1213 {
1214         u32 reg32;
1215         /* Enable Global Periodic RCOMP */
1216         udelay(300);
1217         reg32 = MCHBAR32(GBRCOMPCTL);
1218         reg32 &= ~(1 << 23);
1219         MCHBAR32(GBRCOMPCTL) = reg32;
1220 }
1221
1222 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1223 {
1224         u32 chan0dll = 0, chan1dll = 0;
1225         int i;
1226
1227         printk(BIOS_DEBUG, "Programming DLL Timings... \n");
1228
1229         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1230         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1231
1232         /* We drive both channels with the same speed */
1233         switch (sysinfo->memory_frequency) {
1234         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1235         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1236         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1237         }
1238
1239         for (i=0; i < 4; i++) {
1240                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1241                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1242                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1243                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1244         }
1245 }
1246
1247 static void sdram_force_rcomp(void)
1248 {
1249         u32 reg32;
1250         u8 reg8;
1251
1252         reg32 = MCHBAR32(ODTC);
1253         reg32 |= (1 << 28);
1254         MCHBAR32(ODTC) = reg32;
1255
1256         reg32 = MCHBAR32(SMSRCTL);
1257         reg32 |= (1 << 0);
1258         MCHBAR32(SMSRCTL) = reg32;
1259
1260         /* Start initial RCOMP */
1261         reg32 = MCHBAR32(GBRCOMPCTL);
1262         reg32 |= (1 << 8);
1263         MCHBAR32(GBRCOMPCTL) = reg32;
1264
1265         reg8 = i945_silicon_revision();
1266         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1267
1268                 reg32 = MCHBAR32(GBRCOMPCTL);
1269                 reg32 |= (3 << 5);
1270                 MCHBAR32(GBRCOMPCTL) = reg32;
1271         }
1272 }
1273
1274 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1275 {
1276         u8 reg8;
1277         u32 reg32;
1278
1279         printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
1280         /* Enable Data Half Clock Pushout */
1281         reg8 = MCHBAR8(C0HCTC);
1282         reg8 &= ~0x1f;
1283         reg8 |= ( 1 << 0);
1284         MCHBAR8(C0HCTC) = reg8;
1285
1286         reg8 = MCHBAR8(C1HCTC);
1287         reg8 &= ~0x1f;
1288         reg8 |= ( 1 << 0);
1289         MCHBAR8(C1HCTC) = reg8;
1290
1291         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1292         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1293
1294         MCHBAR8(C0WDLLCMC) = 0;
1295         MCHBAR8(C1WDLLCMC) = 0;
1296
1297         /* Program RCOMP Settings */
1298         sdram_program_dram_width(sysinfo);
1299
1300         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1301
1302         /* Indicate that RCOMP programming is done */
1303         reg32 = MCHBAR32(GBRCOMPCTL);
1304         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1305         reg32 |= (3 << 27) | (3 << 0);
1306         MCHBAR32(GBRCOMPCTL) = reg32;
1307
1308         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1309
1310         /* Program DLL Timings */
1311         sdram_program_dll_timings(sysinfo);
1312
1313         /* Force RCOMP cycle */
1314         sdram_force_rcomp();
1315 }
1316
1317 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1318 {
1319         u32 reg32;
1320
1321         printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
1322
1323         reg32 = MCHBAR32(RCVENMT);
1324         reg32 &= ~(0x3f << 6);
1325         MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1326
1327         reg32 |= (1 << 11) | (1 << 9);
1328         MCHBAR32(RCVENMT) = reg32;
1329
1330         reg32 = MCHBAR32(DRTST);
1331         reg32 |= (1 << 3) | (1 << 2);
1332         MCHBAR32(DRTST) = reg32;
1333
1334         reg32 = MCHBAR32(DRTST);
1335         reg32 |= (1 << 6) | (1 << 4);
1336         MCHBAR32(DRTST) = reg32;
1337
1338         asm volatile ("nop; nop;" ::: "memory");
1339
1340         reg32 = MCHBAR32(DRTST);
1341
1342         /* Is channel 0 populated? */
1343         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1344                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1345                 reg32 |= (1 << 7) | (1 << 5);
1346         else
1347                 reg32 |= (1 << 31);
1348
1349         /* Is channel 1 populated? */
1350         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1351                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1352                 reg32 |= (1 << 9) | (1 << 8);
1353         else
1354                 reg32 |= (1 << 30);
1355
1356         MCHBAR32(DRTST) = reg32;
1357
1358         /* Activate DRAM Channel IO Buffers */
1359         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1360                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1361                 reg32 = MCHBAR32(C0DRC1);
1362                 reg32 |= (1 << 8);
1363                 MCHBAR32(C0DRC1) = reg32;
1364         }
1365         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1366                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1367                 reg32 = MCHBAR32(C1DRC1);
1368                 reg32 |= (1 << 8);
1369                 MCHBAR32(C1DRC1) = reg32;
1370         }
1371 }
1372
1373 struct dimm_size {
1374         unsigned long side1;
1375         unsigned long side2;
1376 };
1377
1378 static struct dimm_size sdram_get_dimm_size(u16 device)
1379 {
1380         /* Calculate the log base 2 size of a DIMM in bits */
1381         struct dimm_size sz;
1382         int value, low, rows, columns;
1383
1384         sz.side1 = 0;
1385         sz.side2 = 0;
1386
1387         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1388         if (rows < 0) goto hw_err;
1389         if ((rows & 0xf) == 0) goto val_err;
1390         sz.side1 += rows & 0xf;
1391
1392         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1393         if (columns < 0) goto hw_err;
1394         if ((columns & 0xf) == 0) goto val_err;
1395         sz.side1 += columns & 0xf;
1396
1397         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1398         if (value < 0) goto hw_err;
1399         if ((value & 0xff) == 0) goto val_err;
1400         sz.side1 += log2(value & 0xff);
1401
1402         /* Get the module data width and convert it to a power of two */
1403         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1404         if (value < 0) goto hw_err;
1405         value &= 0xff;
1406         value <<= 8;
1407
1408         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1409         if (low < 0) goto hw_err;
1410         value = value | (low & 0xff);
1411         if ((value != 72) && (value != 64)) goto val_err;
1412         sz.side1 += log2(value);
1413
1414         /* side 2 */
1415         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1416
1417         if (value < 0) goto hw_err;
1418         value &= 7;
1419         value++;
1420         if (value == 1) goto out;
1421         if (value != 2) goto val_err;
1422
1423         /* Start with the symmetrical case */
1424         sz.side2 = sz.side1;
1425
1426         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1427
1428         /* Don't die here, I have not come across any of these to test what
1429          * actually happens.
1430          */
1431         printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
1432
1433         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1434         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1435
1436         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1437         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1438
1439         goto out;
1440
1441  val_err:
1442         die("Bad SPD value\n");
1443  hw_err:
1444         /* If a hardware error occurs the spd rom probably does not exist.
1445          * In this case report that there is no memory
1446          */
1447         sz.side1 = 0;
1448         sz.side2 = 0;
1449  out:
1450         return sz;
1451 }
1452
1453 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1454 {
1455         int i;
1456
1457         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1458                 struct dimm_size sz;
1459
1460                 sysinfo->banksize[i * 2] = 0;
1461                 sysinfo->banksize[(i * 2) + 1] = 0;
1462
1463                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1464                         continue;
1465
1466                 sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
1467
1468                 sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1469
1470                 if (sz.side1 < 30)
1471                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1472
1473                 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1474
1475                 printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1476
1477                 if (!sz.side2)
1478                         continue;
1479
1480                 /* If there is a second side, it has to have at least 128M, too */
1481                 if (sz.side2 < 30)
1482                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1483
1484                 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1485
1486                 printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1487         }
1488 }
1489
1490 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1491 {
1492         int i;
1493         int cum0, cum1, tolud, tom;
1494
1495         printk(BIOS_DEBUG, "Setting RAM size... \n");
1496
1497         cum0 = 0;
1498         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1499                 cum0 += sysinfo->banksize[i];
1500                 MCHBAR8(C0DRB0+i) = cum0;
1501         }
1502
1503         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1504         cum1 = cum0;
1505
1506         /* Exception: Interleaved starts from the beginning */
1507         if (sysinfo->interleaved)
1508                 cum1 = 0;
1509
1510 #if 0
1511         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1512         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1513                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1514                 cum1 = 0;
1515 #endif
1516
1517         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1518                 cum1 += sysinfo->banksize[i + 4];
1519                 MCHBAR8(C1DRB0+i) = cum1;
1520         }
1521
1522         /* Set TOLUD Top Of Low Usable DRAM */
1523         if (sysinfo->interleaved)
1524                 tolud = (cum0 + cum1) << 1;
1525         else
1526                 tolud = (cum1 ? cum1 : cum0)  << 1;
1527
1528         /* The TOM register has a different format */
1529         tom = tolud >> 3;
1530
1531         /* Limit the value of TOLUD to leave some space for PCI memory. */
1532         if (tolud > 0xd0)
1533                 tolud = 0xd0;   /* 3.25GB : 0.75GB */
1534
1535         pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1536
1537         printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1538         printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1539         printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1540
1541         pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1542
1543         return 0;
1544 }
1545
1546 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1547 {
1548         int i, value;
1549         u16 dra0=0, dra1=0, dra = 0;
1550
1551         printk(BIOS_DEBUG, "Setting row attributes... \n");
1552         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1553                 u16 device;
1554                 u8 columnsrows;
1555
1556                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1557                         continue;
1558                 }
1559
1560                 device = DIMM_SPD_BASE + i;
1561
1562                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1563                 columnsrows = (value & 0x0f);
1564
1565                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1566                 columnsrows |= (value & 0xf) << 4;
1567
1568                 switch (columnsrows) {
1569                 case 0x9d: dra = 2; break;
1570                 case 0xad: dra = 3; break;
1571                 case 0xbd: dra = 4; break;
1572                 case 0xae: dra = 3; break;
1573                 case 0xbe: dra = 4; break;
1574                 default: die("Unsupported Rows/Columns. (DRA)");
1575                 }
1576
1577                 /* Double Sided DIMMs? */
1578                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1579                         dra = (dra << 4) | dra;
1580                 }
1581
1582                 if (i < DIMM_SOCKETS)
1583                         dra0 |= (dra << (i*8));
1584                 else
1585                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1586         }
1587
1588         MCHBAR16(C0DRA0) = dra0;
1589         MCHBAR16(C1DRA0) = dra1;
1590
1591         printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
1592         printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
1593
1594         return 0;
1595 }
1596
1597 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1598 {
1599         u32 off32;
1600         int i;
1601
1602         MCHBAR16(C1BNKARC) &= 0xff00;
1603         MCHBAR16(C0BNKARC) &= 0xff00;
1604
1605         off32 = C0BNKARC;
1606         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1607                 /* Switch to second channel */
1608                 if (i == DIMM_SOCKETS)
1609                         off32 = C1BNKARC;
1610
1611                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1612                         continue;
1613
1614                 if (sysinfo->banks[i] != 8)
1615                         continue;
1616
1617                 printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
1618
1619                 if (i & 1)
1620                         MCHBAR16(off32) |= 0x50;
1621                 else
1622                         MCHBAR16(off32) |= 0x05;
1623         }
1624 }
1625
1626 #define REFRESH_7_8US   1
1627 #define REFRESH_15_6US  0
1628 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1629 {
1630         u32 reg32;
1631
1632         if (sysinfo->refresh == REFRESH_7_8US) {
1633                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1634         } else {
1635                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1636         }
1637
1638         MCHBAR32(C0DRC0) &= ~(7 << 8);
1639         MCHBAR32(C0DRC0) |= reg32;
1640
1641         MCHBAR32(C1DRC0) &= ~(7 << 8);
1642         MCHBAR32(C1DRC0) |= reg32;
1643 }
1644
1645 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1646 {
1647         u32 reg32;
1648         int i;
1649
1650         reg32 = MCHBAR32(C0DRC1);
1651
1652         for (i=0; i < 4; i++) {
1653                 if (sysinfo->banksize[i] == 0) {
1654                         reg32 |= (1 << (16 + i));
1655                 }
1656         }
1657
1658         reg32 |= (1 << 12);
1659
1660         reg32 |= (1 << 11);
1661         MCHBAR32(C0DRC1) = reg32;
1662
1663         /* Do we have to do this if we're in Single Channel Mode?  */
1664         reg32 = MCHBAR32(C1DRC1);
1665
1666         for (i=4; i < 8; i++) {
1667                 if (sysinfo->banksize[i] == 0) {
1668                         reg32 |= (1 << (12 + i));
1669                 }
1670         }
1671
1672         reg32 |= (1 << 12);
1673
1674         reg32 |= (1 << 11);
1675         MCHBAR32(C1DRC1) = reg32;
1676 }
1677
1678 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1679 {
1680         u32 reg32;
1681         int i;
1682
1683         reg32 = MCHBAR32(C0DRC2);
1684
1685         for (i=0; i < 4; i++) {
1686                 if (sysinfo->banksize[i] == 0) {
1687                         reg32 |= (1 << (24 + i));
1688                 }
1689         }
1690         MCHBAR32(C0DRC2) = reg32;
1691
1692         reg32 = MCHBAR32(C1DRC2);
1693
1694         for (i=4; i < 8; i++) {
1695                 if (sysinfo->banksize[i] == 0) {
1696                         reg32 |= (1 << (20 + i));
1697                 }
1698         }
1699         MCHBAR32(C1DRC2) = reg32;
1700 }
1701
1702 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1703 {
1704         u32 reg32, off32;
1705         u32 tWTR;
1706         u32 temp_drt;
1707         int i, page_size;
1708
1709         static const u8 const drt0_table[] = {
1710           /* CL 3, 4, 5 */
1711                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1712                 4, 5, 6,        /* FSB667, DDR533/400 */
1713                 4, 5, 6,        /* FSB667, DDR667 */
1714         };
1715
1716         static const u8 const cas_table[] = {
1717                 2, 1, 0, 3
1718         };
1719
1720         reg32 = MCHBAR32(C0DRC0);
1721         reg32 |= (1 << 2);      /* Burst Length 8 */
1722         reg32 &= ~( (1 << 13) | (1 << 12) );
1723         MCHBAR32(C0DRC0) = reg32;
1724
1725         reg32 = MCHBAR32(C1DRC0);
1726         reg32 |= (1 << 2);      /* Burst Length 8 */
1727         reg32 &= ~( (1 << 13) | (1 << 12) );
1728         MCHBAR32(C1DRC0) = reg32;
1729
1730         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1731                         SYSINFO_DIMM_NOT_POPULATED) {
1732                 reg32 = MCHBAR32(C0DRC0);
1733                 reg32 |= (1 << 15);
1734                 MCHBAR32(C0DRC0) = reg32;
1735         }
1736
1737         sdram_program_refresh_rate(sysinfo);
1738
1739         sdram_program_cke_tristate(sysinfo);
1740
1741         sdram_program_odt_tristate(sysinfo);
1742
1743         /* Calculate DRT0 */
1744
1745         temp_drt = 0;
1746
1747         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1748         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1749         temp_drt |= (reg32 << 28);
1750
1751         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1752         reg32 += sysinfo->trp;
1753         temp_drt |= (reg32 << 4);
1754
1755         if (sysinfo->memory_frequency == 667) {
1756                 tWTR = 3; /* 667MHz */
1757         } else {
1758                 tWTR = 2; /* 400 and 533 */
1759         }
1760
1761         /* B2B Write to Read Command Spacing */
1762         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1763         temp_drt |= (reg32 << 24);
1764
1765         /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1766         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1767
1768         /* Program Write Auto Precharge to Activate */
1769         off32 = 0;
1770         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1771                 off32 += 3;
1772         }
1773         if (sysinfo->memory_frequency == 667) {
1774                 off32 += 3;
1775         }
1776         off32 += sysinfo->cas - 3;
1777         reg32 = drt0_table[off32];
1778         temp_drt |= (reg32 << 11);
1779
1780         /* Read Auto Precharge to Activate */
1781
1782         temp_drt |= (8 << 0);
1783
1784         MCHBAR32(C0DRT0) = temp_drt;
1785         MCHBAR32(C1DRT0) = temp_drt;
1786
1787         /* Calculate DRT1 */
1788
1789         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1790
1791         /* DRAM RASB Precharge */
1792         temp_drt |= (sysinfo->trp - 2) << 0;
1793
1794         /* DRAM RASB to CASB Delay */
1795         temp_drt |= (sysinfo->trcd - 2) << 4;
1796
1797         /* CASB Latency */
1798         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1799
1800         /* Refresh Cycle Time */
1801         temp_drt |= (sysinfo->trfc) << 10;
1802
1803         /* Pre-All to Activate Delay */
1804         temp_drt |= (0 << 16);
1805
1806         /* Precharge to Precharge Delay stays at 1 clock */
1807         temp_drt |= (0 << 18);
1808
1809         /* Activate to Precharge Delay */
1810         temp_drt |= (sysinfo->tras << 19);
1811
1812         /* Read to Precharge (tRTP) */
1813         if (sysinfo->memory_frequency == 667) {
1814                 temp_drt |= (1 << 28);
1815         } else {
1816                 temp_drt |= (0 << 28);
1817         }
1818
1819         /* Determine page size */
1820         reg32 = 0;
1821         page_size = 1; /* Default: 1k pagesize */
1822         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1823                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1824                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1825                         page_size = 2; /* 2k pagesize */
1826         }
1827
1828         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1829                 reg32 = 1;
1830         }
1831         if (sysinfo->memory_frequency == 667) {
1832                 reg32 = page_size;
1833         }
1834
1835         temp_drt |= (reg32 << 30);
1836
1837         MCHBAR32(C0DRT1) = temp_drt;
1838         MCHBAR32(C1DRT1) = temp_drt;
1839
1840         /* Program DRT2 */
1841         reg32 = MCHBAR32(C0DRT2);
1842         reg32 &= ~(1 << 8);
1843         MCHBAR32(C0DRT2) = reg32;
1844
1845         reg32 = MCHBAR32(C1DRT2);
1846         reg32 &= ~(1 << 8);
1847         MCHBAR32(C1DRT2) = reg32;
1848
1849         /* Calculate DRT3 */
1850         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1851
1852         /* Get old tRFC value */
1853         reg32 = MCHBAR32(C0DRT1) >> 10;
1854         reg32 &= 0x3f;
1855
1856         /* 788nS - tRFC */
1857         switch (sysinfo->memory_frequency) {
1858         case 400: /* 5nS */
1859                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1860                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1861                 break;
1862         case 533: /* 3.75nS */
1863                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1864                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1865                 break;
1866         case 667: /* 3nS */
1867                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1868                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1869                 break;
1870         }
1871
1872         temp_drt |= reg32;
1873
1874         MCHBAR32(C0DRT3) = temp_drt;
1875         MCHBAR32(C1DRT3) = temp_drt;
1876 }
1877
1878 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1879 {
1880         u32 reg32;
1881
1882         printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
1883
1884         if (sdram_capabilities_interleave() &&
1885                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1886                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1887                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1888                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1889                 /* Both channels equipped with DIMMs of the same size */
1890                 sysinfo->interleaved = 1;
1891         } else {
1892                 sysinfo->interleaved = 0;
1893         }
1894
1895         reg32 = MCHBAR32(DCC);
1896         reg32 &= ~(7 << 0);
1897
1898         if(sysinfo->interleaved) {
1899                 /* Dual Channel Interleaved */
1900                 printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
1901                 reg32 |= (1 << 1);
1902         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1903                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1904                 /* Channel 1 only */
1905                 printk(BIOS_DEBUG, "Single Channel 1 only.\n");
1906                 reg32 |= (1 << 2);
1907         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1908                         SYSINFO_DIMM_NOT_POPULATED) {
1909                 /* Dual Channel Assymetric */
1910                 printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
1911                 reg32 |= (1 << 0);
1912         } else {
1913                 /* All bits 0 means Single Channel 0 operation */
1914                 printk(BIOS_DEBUG, "Single Channel 0 only.\n");
1915         }
1916
1917         /* Now disable channel XORing */
1918         reg32 |= (1 << 10);
1919
1920         MCHBAR32(DCC) = reg32;
1921
1922         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1923 }
1924
1925 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1926 {
1927         volatile u16 reg16;
1928
1929         MCHBAR32(PLLMON) = 0x80800000;
1930
1931         sysinfo->fsb_frequency = fsbclk();
1932         if (sysinfo->fsb_frequency == 0xffff)
1933                 die("Unsupported FSB speed");
1934
1935         /* Program CPCTL according to FSB speed */
1936         /* Only write the lower byte */
1937         switch (sysinfo->fsb_frequency) {
1938         case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1939         case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1940         case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1941         }
1942
1943         MCHBAR16(CPCTL) &= ~(1 << 11);
1944
1945         reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1946 }
1947
1948 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1949 {
1950         u8  reg8;
1951         u16 reg16;
1952         u8  freq, second_vco, voltage;
1953
1954 #define CRCLK_166MHz    0x00
1955 #define CRCLK_200MHz    0x01
1956 #define CRCLK_250MHz    0x03
1957 #define CRCLK_400MHz    0x05
1958
1959 #define CDCLK_200MHz    0x00
1960 #define CDCLK_320MHz    0x40
1961
1962 #define VOLTAGE_1_05    0x00
1963 #define VOLTAGE_1_50    0x01
1964
1965         printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
1966
1967         printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
1968
1969         voltage = VOLTAGE_1_05;
1970         if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1971                 voltage = VOLTAGE_1_50;
1972         printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
1973
1974         /* Gate graphics hardware for frequency change */
1975         reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
1976         reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
1977         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1978
1979         /* Get graphics frequency capabilities */
1980         reg8 = sdram_capabilities_core_frequencies();
1981
1982         freq = CRCLK_250MHz;
1983         switch (reg8) {
1984         case GFX_FREQUENCY_CAP_ALL:
1985                 if (voltage == VOLTAGE_1_05)
1986                         freq = CRCLK_250MHz;
1987                 else
1988                         freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
1989                 break;
1990         case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
1991         case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
1992         case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
1993         }
1994
1995         if (freq != CRCLK_400MHz) {
1996                 /* What chipset are we? Force 166MHz for GMS */
1997                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
1998                 if (reg8==2)
1999                         freq = CRCLK_166MHz;
2000         }
2001
2002         printk(BIOS_DEBUG, "Render: ");
2003         switch (freq) {
2004         case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
2005         case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
2006         case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
2007         case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
2008         }
2009
2010         if (i945_silicon_revision() == 0) {
2011                 sysinfo->mvco4x = 1;
2012         } else {
2013                 sysinfo->mvco4x = 0;
2014         }
2015
2016         second_vco = 0;
2017
2018         if (voltage == VOLTAGE_1_50) {
2019                 second_vco = 1;
2020         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
2021                 u16 mem = sysinfo->memory_frequency;
2022                 u16 fsb = sysinfo->fsb_frequency;
2023
2024                 if ( (fsb == 667 && mem == 533) ||
2025                      (fsb == 533 && mem == 533) ||
2026                      (fsb == 533 && mem == 400)) {
2027                         second_vco = 1;
2028                 }
2029
2030                 if (fsb == 667 && mem == 533)
2031                         sysinfo->mvco4x = 1;
2032         }
2033
2034         if (second_vco) {
2035                 sysinfo->clkcfg_bit7=1;
2036         } else {
2037                 sysinfo->clkcfg_bit7=0;
2038         }
2039
2040         /* Graphics Core Render Clock */
2041         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
2042         reg16 &= ~( (7 << 0) | (1 << 13) );
2043         reg16 |= freq;
2044         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
2045
2046         /* Graphics Core Display Clock */
2047         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
2048         reg8 &= ~( (1<<7) | (7<<4) );
2049
2050         if (voltage == VOLTAGE_1_05) {
2051                 reg8 |= CDCLK_200MHz;
2052                 printk(BIOS_DEBUG, " Display: 200MHz\n");
2053         } else {
2054                 reg8 |= CDCLK_320MHz;
2055                 printk(BIOS_DEBUG, " Display: 320MHz\n");
2056         }
2057         pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
2058
2059         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
2060
2061         reg8 |= (1<<3) | (1<<1);
2062         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2063
2064         reg8 |= 0x0f;
2065         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2066
2067         /* Ungate core render and display clocks */
2068         reg8 &= 0xf0;
2069         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2070 }
2071
2072 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
2073 {
2074         u32 clkcfg;
2075         u8 reg8;
2076
2077         printk(BIOS_DEBUG, "Setting Memory Frequency... ");
2078
2079         clkcfg = MCHBAR32(CLKCFG);
2080
2081         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
2082
2083         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
2084
2085         if (sysinfo->mvco4x) {
2086                 printk(BIOS_DEBUG, "MVCO 4x, ");
2087                 clkcfg &= ~(1 << 12);
2088         }
2089
2090         if (sysinfo->clkcfg_bit7) {
2091                 printk(BIOS_DEBUG, "second VCO, ");
2092
2093                 clkcfg |= (1 << 7);
2094         }
2095
2096         switch (sysinfo->memory_frequency) {
2097         case 400: clkcfg |= (2 << 4); break;
2098         case 533: clkcfg |= (3 << 4); break;
2099         case 667: clkcfg |= (4 << 4); break;
2100         default: die("Target Memory Frequency Error");
2101         }
2102
2103         if (MCHBAR32(CLKCFG) == clkcfg) {
2104                 printk(BIOS_DEBUG, "ok (unchanged)\n");
2105                 return;
2106         }
2107
2108         MCHBAR32(CLKCFG) = clkcfg;
2109
2110         /* Make sure the following code is in the
2111          * cache before we execute it.
2112          */
2113         goto cache_code;
2114 vco_update:
2115         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2116         reg8 &= ~(1 << 7);
2117         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2118
2119         clkcfg &= ~(1 << 10);
2120         MCHBAR32(CLKCFG) = clkcfg;
2121         clkcfg |= (1 << 10);
2122         MCHBAR32(CLKCFG) = clkcfg;
2123
2124         asm volatile (
2125                 "       movl $0x100, %%ecx\n"
2126                 "delay_update:\n"
2127                 "       nop\n"
2128                 "       nop\n"
2129                 "       nop\n"
2130                 "       nop\n"
2131                 "       loop delay_update\n"
2132                 : /* No outputs */
2133                 : /* No inputs */
2134                 : "%ecx", "memory"
2135                 );
2136
2137         clkcfg &= ~(1 << 10);
2138         MCHBAR32(CLKCFG) = clkcfg;
2139
2140         goto out;
2141 cache_code:
2142         goto vco_update;
2143 out:
2144
2145         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
2146         printk(BIOS_DEBUG, "ok\n");
2147 }
2148
2149 static void sdram_program_clock_crossing(void)
2150 {
2151         int idx = 0;
2152
2153         /**
2154          * We add the indices according to our clocks from CLKCFG.
2155          */
2156 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
2157         static const u32 data_clock_crossing[] = {
2158                 0x00100401, 0x00000000, /* DDR400 FSB400 */
2159                 0xffffffff, 0xffffffff, /*  nonexistant  */
2160                 0xffffffff, 0xffffffff, /*  nonexistant  */
2161
2162                 0x08040120, 0x00000000, /* DDR400 FSB533 */
2163                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2164                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2165
2166                 0x04020120, 0x00000010, /* DDR400 FSB667 */
2167                 0x10040280, 0x00000040, /* DDR533 FSB667 */
2168                 0x00100401, 0x00000000, /* DDR667 FSB667 */
2169
2170                 0xffffffff, 0xffffffff, /*  nonexistant  */
2171                 0xffffffff, 0xffffffff, /*  nonexistant  */
2172                 0xffffffff, 0xffffffff, /*  nonexistant  */
2173
2174                 0xffffffff, 0xffffffff, /*  nonexistant  */
2175                 0xffffffff, 0xffffffff, /*  nonexistant  */
2176                 0xffffffff, 0xffffffff, /*  nonexistant  */
2177         };
2178
2179         static const u32 command_clock_crossing[] = {
2180                 0x04020208, 0x00000000, /* DDR400 FSB400 */
2181                 0xffffffff, 0xffffffff, /*  nonexistant  */
2182                 0xffffffff, 0xffffffff, /*  nonexistant  */
2183
2184                 0x00060108, 0x00000000, /* DDR400 FSB533 */
2185                 0x04020108, 0x00000000, /* DDR533 FSB533 */
2186                 0xffffffff, 0xffffffff, /*  nonexistant  */
2187
2188                 0x00040318, 0x00000000, /* DDR400 FSB667 */
2189                 0x04020118, 0x00000000, /* DDR533 FSB667 */
2190                 0x02010804, 0x00000000, /* DDR667 FSB667 */
2191
2192                 0xffffffff, 0xffffffff, /*  nonexistant  */
2193                 0xffffffff, 0xffffffff, /*  nonexistant  */
2194                 0xffffffff, 0xffffffff, /*  nonexistant  */
2195
2196                 0xffffffff, 0xffffffff, /*  nonexistant  */
2197                 0xffffffff, 0xffffffff, /*  nonexistant  */
2198                 0xffffffff, 0xffffffff, /*  nonexistant  */
2199         };
2200
2201 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
2202         /* i945 G/P */
2203         static const u32 data_clock_crossing[] = {
2204                 0xffffffff, 0xffffffff, /*  nonexistant  */
2205                 0xffffffff, 0xffffffff, /*  nonexistant  */
2206                 0xffffffff, 0xffffffff, /*  nonexistant  */
2207
2208                 0x10080201, 0x00000000, /* DDR400 FSB533 */
2209                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2210                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2211
2212                 0xffffffff, 0xffffffff, /*  nonexistant  */
2213                 0xffffffff, 0xffffffff, /*  nonexistant  */
2214                 0xffffffff, 0xffffffff, /*  nonexistant  */
2215
2216                 0x04020108, 0x00000000, /* DDR400 FSB800 */
2217                 0x00020108, 0x00000000, /* DDR533 FSB800 */
2218                 0x00080201, 0x00000000, /* DDR667 FSB800 */
2219
2220                 0x00010402, 0x00000000, /* DDR400 FSB1066 */
2221                 0x04020108, 0x00000000, /* DDR533 FSB1066 */
2222                 0x08040110, 0x00000000, /* DDR667 FSB1066 */
2223         };
2224
2225         static const u32 command_clock_crossing[] = {
2226                 0xffffffff, 0xffffffff, /*  nonexistant  */
2227                 0xffffffff, 0xffffffff, /*  nonexistant  */
2228                 0xffffffff, 0xffffffff, /*  nonexistant  */
2229
2230                 0x00010800, 0x00000402, /* DDR400 FSB533 */
2231                 0x01000400, 0x00000200, /* DDR533 FSB533 */
2232                 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
2233
2234                 0xffffffff, 0xffffffff, /*  nonexistant  */
2235                 0xffffffff, 0xffffffff, /*  nonexistant  */
2236                 0xffffffff, 0xffffffff, /*  nonexistant  */
2237
2238                 0x02010804, 0x00000000, /* DDR400 FSB800 */
2239                 0x00010402, 0x00000000, /* DDR533 FSB800 */
2240                 0x04020180, 0x00000008, /* DDR667 FSB800 */
2241
2242                 0x00020904, 0x00000000, /* DDR400 FSB1066 */
2243                 0x02010804, 0x00000000, /* DDR533 FSB1066 */
2244                 0x180601c0, 0x00000020, /* DDR667 FSB1066 */
2245         };
2246 #endif
2247
2248         printk(BIOS_DEBUG, "Programming Clock Crossing...");
2249
2250         printk(BIOS_DEBUG, "MEM=");
2251         switch (memclk()) {
2252         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2253         case 533:       printk(BIOS_DEBUG, "533"); idx += 2; break;
2254         case 667:       printk(BIOS_DEBUG, "667"); idx += 4; break;
2255         default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
2256         }
2257
2258         printk(BIOS_DEBUG, " FSB=");
2259         switch (fsbclk()) {
2260         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2261         case 533:       printk(BIOS_DEBUG, "533"); idx += 6; break;
2262         case 667:       printk(BIOS_DEBUG, "667"); idx += 12; break;
2263         case 800:       printk(BIOS_DEBUG, "800"); idx += 18; break;
2264         case 1066:      printk(BIOS_DEBUG, "1066"); idx += 24; break;
2265         default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
2266         }
2267
2268         if (command_clock_crossing[idx]==0xffffffff) {
2269                 printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
2270         }
2271
2272         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2273         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2274
2275         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2276         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2277         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2278         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2279
2280         printk(BIOS_DEBUG, "... ok\n");
2281 }
2282
2283 static void sdram_disable_fast_dispatch(void)
2284 {
2285         u32 reg32;
2286
2287         reg32 = MCHBAR32(FSBPMC3);
2288         reg32 |= (1 << 1);
2289         MCHBAR32(FSBPMC3) = reg32;
2290
2291         reg32 = MCHBAR32(SBTEST);
2292         reg32 |= (3 << 1);
2293         MCHBAR32(SBTEST) = reg32;
2294 }
2295
2296 static void sdram_pre_jedec_initialization(void)
2297 {
2298         u32 reg32;
2299
2300         reg32 = MCHBAR32(WCC);
2301         reg32 &= 0x113ff3ff;
2302         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2303         MCHBAR32(WCC) = reg32;
2304
2305         MCHBAR32(SMVREFC) |= (1 << 6);
2306
2307         MCHBAR32(MMARB0) &= ~(3 << 17);
2308         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2309
2310         MCHBAR32(MMARB1) &= ~(7 << 8);
2311         MCHBAR32(MMARB1) |= (3 << 8);
2312
2313         /* Adaptive Idle Timer Control */
2314         MCHBAR32(C0AIT) = 0x000006c4;
2315         MCHBAR32(C0AIT+4) = 0x871a066d;
2316
2317         MCHBAR32(C1AIT) = 0x000006c4;
2318         MCHBAR32(C1AIT+4) = 0x871a066d;
2319 }
2320
2321 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2322 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2323 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2324 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2325 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2326 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2327 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2328 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2329
2330 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2331 {
2332         u32 chan0 = 0, chan1 = 0;
2333         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2334
2335         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2336                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2337         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2338                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2339         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2340         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2341
2342         if (sdram_capabilities_enhanced_addressing_xor()) {
2343                 if (!sysinfo->interleaved) {
2344                         /* Single Channel & Dual Channel Assymetric */
2345                         if (chan0_populated) {
2346                                 if (chan0_dualsided) {
2347                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2348                                 } else {
2349                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2350                                 }
2351                         }
2352                         if (chan1_populated) {
2353                                 if (chan1_dualsided) {
2354                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2355                                 } else {
2356                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2357                                 }
2358                         }
2359                 } else {
2360                         /* Interleaved has always both channels populated */
2361                         if (chan0_dualsided) {
2362                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2363                         } else {
2364                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2365                         }
2366
2367                         if (chan1_dualsided) {
2368                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2369                         } else {
2370                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2371                         }
2372                 }
2373         } else {
2374                 if (!sysinfo->interleaved) {
2375                         /* Single Channel & Dual Channel Assymetric */
2376                         if (chan0_populated) {
2377                                 if (chan0_dualsided) {
2378                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2379                                 } else {
2380                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2381                                 }
2382                         }
2383                         if (chan1_populated) {
2384                                 if (chan1_dualsided) {
2385                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2386                                 } else {
2387                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2388                                 }
2389                         }
2390                 } else {
2391                         /* Interleaved has always both channels populated */
2392                         if (chan0_dualsided) {
2393                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2394                         } else {
2395                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2396                         }
2397
2398                         if (chan1_dualsided) {
2399                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2400                         } else {
2401                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2402                         }
2403                 }
2404         }
2405
2406         MCHBAR32(C0DRC1) &= 0x00ffffff;
2407         MCHBAR32(C0DRC1) |= chan0;
2408         MCHBAR32(C1DRC1) &= 0x00ffffff;
2409         MCHBAR32(C1DRC1) |= chan1;
2410 }
2411
2412 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2413 {
2414         u32 reg32;
2415
2416         /* Enable Channel XORing for Dual Channel Interleave */
2417         if (sysinfo->interleaved) {
2418
2419                 reg32 = MCHBAR32(DCC);
2420 #if CONFIG_CHANNEL_XOR_RANDOMIZATION
2421                 reg32 &= ~(1 << 10);
2422                 reg32 |= (1 << 9);
2423 #else
2424                 reg32 &= ~(1 << 9);
2425 #endif
2426                 MCHBAR32(DCC) = reg32;
2427         }
2428
2429         /* DRAM mode optimizations */
2430         sdram_enhanced_addressing_mode(sysinfo);
2431
2432         reg32 = MCHBAR32(FSBPMC3);
2433         reg32 &= ~(1 << 1);
2434         MCHBAR32(FSBPMC3) = reg32;
2435
2436         reg32 = MCHBAR32(SBTEST);
2437         reg32 &= ~(1 << 2);
2438         MCHBAR32(SBTEST) = reg32;
2439
2440         reg32 = MCHBAR32(SBOCC);
2441         reg32 &= 0xffbdb6ff;
2442         reg32 |= (0xbdb6 << 8) | (1 << 0);
2443         MCHBAR32(SBOCC) = reg32;
2444 }
2445
2446 static void sdram_power_management(struct sys_info *sysinfo)
2447 {
2448         u8 reg8;
2449         u16 reg16;
2450         u32 reg32;
2451         int integrated_graphics = 1;
2452         int i;
2453
2454         reg32 = MCHBAR32(C0DRT2);
2455         reg32 &= 0xffffff00;
2456         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2457         reg32 |= (1 << 5) | (1 << 4);
2458         MCHBAR32(C0DRT2) = reg32;
2459
2460         reg32 = MCHBAR32(C1DRT2);
2461         reg32 &= 0xffffff00;
2462         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2463         reg32 |= (1 << 5) | (1 << 4);
2464         MCHBAR32(C1DRT2) = reg32;
2465
2466         reg32 = MCHBAR32(C0DRC1);
2467
2468         reg32 |= (1 << 12) | (1 << 11);
2469         MCHBAR32(C0DRC1) = reg32;
2470
2471         reg32 = MCHBAR32(C1DRC1);
2472
2473         reg32 |= (1 << 12) | (1 << 11);
2474         MCHBAR32(C1DRC1) = reg32;
2475
2476         if (i945_silicon_revision()>1) {
2477                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2478                 u16 peg_bits = (1 << 5) | (1 << 0);
2479
2480                 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2481         } else {
2482                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2483                 u16 peg_bits = (1 << 5) | (1 << 0);
2484
2485                 /* Rev 0 and 1 */
2486                 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2487         }
2488
2489         reg16 = MCHBAR16(UPMC2);
2490         reg16 &= 0xfc00;
2491         reg16 |= 0x0100;
2492         MCHBAR16(UPMC2) = reg16;
2493
2494         MCHBAR32(UPMC3) = 0x000f06ff;
2495
2496         for (i=0; i<5; i++) {
2497                 MCHBAR32(UPMC3) &= ~(1 << 16);
2498                 MCHBAR32(UPMC3) |= (1 << 16);
2499         }
2500
2501         MCHBAR32(GIPMC1) = 0x8000000c;
2502
2503         reg16 = MCHBAR16(CPCTL);
2504         reg16 &= ~(7 << 11);
2505         if (i945_silicon_revision()>2) {
2506                 reg16 |= (6 << 11);
2507         } else {
2508                 reg16 |= (4 << 11);
2509         }
2510         MCHBAR16(CPCTL) = reg16;
2511
2512 #if 0
2513         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2514 #else
2515         if (i945_silicon_revision() != 0) {
2516 #endif
2517                 switch (sysinfo->fsb_frequency) {
2518                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2519                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2520                 }
2521         } else {
2522                 switch (sysinfo->fsb_frequency) {
2523                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2524                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2525                 }
2526         }
2527
2528         MCHBAR32(FSBPMC1) = 0x8000000c;
2529
2530         reg32 = MCHBAR32(C2C3TT);
2531         reg32 &= 0xffff0000;
2532         switch (sysinfo->fsb_frequency) {
2533         case 667: reg32 |= 0x0600; break;
2534         case 533: reg32 |= 0x0480; break;
2535         }
2536         MCHBAR32(C2C3TT) = reg32;
2537
2538         reg32 = MCHBAR32(C3C4TT);
2539         reg32 &= 0xffff0000;
2540         switch (sysinfo->fsb_frequency) {
2541         case 667: reg32 |= 0x0b80; break;
2542         case 533: reg32 |= 0x0980; break;
2543         }
2544         MCHBAR32(C3C4TT) = reg32;
2545
2546         if (i945_silicon_revision() == 0) {
2547                 MCHBAR32(ECO) &= ~(1 << 16);
2548         } else {
2549                 MCHBAR32(ECO) |= (1 << 16);
2550         }
2551
2552 #if 0
2553
2554         if (i945_silicon_revision() == 0) {
2555                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2556         } else {
2557                 MCHBAR32(FSBPMC3) |= (1 << 29);
2558         }
2559 #endif
2560         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2561
2562         MCHBAR32(FSBPMC3) |= (1 << 21);
2563
2564         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2565
2566         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2567
2568         reg32 = MCHBAR32(FSBPMC4);
2569         reg32 &= ~(3 << 24);
2570         reg32 |= ( 2 << 24);
2571         MCHBAR32(FSBPMC4) = reg32;
2572
2573         MCHBAR32(FSBPMC4) |= (1 << 21);
2574
2575         MCHBAR32(FSBPMC4) |= (1 << 5);
2576
2577         if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2578                 /* stepping 0 and 1 or CPUID 6e8 */
2579                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2580         } else {
2581                 MCHBAR32(FSBPMC4) |= (1 << 4);
2582         }
2583
2584         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2585         reg8 |= (1 << 4);
2586         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2587
2588         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2589         reg8 |= (1 << 2);
2590         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2591
2592 #ifdef C2_SELF_REFRESH_DISABLE
2593
2594         if (integrated_graphics) {
2595                 printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
2596                 MCHBAR16(MIPMC4) = 0x0468;
2597                 MCHBAR16(MIPMC5) = 0x046c;
2598                 MCHBAR16(MIPMC6) = 0x046c;
2599         } else {
2600                 MCHBAR16(MIPMC4) = 0x6468;
2601                 MCHBAR16(MIPMC5) = 0x646c;
2602                 MCHBAR16(MIPMC6) = 0x646c;
2603         }
2604 #else
2605         if (integrated_graphics) {
2606                 MCHBAR16(MIPMC4) = 0x04f8;
2607                 MCHBAR16(MIPMC5) = 0x04fc;
2608                 MCHBAR16(MIPMC6) = 0x04fc;
2609         } else {
2610                 MCHBAR16(MIPMC4) = 0x64f8;
2611                 MCHBAR16(MIPMC5) = 0x64fc;
2612                 MCHBAR16(MIPMC6) = 0x64fc;
2613         }
2614
2615 #endif
2616
2617         reg32 = MCHBAR32(PMCFG);
2618         reg32 &= ~(3 << 17);
2619         reg32 |= (2 << 17);
2620         MCHBAR32(PMCFG) = reg32;
2621
2622         MCHBAR32(PMCFG) |= (1 << 4);
2623
2624         reg32 = MCHBAR32(0xc30);
2625         reg32 &= 0xffffff00;
2626         reg32 |= 0x01;
2627         MCHBAR32(0xc30) = reg32;
2628
2629         MCHBAR32(0xb18) &= ~(1 << 21);
2630 }
2631
2632 static void sdram_thermal_management(void)
2633 {
2634
2635         MCHBAR8(TCO1) = 0x00;
2636         MCHBAR8(TCO0) = 0x00;
2637
2638         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2639          * 0x30/0x32.
2640          */
2641
2642         /* TODO This is not implemented yet. Volunteers? */
2643 }
2644
2645 static void sdram_save_receive_enable(void)
2646 {
2647         int i;
2648         u32 reg32;
2649         u8 values[4];
2650
2651         /* The following values are stored to an unused CMOS
2652          * area and restored instead of recalculated in case
2653          * of an S3 resume.
2654          *
2655          * C0WL0REOST [7:0]             -> 8 bit
2656          * C1WL0REOST [7:0]             -> 8 bit
2657          * RCVENMT    [11:8] [3:0]      -> 8 bit
2658          * C0DRT1     [27:24]           -> 4 bit
2659          * C1DRT1     [27:24]           -> 4 bit
2660          */
2661
2662         values[0] = MCHBAR8(C0WL0REOST);
2663         values[1] = MCHBAR8(C1WL0REOST);
2664
2665         reg32 = MCHBAR32(RCVENMT);
2666         values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2667
2668         reg32 = MCHBAR32(C0DRT1);
2669         values[3] = (reg32 >> 24) & 0x0f;
2670         reg32 = MCHBAR32(C1DRT1);
2671         values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2672
2673         /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2674          * so we grab bytes 128 - 131 to save the receive enable values
2675          */
2676
2677         for (i=0; i<4; i++)
2678                 cmos_write(values[i], 128 + i);
2679 }
2680
2681 static void sdram_recover_receive_enable(void)
2682 {
2683         int i;
2684         u32 reg32;
2685         u8 values[4];
2686
2687         for (i=0; i<4; i++)
2688                 values[i] = cmos_read(128 + i);
2689
2690         MCHBAR8(C0WL0REOST) = values[0];
2691         MCHBAR8(C1WL0REOST) = values[1];
2692
2693         reg32 = MCHBAR32(RCVENMT);
2694         reg32 &= ~((0x0f << 8) | (0x0f << 0));
2695         reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2696         MCHBAR32(RCVENMT) = reg32;
2697
2698         reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2699         reg32 |= (u32)(values[3] & 0x0f) << 24;
2700         MCHBAR32(C0DRT1) = reg32;
2701
2702         reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2703         reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2704         MCHBAR32(C1DRT1) = reg32;
2705 }
2706
2707 #include "rcven.c"
2708
2709 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2710 {
2711         MCHBAR32(REPC) |= (1 << 0);
2712
2713         /* enable upper CMOS */
2714         RCBA32(0x3400) = (1 << 2);
2715
2716         /* Program Receive Enable Timings */
2717         if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2718                 sdram_recover_receive_enable();
2719         } else {
2720                 receive_enable_adjust(sysinfo);
2721                 sdram_save_receive_enable();
2722         }
2723
2724         MCHBAR32(C0DRC1) |= (1 << 6);
2725         MCHBAR32(C1DRC1) |= (1 << 6);
2726         MCHBAR32(C0DRC1) &= ~(1 << 6);
2727         MCHBAR32(C1DRC1) &= ~(1 << 6);
2728
2729         MCHBAR32(MIPMC3) |= (0x0f << 0);
2730 }
2731
2732 /**
2733  * @brief Enable On-Die Termination for DDR2.
2734  *
2735  */
2736
2737 static void sdram_on_die_termination(struct sys_info *sysinfo)
2738 {
2739         static const u32 odt[] = {
2740                 0x00024911, 0xe0010000,
2741                 0x00049211, 0xe0020000,
2742                 0x0006db11, 0xe0030000,
2743         };
2744
2745         u32 reg32;
2746         int cas;
2747
2748         reg32 = MCHBAR32(ODTC);
2749         reg32 &= ~(3 << 16);
2750         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2751         MCHBAR32(ODTC) = reg32;
2752
2753         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2754                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2755                 printk(BIOS_DEBUG, "one dimm per channel config.. \n");
2756
2757                 reg32 = MCHBAR32(C0ODT);
2758                 reg32 &= ~(7 << 28);
2759                 MCHBAR32(C0ODT) = reg32;
2760                 reg32 = MCHBAR32(C1ODT);
2761                 reg32 &= ~(7 << 28);
2762                 MCHBAR32(C1ODT) = reg32;
2763         }
2764
2765         cas = sysinfo->cas;
2766
2767         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2768         reg32 |= odt[(cas-3) * 2];
2769         MCHBAR32(C0ODT) = reg32;
2770
2771         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2772         reg32 |= odt[(cas-3) * 2];
2773         MCHBAR32(C1ODT) = reg32;
2774
2775         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2776         reg32 |= odt[((cas-3) * 2) + 1];
2777         MCHBAR32(C0ODT + 4) = reg32;
2778
2779         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2780         reg32 |= odt[((cas-3) * 2) + 1];
2781         MCHBAR32(C1ODT + 4) = reg32;
2782 }
2783
2784 /**
2785  * @brief Enable clocks to populated sockets
2786  */
2787
2788 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2789 {
2790         u8 clocks[2] = { 0, 0 };
2791
2792 #if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM)
2793 #define CLOCKS_WIDTH 2
2794 #elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC)
2795 #define CLOCKS_WIDTH 3
2796 #endif
2797         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2798                 clocks[0] |= (1 << CLOCKS_WIDTH)-1;
2799
2800         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2801                 clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2802
2803         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2804                 clocks[1] |= (1 << CLOCKS_WIDTH)-1;
2805
2806         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2807                 clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2808
2809 #if CONFIG_OVERRIDE_CLOCK_DISABLE
2810         /* Usually system firmware turns off system memory clock signals
2811          * to unused SO-DIMM slots to reduce EMI and power consumption.
2812          * However, the Kontron 986LCD-M does not like unused clock
2813          * signals to be disabled.
2814          */
2815
2816         clocks[0] = 0xf; /* force all clock gate pairs to enable */
2817         clocks[1] = 0xf; /* force all clock gate pairs to enable */
2818 #endif
2819
2820         MCHBAR8(C0DCLKDIS) = clocks[0];
2821         MCHBAR8(C1DCLKDIS) = clocks[1];
2822 }
2823
2824 #define RTT_ODT_NONE    0
2825 #define RTT_ODT_50_OHM  ( (1 << 9) | (1 << 5) )
2826 #define RTT_ODT_75_OHM  (1 << 5)
2827 #define RTT_ODT_150_OHM (1 << 9)
2828
2829 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2830
2831 #define MRS_CAS_3       (3 << 7)
2832 #define MRS_CAS_4       (4 << 7)
2833 #define MRS_CAS_5       (5 << 7)
2834
2835 #define MRS_TWR_3       (2 << 12)
2836 #define MRS_TWR_4       (3 << 12)
2837 #define MRS_TWR_5       (4 << 12)
2838
2839 #define MRS_BT          (1 << 6)
2840
2841 #define MRS_BL4         (2 << 3)
2842 #define MRS_BL8         (3 << 3)
2843
2844 static void sdram_jedec_enable(struct sys_info *sysinfo)
2845 {
2846         int i, nonzero;
2847         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2848
2849         for (i = 0, nonzero = -1; i < 8; i++) {
2850                 if (sysinfo->banksize[i]  == 0) {
2851                         continue;
2852                 }
2853
2854                 printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
2855                 switch (i) {
2856                 case 0:
2857                         /* Start at address 0 */
2858                         bankaddr = 0;
2859                         break;
2860                 case 4:
2861                         if (sysinfo->interleaved) {
2862                                 bankaddr = 0x40;
2863                                 break;
2864                         }
2865                 default:
2866                         if (nonzero != -1) {
2867                                 printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
2868                                 bankaddr += sysinfo->banksize[nonzero] <<
2869                                         (sysinfo->interleaved ? 26 : 25);
2870                                 break;
2871                         }
2872                         /* No populated bank hit before. Start at address 0 */
2873                         bankaddr = 0;
2874                 }
2875
2876                 /* We have a bank with a non-zero size.. Remember it
2877                  * for the next offset we have to calculate
2878                  */
2879                 nonzero = i;
2880
2881                 /* Get CAS latency set up */
2882                 switch (sysinfo->cas) {
2883                 case 5: mrsaddr = MRS_CAS_5; break;
2884                 case 4: mrsaddr = MRS_CAS_4; break;
2885                 case 3: mrsaddr = MRS_CAS_3; break;
2886                 default: die("Jedec Error (CAS).\n");
2887                 }
2888
2889                 /* Get tWR set */
2890                 switch (sysinfo->twr) {
2891                 case 5: mrsaddr |= MRS_TWR_5; break;
2892                 case 4: mrsaddr |= MRS_TWR_4; break;
2893                 case 3: mrsaddr |= MRS_TWR_3; break;
2894                 default: die("Jedec Error (tWR).\n");
2895                 }
2896
2897                 /* Set "Burst Type" */
2898                 mrsaddr |= MRS_BT;
2899
2900                 /* Interleaved */
2901                 if (sysinfo->interleaved) {
2902                         mrsaddr = mrsaddr << 1;
2903                 }
2904
2905                 /* Only burst length 8 supported */
2906                 mrsaddr |= MRS_BL8;
2907
2908                 /* Apply NOP */
2909                 PRINTK_DEBUG("Apply NOP\n");
2910                 do_ram_command(RAM_COMMAND_NOP);
2911                 ram_read32(bankaddr);
2912
2913                 /* Precharge all banks */
2914                 PRINTK_DEBUG("All Banks Precharge\n");
2915                 do_ram_command(RAM_COMMAND_PRECHARGE);
2916                 ram_read32(bankaddr);
2917
2918                 /* Extended Mode Register Set (2) */
2919                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2920                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2921                 ram_read32(bankaddr);
2922
2923                 /* Extended Mode Register Set (3) */
2924                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2925                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2926                 ram_read32(bankaddr);
2927
2928                 /* Extended Mode Register Set */
2929                 PRINTK_DEBUG("Extended Mode Register Set\n");
2930                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2931                 tmpaddr = bankaddr;
2932                 if (!sdram_capabilities_dual_channel()) {
2933                         tmpaddr |= RTT_ODT_75_OHM;
2934                 } else if (sysinfo->interleaved) {
2935                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2936                 } else {
2937                         tmpaddr |= RTT_ODT_150_OHM;
2938                 }
2939                 ram_read32(tmpaddr);
2940
2941                 /* Mode Register Set: Reset DLLs */
2942                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2943                 do_ram_command(RAM_COMMAND_MRS);
2944                 tmpaddr = bankaddr;
2945                 tmpaddr |= mrsaddr;
2946                 /* Set DLL reset bit */
2947                 if (sysinfo->interleaved)
2948                         tmpaddr |= (1 << 12);
2949                 else
2950                         tmpaddr |= (1 << 11);
2951                 ram_read32(tmpaddr);
2952
2953                 /* Precharge all banks */
2954                 PRINTK_DEBUG("All Banks Precharge\n");
2955                 do_ram_command(RAM_COMMAND_PRECHARGE);
2956                 ram_read32(bankaddr);
2957
2958                 /* CAS before RAS Refresh */
2959                 PRINTK_DEBUG("CAS before RAS\n");
2960                 do_ram_command(RAM_COMMAND_CBR);
2961
2962                 /* CBR wants two READs */
2963                 ram_read32(bankaddr);
2964                 ram_read32(bankaddr);
2965
2966                 /* Mode Register Set: Enable DLLs */
2967                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2968                 do_ram_command(RAM_COMMAND_MRS);
2969
2970                 tmpaddr = bankaddr;
2971                 tmpaddr |= mrsaddr;
2972                 ram_read32(tmpaddr);
2973
2974                 /* Extended Mode Register Set */
2975                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2976                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2977
2978                 tmpaddr = bankaddr;
2979                 if (!sdram_capabilities_dual_channel()) {
2980
2981                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2982                 } else if (sysinfo->interleaved) {
2983                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
2984                 } else {
2985                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
2986                 }
2987                 ram_read32(tmpaddr);
2988
2989                 /* Extended Mode Register Set */
2990                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
2991                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2992
2993                 tmpaddr = bankaddr;
2994                 if (!sdram_capabilities_dual_channel()) {
2995                         tmpaddr |= RTT_ODT_75_OHM;
2996                 } else if (sysinfo->interleaved) {
2997                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2998                 } else {
2999                         tmpaddr |= RTT_ODT_150_OHM;
3000                 }
3001                 ram_read32(tmpaddr);
3002         }
3003 }
3004
3005 static void sdram_init_complete(void)
3006 {
3007         PRINTK_DEBUG("Normal Operation\n");
3008         do_ram_command(RAM_COMMAND_NORMAL);
3009 }
3010
3011 static void sdram_setup_processor_side(void)
3012 {
3013         if (i945_silicon_revision() == 0)
3014                 MCHBAR32(FSBPMC3) |= (1 << 2);
3015
3016         MCHBAR8(0xb00) |= 1;
3017
3018         if (i945_silicon_revision() == 0)
3019                 MCHBAR32(SLPCTL) |= (1 << 8);
3020 }
3021
3022 /**
3023  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
3024  */
3025 void sdram_initialize(int boot_path)
3026 {
3027         struct sys_info sysinfo;
3028         u8 reg8, cas_mask;
3029
3030         printk(BIOS_DEBUG, "Setting up RAM controller.\n");
3031
3032         memset(&sysinfo, 0, sizeof(sysinfo));
3033
3034         sysinfo.boot_path = boot_path;
3035
3036         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
3037         sdram_get_dram_configuration(&sysinfo);
3038
3039         /* If error, do cold boot */
3040         sdram_detect_errors(&sysinfo);
3041
3042         /* Check whether we have stacked DIMMs */
3043         sdram_verify_package_type(&sysinfo);
3044
3045         /* Determine common CAS */
3046         cas_mask = sdram_possible_cas_latencies(&sysinfo);
3047
3048         /* Choose Common Frequency */
3049         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
3050
3051         /* Determine smallest common tRAS */
3052         sdram_detect_smallest_tRAS(&sysinfo);
3053
3054         /* Determine tRP */
3055         sdram_detect_smallest_tRP(&sysinfo);
3056
3057         /* Determine tRCD */
3058         sdram_detect_smallest_tRCD(&sysinfo);
3059
3060         /* Determine smallest refresh period */
3061         sdram_detect_smallest_refresh(&sysinfo);
3062
3063         /* Verify all DIMMs support burst length 8 */
3064         sdram_verify_burst_length(&sysinfo);
3065
3066         /* determine tWR */
3067         sdram_detect_smallest_tWR(&sysinfo);
3068
3069         /* Determine DIMM size parameters (rows, columns banks) */
3070         sdram_detect_dimm_size(&sysinfo);
3071
3072         /* determine tRFC */
3073         sdram_detect_smallest_tRFC(&sysinfo);
3074
3075         /* Program PLL settings */
3076         sdram_program_pll_settings(&sysinfo);
3077
3078         /* Program Graphics Frequency */
3079         sdram_program_graphics_frequency(&sysinfo);
3080
3081         /* Program System Memory Frequency */
3082         sdram_program_memory_frequency(&sysinfo);
3083
3084         /* Determine Mode of Operation (Interleaved etc) */
3085         sdram_set_channel_mode(&sysinfo);
3086
3087         /* Program Clock Crossing values */
3088         sdram_program_clock_crossing();
3089
3090         /* Disable fast dispatch */
3091         sdram_disable_fast_dispatch();
3092
3093         /* Enable WIODLL Power Down in ACPI states */
3094         MCHBAR32(C0DMC) |= (1 << 24);
3095         MCHBAR32(C1DMC) |= (1 << 24);
3096
3097         /* Program DRAM Row Boundary/Attribute Registers */
3098
3099         /* program row size DRB and set TOLUD */
3100         sdram_program_row_boundaries(&sysinfo);
3101
3102         /* program page size DRA */
3103         sdram_set_row_attributes(&sysinfo);
3104
3105         /* Program CxBNKARC */
3106         sdram_set_bank_architecture(&sysinfo);
3107
3108         /* Program DRAM Timing and Control registers based on SPD */
3109         sdram_set_timing_and_control(&sysinfo);
3110
3111         /* On-Die Termination Adjustment */
3112         sdram_on_die_termination(&sysinfo);
3113
3114         /* Pre Jedec Initialization */
3115         sdram_pre_jedec_initialization();
3116
3117         /* Perform System Memory IO Initialization */
3118         sdram_initialize_system_memory_io(&sysinfo);
3119
3120         /* Perform System Memory IO Buffer Enable */
3121         sdram_enable_system_memory_io(&sysinfo);
3122
3123         /* Enable System Memory Clocks */
3124         sdram_enable_memory_clocks(&sysinfo);
3125
3126         if (boot_path == BOOT_PATH_NORMAL) {
3127                 /* Jedec Initialization sequence */
3128                 sdram_jedec_enable(&sysinfo);
3129         }
3130
3131         /* Program Power Management Registers */
3132         sdram_power_management(&sysinfo);
3133
3134         /* Post Jedec Init */
3135         sdram_post_jedec_initialization(&sysinfo);
3136
3137         /* Program DRAM Throttling */
3138         sdram_thermal_management();
3139
3140         /* Normal Operations */
3141         sdram_init_complete();
3142
3143         /* Program Receive Enable Timings */
3144         sdram_program_receive_enable(&sysinfo);
3145
3146         /* Enable Periodic RCOMP */
3147         sdram_enable_rcomp();
3148
3149         /* Tell ICH7 that we're done */
3150         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
3151         reg8 &= ~(1 << 7);
3152         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
3153
3154         printk(BIOS_DEBUG, "RAM initialization finished.\n");
3155
3156         sdram_setup_processor_side();
3157 }
3158
3159 unsigned long get_top_of_ram(void)
3160 {
3161         /* This will not work if TSEG is in place! */
3162         u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
3163
3164         return (unsigned long) tom;
3165 }
3166