2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Tyan
5 * Copyright (C) 2006 AMD
6 * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
8 * Copyright (C) 2007 University of Mannheim
9 * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
10 * Copyright (C) 2009 University of Heidelberg
11 * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define RAMINIT_SYSINFO 1
30 #define K8_ALLOCATE_IO_RANGE 1
32 #define QRANK_DIMM_SUPPORT 1
34 #if CONFIG_LOGICAL_CPUS==1
35 #define SET_NB_CFG_54 1
38 //used by init_cpus and fidvid
40 //if we want to wait for core1 done before DQS training, set it to 0
41 #define SET_FIDVID_CORE0_ONLY 1
43 #if CONFIG_K8_REV_F_SUPPORT == 1
44 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
49 #include <device/pci_def.h>
50 #include <device/pci_ids.h>
52 #include <device/pnp_def.h>
53 #include <arch/romcc_io.h>
54 #include <cpu/x86/lapic.h>
55 #include <pc80/mc146818rtc.h>
57 #include <console/console.h>
58 #include "lib/ramtest.c"
60 #include <cpu/amd/model_fxx_rev.h>
62 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
63 #include "northbridge/amd/amdk8/raminit.h"
64 #include "cpu/amd/model_fxx/apic_timer.c"
65 #include "lib/delay.c"
67 #include "cpu/x86/lapic/boot_cpu.c"
68 #include "northbridge/amd/amdk8/reset_test.c"
70 #include "superio/serverengines/pilot/pilot_early_serial.c"
71 #include "superio/serverengines/pilot/pilot_early_init.c"
72 #include "superio/nsc/pc87417/pc87417_early_serial.c"
74 #include "cpu/x86/bist.h"
76 #include "northbridge/amd/amdk8/debug.c"
78 #include "cpu/x86/mtrr/earlymtrr.c"
80 #include "northbridge/amd/amdk8/setup_resource_map.c"
82 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
83 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
85 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
87 static void memreset(int controllers, const struct mem_controller *ctrl)
91 static inline void activate_spd_rom(const struct mem_controller *ctrl)
93 #define SMBUS_SWITCH1 0x70
94 #define SMBUS_SWITCH2 0x72
95 unsigned device = (ctrl->channel0[0]) >> 8;
96 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
97 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
100 static inline int spd_read_byte(unsigned device, unsigned address)
102 return smbus_read_byte(device, address);
105 #include "northbridge/amd/amdk8/amdk8_f.h"
106 #include "northbridge/amd/amdk8/incoherent_ht.c"
107 #include "northbridge/amd/amdk8/coherent_ht.c"
108 #include "northbridge/amd/amdk8/raminit_f.c"
109 #include "lib/generic_sdram.c"
111 #include "cpu/amd/dualcore/dualcore.c"
126 #include "cpu/amd/car/post_cache_as_ram.c"
128 #include "cpu/amd/model_fxx/init_cpus.c"
130 #include "cpu/amd/model_fxx/fidvid.c"
132 #include "northbridge/amd/amdk8/early_ht.c"
137 static void setup_early_ipmi_serial()
139 unsigned char result;
140 char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
141 char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
142 char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
143 char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
144 char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
147 //set channel access system only
148 ipmi_request(5,channel_access);
151 //Set serial/modem config
152 result=ipmi_request(6,serialmodem_conf);
156 result=ipmi_request(4,serial_mux1);
160 result=ipmi_request(4,serial_mux2);
164 result=ipmi_request(4,serial_mux3);
172 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
174 static const uint16_t spd_addr[] = {
184 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
185 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
188 unsigned bsp_apicid = 0;
190 if (!cpu_init_detectedx && boot_cpu()) {
191 /* Nothing special needs to be done to find bus 0 */
192 /* Allow the HT devices to be found */
194 enumerate_ht_chain();
195 bcm5785_enable_rom();
196 bcm5785_enable_lpc();
198 pc87417_enable_dev(RTC_DEV);
202 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
205 pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
209 /* Halt if there was a built in self test failure */
210 report_bist_failure(bist);
213 // setup_early_ipmi_serial();
214 pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
215 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
216 printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
218 #if CONFIG_MEM_TRAIN_SEQ == 1
219 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
221 setup_coherent_ht_domain();
223 wait_all_core0_started();
224 #if CONFIG_LOGICAL_CPUS==1
225 // It is said that we should start core1 after all core0 launched
226 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
227 * So here need to make sure last core0 is started, esp for two way system,
228 * (there may be apic id conflicts in that case)
231 wait_all_other_cores_started(bsp_apicid);
234 /* it will set up chains and store link pair for optimization later */
235 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
236 bcm5785_early_setup();
241 msr=rdmsr(0xc0010042);
242 printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
245 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
246 init_fidvid_bsp(bsp_apicid);
247 // show final fid and vid
250 msr=rdmsr(0xc0010042);
251 printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
255 needs_reset = optimize_link_coherent_ht();
256 needs_reset |= optimize_link_incoherent_ht(sysinfo);
258 // fidvid change will issue one LDTSTOP and the HT change will be effective too
260 printk(BIOS_INFO, "ht reset -\n");
264 allow_all_aps_stop(bsp_apicid);
266 //It's the time to set ctrl in sysinfo now;
267 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
270 //do we need apci timer, tsc...., only debug need it for better output
271 /* all ap stopped? */
272 // init_timer(); // Need to use TMICT to synconize FID/VID
274 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);