src/mainboard/hp/dl145_g1/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <console/console.h>
  16
  17 #include <cpu/amd/model_fxx_rev.h>
  18
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/amd/amdk8/reset_test.c"
  27 #include "northbridge/amd/amdk8/debug.c"
  28 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  29
  30 #include "cpu/x86/mtrr/earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32
  33 #include "northbridge/amd/amdk8/setup_resource_map.c"
  34
  35 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  36
  37 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  38
  39 static void memreset_setup(void)
  40 {
  41    if (is_cpu_pre_c0()) {
  42       /* Set the memreset low */
  43       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  44       /* Ensure the BIOS has control of the memory lines */
  45       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  46    } else {
  47       /* Ensure the CPU has controll of the memory lines */
  48       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  49    }
  50 }
  51
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54    if (is_cpu_pre_c0()) {
  55       udelay(800);
  56       /* Set memreset_high */
  57       outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  58       udelay(90);
  59    }
  60 }
  61
  62 #define SMBUS_HUB 0x18
  63
  64 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66   int ret,i;
  67   unsigned device=(ctrl->channel0[0])>>8;
  68   /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  69   i=2;
  70   do {
  71     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  72   } while ((ret!=0) && (i-->0));
  73
  74   smbus_write_byte(SMBUS_HUB, 0x03, 0);
  75 }
  76
  77 static inline void change_i2c_mux(unsigned device)
  78 {
  79   int ret, i;
  80   print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  81   i=2;
  82   do {
  83     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  84     print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  85   } while ((ret!=0) && (i-->0));
  86   ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  87   print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  88 }
  89
  90 static inline int spd_read_byte(unsigned device, unsigned address)
  91 {
  92         return smbus_read_byte(device, address);
  93 }
  94
  95 #include "northbridge/amd/amdk8/raminit.c"
  96 #include "resourcemap.c"
  97 #include "northbridge/amd/amdk8/coherent_ht.c"
  98 #include "lib/generic_sdram.c"
  99
 100 #include "cpu/amd/dualcore/dualcore.c"
 101
 102 #define RC0 ((1<<1)<<8) // Not sure about these values
 103 #define RC1 ((1<<2)<<8) // Not sure about these values
 104
 105 #define DIMM0 0x50
 106 #define DIMM1 0x51
 107 #define DIMM2 0x52
 108 #define DIMM3 0x53
 109
 110 #include "cpu/amd/car/post_cache_as_ram.c"
 111
 112 #include "cpu/amd/model_fxx/init_cpus.c"
 113
 114 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 115 #include "northbridge/amd/amdk8/early_ht.c"
 116
 117
 118 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 119 {
 120         static const uint16_t spd_addr [] = {
 121                         //first node
 122                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 123                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 124 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 125                         //second node
 126                         RC1|DIMM0, RC1|DIMM2, 0, 0,
 127                         RC1|DIMM1, RC1|DIMM3, 0, 0,
 128 #endif
 129         };
 130
 131         int needs_reset;
 132         unsigned bsp_apicid = 0;
 133
 134         struct mem_controller ctrl[8];
 135         unsigned nodes;
 136
 137         if (!cpu_init_detectedx && boot_cpu()) {
 138                 /* Nothing special needs to be done to find bus 0 */
 139                 /* Allow the HT devices to be found */
 140
 141                 enumerate_ht_chain();
 142
 143                 /* Setup the amd8111 */
 144                 amd8111_enable_rom();
 145         }
 146
 147         if (bist == 0) {
 148                 bsp_apicid = init_cpus(cpu_init_detectedx);
 149         }
 150
 151 //      post_code(0x32);
 152
 153         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 154         uart_init();
 155         console_init();
 156
 157         /* Halt if there was a built in self test failure */
 158         report_bist_failure(bist);
 159
 160         setup_dl145g1_resource_map();
 161         //setup_default_resource_map();
 162
 163         needs_reset = setup_coherent_ht_domain();
 164
 165         wait_all_core0_started();
 166 #if CONFIG_LOGICAL_CPUS==1
 167         // It is said that we should start core1 after all core0 launched
 168         start_other_cores();
 169         wait_all_other_cores_started(bsp_apicid);
 170 #endif
 171
 172         needs_reset |= ht_setup_chains_x();
 173
 174         if (needs_reset) {
 175                 print_info("ht reset -\n");
 176                 soft_reset();
 177         }
 178
 179         enable_smbus();
 180
 181         int i;
 182         for(i=0;i<2;i++) {
 183                 activate_spd_rom(&ctrl[i]);
 184         }
 185         for(i=2;i<8;i<<=1) {
 186                 change_i2c_mux(i);
 187         }
 188
 189         //dump_spd_registers(&ctrl[0]);
 190         //dump_spd_registers(&ctrl[1]);
 191         //dump_smbus_registers();
 192
 193         allow_all_aps_stop(bsp_apicid);
 194
 195         nodes = get_nodes();
 196         //It's the time to set ctrl now;
 197         fill_mem_ctrl(nodes, ctrl, spd_addr);
 198
 199         memreset_setup();
 200         sdram_initialize(nodes, ctrl);
 201
 202         //dump_pci_devices();
 203
 204         post_cache_as_ram();
 205 }