src/mainboard/tyan/s4882/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include <lib.h>
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29
  30 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  31
  32 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  33
  34 static void memreset_setup(void)
  35 {
  36    if (is_cpu_pre_c0()) {
  37         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  38    }
  39    else {
  40         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  41    }
  42         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  43 }
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl)
  46 {
  47    if (is_cpu_pre_c0()) {
  48         udelay(800);
  49         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  50         udelay(90);
  51    }
  52 }
  53 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  54 {
  55 #define SMBUS_HUB 0x18
  56         int ret,i;
  57         unsigned device=(ctrl->channel0[0])>>8;
  58         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  59         i=2;
  60         do {
  61                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  62         } while ((ret!=0) && (i-->0));
  63
  64         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  65 }
  66 #if 0
  67 static inline void change_i2c_mux(unsigned device)
  68 {
  69 #define SMBUS_HUB 0x18
  70         int ret, i;
  71         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  72         i=2;
  73         do {
  74                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  75                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  76         } while ((ret!=0) && (i-->0));
  77         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  78         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  79 }
  80 #endif
  81
  82 static inline int spd_read_byte(unsigned device, unsigned address)
  83 {
  84         return smbus_read_byte(device, address);
  85 }
  86
  87 #define QRANK_DIMM_SUPPORT 1
  88
  89 #include "northbridge/amd/amdk8/raminit.c"
  90 #include "northbridge/amd/amdk8/coherent_ht.c"
  91 #include "lib/generic_sdram.c"
  92
  93  /* tyan does not want the default */
  94 #include "resourcemap.c"
  95
  96 #if CONFIG_LOGICAL_CPUS==1
  97 #define SET_NB_CFG_54 1
  98 #endif
  99 #include "cpu/amd/dualcore/dualcore.c"
 100
 101 #define RC0 ((1<<2)<<8)
 102 #define RC1 ((1<<1)<<8)
 103 #define RC2 ((1<<4)<<8)
 104 #define RC3 ((1<<3)<<8)
 105
 106 #define DIMM0 0x50
 107 #define DIMM1 0x51
 108 #define DIMM2 0x52
 109 #define DIMM3 0x53
 110
 111
 112
 113 #include "cpu/amd/car/post_cache_as_ram.c"
 114
 115 #include "cpu/amd/model_fxx/init_cpus.c"
 116
 117 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 118 #include "northbridge/amd/amdk8/early_ht.c"
 119
 120 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 121 {
 122         static const uint16_t spd_addr [] = {
 123                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 124                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 125 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 126                         RC1|DIMM0, RC1|DIMM2, 0, 0,
 127                         RC1|DIMM1, RC1|DIMM3, 0, 0,
 128 #endif
 129 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 130                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 131                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 132                         RC3|DIMM0, RC3|DIMM2, 0, 0,
 133                         RC3|DIMM1, RC3|DIMM3, 0, 0,
 134 #endif
 135         };
 136
 137         int needs_reset;
 138         unsigned bsp_apicid = 0;
 139
 140         struct mem_controller ctrl[8];
 141         unsigned nodes;
 142
 143         if (!cpu_init_detectedx && boot_cpu()) {
 144                 /* Nothing special needs to be done to find bus 0 */
 145                 /* Allow the HT devices to be found */
 146
 147                 enumerate_ht_chain();
 148
 149                 amd8111_enable_rom();
 150         }
 151
 152         if (bist == 0) {
 153                 bsp_apicid = init_cpus(cpu_init_detectedx);
 154         }
 155
 156
 157         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 158         uart_init();
 159         console_init();
 160
 161         /* Halt if there was a built in self test failure */
 162         report_bist_failure(bist);
 163
 164         setup_s4882_resource_map();
 165
 166         needs_reset = setup_coherent_ht_domain();
 167
 168         wait_all_core0_started();
 169 #if CONFIG_LOGICAL_CPUS==1
 170         // It is said that we should start core1 after all core0 launched
 171         start_other_cores();
 172         wait_all_other_cores_started(bsp_apicid);
 173 #endif
 174
 175         // automatically set that for you, but you might meet tight space
 176         needs_reset |= ht_setup_chains_x();
 177
 178         if (needs_reset) {
 179                 print_info("ht reset -\n");
 180                 soft_reset();
 181         }
 182
 183         allow_all_aps_stop(bsp_apicid);
 184
 185         nodes = get_nodes();
 186         //It's the time to set ctrl now;
 187         fill_mem_ctrl(nodes, ctrl, spd_addr);
 188
 189         enable_smbus();
 190
 191         memreset_setup();
 192         sdram_initialize(nodes, ctrl);
 193
 194         post_cache_as_ram();
 195
 196 }
 197