src/mainboard/tyan/s2882/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include <pc80/mc146818rtc.h>
  11 #include <console/console.h>
  12 #include "lib/ramtest.c"
  13
  14 #include <cpu/amd/model_fxx_rev.h>
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  34
  35 static void memreset_setup(void)
  36 {
  37    if (is_cpu_pre_c0()) {
  38         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  39    }
  40    else {
  41         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  42    }
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48    if (is_cpu_pre_c0()) {
  49         udelay(800);
  50         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  51         udelay(90);
  52    }
  53 }
  54
  55 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  56 {
  57         /* nothing to do */
  58 }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 #define QRANK_DIMM_SUPPORT 1
  66
  67 #include "northbridge/amd/amdk8/raminit.c"
  68 #include "northbridge/amd/amdk8/resourcemap.c"
  69 #include "northbridge/amd/amdk8/coherent_ht.c"
  70 #include "lib/generic_sdram.c"
  71
  72 #if CONFIG_LOGICAL_CPUS==1
  73 #define SET_NB_CFG_54 1
  74 #endif
  75 #include "cpu/amd/dualcore/dualcore.c"
  76
  77 #define FIRST_CPU  1
  78 #define SECOND_CPU 1
  79 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  80
  81
  82
  83 #include "cpu/amd/car/post_cache_as_ram.c"
  84
  85 #include "cpu/amd/model_fxx/init_cpus.c"
  86
  87 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  88 #include "northbridge/amd/amdk8/early_ht.c"
  89
  90 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  91 {
  92         static const struct mem_controller cpu[] = {
  93                 {
  94                         .node_id = 0,
  95                         .f0 = PCI_DEV(0, 0x18, 0),
  96                         .f1 = PCI_DEV(0, 0x18, 1),
  97                         .f2 = PCI_DEV(0, 0x18, 2),
  98                         .f3 = PCI_DEV(0, 0x18, 3),
  99                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 100                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 101                 },
 102 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 103                 {
 104                         .node_id = 1,
 105                         .f0 = PCI_DEV(0, 0x19, 0),
 106                         .f1 = PCI_DEV(0, 0x19, 1),
 107                         .f2 = PCI_DEV(0, 0x19, 2),
 108                         .f3 = PCI_DEV(0, 0x19, 3),
 109                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 110                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 111                 },
 112 #endif
 113         };
 114
 115         int needs_reset;
 116
 117         if (!cpu_init_detectedx && boot_cpu()) {
 118                 /* Nothing special needs to be done to find bus 0 */
 119                 /* Allow the HT devices to be found */
 120
 121                 enumerate_ht_chain();
 122
 123                 amd8111_enable_rom();
 124         }
 125
 126         if (bist == 0) {
 127                 init_cpus(cpu_init_detectedx);
 128         }
 129
 130
 131         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 132         uart_init();
 133         console_init();
 134
 135         /* Halt if there was a built in self test failure */
 136         report_bist_failure(bist);
 137
 138         setup_default_resource_map();
 139
 140         needs_reset = setup_coherent_ht_domain();
 141
 142 #if CONFIG_LOGICAL_CPUS==1
 143         // It is said that we should start core1 after all core0 launched
 144         start_other_cores();
 145 #endif
 146         // automatically set that for you, but you might meet tight space
 147         needs_reset |= ht_setup_chains_x();
 148
 149         if (needs_reset) {
 150                 print_info("ht reset -\n");
 151                 soft_reset();
 152         }
 153
 154         enable_smbus();
 155
 156         memreset_setup();
 157         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 158
 159         post_cache_as_ram();
 160
 161 }
 162