src/mainboard/tyan/s2891/romstage.c

   1 //used by raminit
   2 #define QRANK_DIMM_SUPPORT 1
   3
   4 #if CONFIG_LOGICAL_CPUS==1
   5 #define SET_NB_CFG_54 1
   6 #endif
   7
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <device/pci_def.h>
  11 #include <arch/io.h>
  12 #include <device/pnp_def.h>
  13 #include <arch/romcc_io.h>
  14 #include <cpu/x86/lapic.h>
  15 #include <pc80/mc146818rtc.h>
  16 #include <console/console.h>
  17 #include <lib.h>
  18
  19 #include <cpu/amd/model_fxx_rev.h>
  20
  21 #include "northbridge/amd/amdk8/incoherent_ht.c"
  22 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  23 #include "northbridge/amd/amdk8/raminit.h"
  24 #include "cpu/amd/model_fxx/apic_timer.c"
  25 #include "lib/delay.c"
  26 #include "cpu/x86/lapic/boot_cpu.c"
  27 #include "northbridge/amd/amdk8/reset_test.c"
  28 #include "northbridge/amd/amdk8/debug.c"
  29 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  30
  31 #include "cpu/x86/mtrr/earlymtrr.c"
  32 #include "cpu/x86/bist.h"
  33
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  37
  38 static void memreset_setup(void)
  39 {
  40 }
  41
  42 static void memreset(int controllers, const struct mem_controller *ctrl)
  43 {
  44 }
  45
  46 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  47 {
  48         /* nothing to do */
  49 }
  50
  51 static inline int spd_read_byte(unsigned device, unsigned address)
  52 {
  53         return smbus_read_byte(device, address);
  54 }
  55
  56 #include "northbridge/amd/amdk8/raminit.c"
  57 #include "northbridge/amd/amdk8/coherent_ht.c"
  58 #include "lib/generic_sdram.c"
  59
  60  /* tyan does not want the default */
  61 #include "resourcemap.c"
  62
  63 #include "cpu/amd/dualcore/dualcore.c"
  64
  65 #define CK804_NUM 1
  66 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  67 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  68
  69
  70
  71 #include "cpu/amd/car/post_cache_as_ram.c"
  72
  73 #include "cpu/amd/model_fxx/init_cpus.c"
  74
  75 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  76 #include "northbridge/amd/amdk8/early_ht.c"
  77
  78 static void sio_setup(void)
  79 {
  80         uint32_t dword;
  81         uint8_t byte;
  82
  83         /* subject decoding*/
  84         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  85         byte |= 0x20;
  86         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  87
  88         /* LPC Positive Decode 0 */
  89         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  90         /* Serial 0, Serial 1 */
  91         dword |= (1<<0) | (1<<1);
  92         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  93
  94 #if 1
  95         /* s2891 has onboard LPC port 80 */
  96         /*Hope I can enable port 80 here
  97         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
  98         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
  99         dword |= (1<<16);
 100         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 101 #endif
 102 }
 103
 104 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 105 {
 106         static const uint16_t spd_addr [] = {
 107                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 108                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 109 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 110                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 111                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 112 #endif
 113         };
 114
 115         int needs_reset;
 116         unsigned bsp_apicid = 0;
 117
 118         struct mem_controller ctrl[8];
 119         unsigned nodes;
 120
 121         if (!cpu_init_detectedx && boot_cpu()) {
 122                 /* Nothing special needs to be done to find bus 0 */
 123                 /* Allow the HT devices to be found */
 124
 125                 enumerate_ht_chain();
 126
 127                 sio_setup();
 128
 129                 /* Setup the ck804 */
 130                 ck804_enable_rom();
 131         }
 132
 133         if (bist == 0) {
 134                 bsp_apicid = init_cpus(cpu_init_detectedx);
 135         }
 136
 137 //      post_code(0x32);
 138
 139         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 140         uart_init();
 141         console_init();
 142
 143         /* Halt if there was a built in self test failure */
 144         report_bist_failure(bist);
 145
 146         setup_s2891_resource_map();
 147 #if 0
 148         dump_pci_device(PCI_DEV(0, 0x18, 0));
 149         dump_pci_device(PCI_DEV(0, 0x19, 0));
 150 #endif
 151
 152         needs_reset = setup_coherent_ht_domain();
 153
 154         wait_all_core0_started();
 155 #if CONFIG_LOGICAL_CPUS==1
 156         // It is said that we should start core1 after all core0 launched
 157         start_other_cores();
 158         wait_all_other_cores_started(bsp_apicid);
 159 #endif
 160
 161         needs_reset |= ht_setup_chains_x();
 162
 163         needs_reset |= ck804_early_setup_x();
 164
 165         if (needs_reset) {
 166                 printk(BIOS_INFO, "ht reset -\n");
 167                 soft_reset();
 168         }
 169
 170         allow_all_aps_stop(bsp_apicid);
 171
 172         nodes = get_nodes();
 173         //It's the time to set ctrl now;
 174         fill_mem_ctrl(nodes, ctrl, spd_addr);
 175
 176         enable_smbus();
 177 #if 0
 178         dump_spd_registers(&cpu[0]);
 179 #endif
 180 #if 0
 181         dump_smbus_registers();
 182 #endif
 183
 184         memreset_setup();
 185         sdram_initialize(nodes, ctrl);
 186
 187 #if 0
 188         print_pci_devices();
 189 #endif
 190
 191 #if 0
 192         dump_pci_devices();
 193 #endif
 194
 195         post_cache_as_ram();
 196 }
 197