src/mainboard/tyan/s2735/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include "lib/ramtest.c"
  12
  13 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  14 #include "northbridge/intel/e7501/raminit.h"
  15
  16 #include "northbridge/intel/e7501/debug.c"
  17 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  18
  19 #include "cpu/x86/mtrr/earlymtrr.c"
  20 #include "cpu/x86/bist.h"
  21
  22 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  23
  24 // FIXME: There's another hard_reset() in reset.c. Why?
  25 static void hard_reset(void)
  26 {
  27         /* full reset */
  28         outb(0x0a, 0x0cf9);
  29         outb(0x0e, 0x0cf9);
  30 }
  31
  32 static inline int spd_read_byte(unsigned device, unsigned address)
  33 {
  34         return smbus_read_byte(device, address);
  35 }
  36
  37 #include "northbridge/intel/e7501/raminit.c"
  38 #include "northbridge/intel/e7501/reset_test.c"
  39 #include "lib/generic_sdram.c"
  40
  41 void main(unsigned long bist)
  42 {
  43         static const struct mem_controller memctrl[] = {
  44                 {
  45                         .d0 = PCI_DEV(0, 0, 0),
  46                         .d0f1 = PCI_DEV(0, 0, 1),
  47                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
  48                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
  49                 },
  50         };
  51
  52         if (bist == 0) {
  53                 enable_lapic();
  54         }
  55
  56         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  57         uart_init();
  58         console_init();
  59
  60         /* Halt if there was a built in self test failure */
  61         report_bist_failure(bist);
  62
  63         if(bios_reset_detected()) {
  64                 hard_reset();
  65         }
  66
  67         enable_smbus();
  68 #if 0
  69         dump_spd_registers(&memctrl[0]);
  70 #endif
  71 #if 0
  72         dump_smbus_registers();
  73 #endif
  74
  75         sdram_initialize(1, memctrl);
  76
  77 #if 0
  78         dump_pci_devices();
  79 #endif
  80
  81 #if 1
  82         dump_pci_device(PCI_DEV(0, 0, 0));
  83 #endif
  84 }
  85