Stefan Reinauer [Sun, 26 Sep 2010 15:04:14 +0000 (15:04 +0000)]
update license header for dumpmmcr utility according to svn history.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5850
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Uwe Hermann [Sun, 26 Sep 2010 10:34:36 +0000 (10:34 +0000)]
Fix the build, CONFIG_USBDEBUG must always be defined (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5849
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Uwe Hermann [Sun, 26 Sep 2010 07:35:55 +0000 (07:35 +0000)]
Only show the USB Debug Port kconfig option to the user if a mainboard
is selected that uses a chipset which actually has that functionality _and_
we have code to initialize the Debug Port in coreboot (for that chipset).
Also, remove the duplicate list of PCI IDs and just link to the wiki page at:
http://www.coreboot.org/EHCI_Debug_Port
The list is now less useful in the kconfig help as this option will only
appear for those boards where it's actually supported.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848
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Uwe Hermann [Sat, 25 Sep 2010 23:47:15 +0000 (23:47 +0000)]
Various Debug Port southbridge implementation fixes / cosmetics.
- Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of
hardcoding their values.
- SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE.
- ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC.
- s/uint32_t/u32/.
- Cosmetics, whitespace, coding style fixes and added code comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847
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Patrick Georgi [Sat, 25 Sep 2010 17:24:10 +0000 (17:24 +0000)]
Mark read-only data as read-only, so the global vars test doesn't fail on it.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5846
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Sat, 25 Sep 2010 17:01:13 +0000 (17:01 +0000)]
Add an EHCI driver to libpayload's USB stack.
Interrupt transfer support is missing (ie. no keyboard),
bulk and control transfers work (ie. mass storage).
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5845
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Uwe Hermann [Sat, 25 Sep 2010 16:17:20 +0000 (16:17 +0000)]
Drop some useless "../../../" in #includes (trivial).
Build-tested using abuild.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5844
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 25 Sep 2010 14:58:28 +0000 (14:58 +0000)]
Various CONFIG_DEBUG_RAM_SETUP related fixes (trivial).
Some boards still used the old DEBUG_RAM_SETUP (without _CONFIG prefix).
Also, consistently use "#if CONFIG_DEBUG_RAM_SETUP" (not #ifdef) as we do
elsewhere.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5843
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 25 Sep 2010 14:23:31 +0000 (14:23 +0000)]
Various USB Debug Port fixes (trivial).
- Drop unused DBGP_DEFAULT #defines on boards with chipsets where no
USB Debug Port support is implemented anyway (at the moment, at least):
- hp/dl145_g3
- hp/dl165_g6_fam10
- ICH7: Move unrelated code out of set_debug_port(). All ICH southbridges
with Debug Port hardcode the physical USB port used as Debug Port to 1.
In other words, this port is not user-configurable (as seems to be
the case on NVIDIA MCP55). For now we keep the 'port' parameter in order
to not change the API, this might be fixed differently later.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5842
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Patrick Georgi [Sat, 25 Sep 2010 14:15:41 +0000 (14:15 +0000)]
Make globals in romstage break the build, so we don't have to
wonder why variables in .data or .bss (both somewhere in ROM space)
are wrong.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5841
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Uwe Hermann [Sat, 25 Sep 2010 12:37:33 +0000 (12:37 +0000)]
Drop <cpu/amd/mtrr.h> #include from Intel CPUs.
Three CAR implementations on Intel CPUs include <cpu/amd/mtrr.h>, which
is obviously wrong, so drop the #includes. None of their #defines are used
in the Intel code.
Build-tested with two of the affected boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5840
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Myles Watson [Sat, 25 Sep 2010 10:42:55 +0000 (10:42 +0000)]
Keep the mc146818rtc.h include close to the option table include where
possible.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5839
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Stefan Reinauer [Sat, 25 Sep 2010 10:40:47 +0000 (10:40 +0000)]
- Fix race condition in option_table.h generation by moving the include
statement to those files that actually need it. This significantly
reduces the number of dependencies, so it's no longer extremely ugly to
specify them manually (see the src/pc80/Makefile.inc portion)
- Add double include guards around option_table.h defines
- Also, drop the AMD DBM690T work around for the issue
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838
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Uwe Hermann [Fri, 24 Sep 2010 23:37:25 +0000 (23:37 +0000)]
Make SB600/SB700 more similar for easier diffs (trivial).
Also fixes random whitespace issues, typos, etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5837
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Patrick Georgi [Fri, 24 Sep 2010 22:15:54 +0000 (22:15 +0000)]
Fix CCACHE handling, and make use of ccache's BASEDIR feature
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5836
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 24 Sep 2010 18:42:56 +0000 (18:42 +0000)]
Automatically fetch bus information for mptable from
the device tree, instead of using hardcoded values.
If this changes behaviour, this is either
- a bug in mptable_write_buses(), or
- a bug in the old mptable or device config, that is
they were inconsistent.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5835
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Patrick Georgi [Fri, 24 Sep 2010 18:28:50 +0000 (18:28 +0000)]
Undo stupid mistake in r5832
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5834
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Uwe Hermann [Fri, 24 Sep 2010 18:18:20 +0000 (18:18 +0000)]
Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.
Without a (currently) dummy set_debug_port() function the build fails,
this may or may not be fixed differently in the future.
Manually build-tested on all SB600/SB700 boards, and tested on hardware on
one SB600 board I own, works fine.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 24 Sep 2010 18:12:46 +0000 (18:12 +0000)]
Fix hp/dl165_g6_fam10 build. Failed to take r5800 and
another recent change into account.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5832
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Arne Georg Gleditsch [Fri, 24 Sep 2010 17:35:32 +0000 (17:35 +0000)]
Add support for HP DL165-G6 with Fam10 CPU.
Original patch was
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Updates to accomodate changes in coreboot are
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5831
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Uwe Hermann [Thu, 23 Sep 2010 18:48:27 +0000 (18:48 +0000)]
Whitespace/typo/cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5830
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Stefan Reinauer [Thu, 23 Sep 2010 18:29:40 +0000 (18:29 +0000)]
Fix some wrong capitalizations, reformat comments, fix a typo.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5829
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Uwe Hermann [Thu, 23 Sep 2010 18:16:46 +0000 (18:16 +0000)]
USB Debug Port related license header fixes (trivial).
- Add missing license headers, or missing (C) lines to various files.
(most are from AMD / Yinghai Lu, based on svn logs)
- src/include/ehci.h was taken from the Linux kernel. Updating it to
the latest version from git HEAD while I'm at it (build-tested with
one board). It also sports some new EHCI 1.1 addendum #defines which
we may or may not need.
This new file also already has a proper GPL header.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5828
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Marc Jones [Thu, 23 Sep 2010 15:38:55 +0000 (15:38 +0000)]
Generate and extract debug sysmbols for coreboot. *.debug files can be
used for source level debug.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5827
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Uwe Hermann [Wed, 22 Sep 2010 23:42:32 +0000 (23:42 +0000)]
Fix a compiler warning in src/lib/usbdebug.c (trivial).
The 'delay' variable shadows the global 'delay()' function, yielding
this compiler warning/error:
src/pc80/../lib/usbdebug.c: In function `ehci_reset_port':
src/pc80/../lib/usbdebug.c:281: error: declaration of `delay' shadows a global declaration
src/lib/delay.c:9: error: shadowed declaration is here
This fixes the issue by renaming the 'delay' variable to 'delay_ms'.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5826
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Rudolf Marek [Wed, 22 Sep 2010 22:46:47 +0000 (22:46 +0000)]
Here is a proposed way how to handle the SATA PHY settings on SB700. It
consits of weak function which always exists (with defaults) and a possibility to
override this with normal function in main.c. This is the other way of
doing that and not using the devictree.cb.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825
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Uwe Hermann [Tue, 21 Sep 2010 23:53:47 +0000 (23:53 +0000)]
First round of i82801ax clean-ups (trivial).
After we splitted up the old i82801xx driver which was supposed to support
multiple generations of ICH* chipsets, some of the generified code
is now obsolete in i82801ax which should only cover ICH/ICH0 and none of
the later ICH* generations.
Hence:
- Drop "struct pci_driver" entries for chipsets other than ICH/ICH0.
- Drop drivers for hardware that is not present on ICH/ICH0: NIC, SATA, EHCI.
- Drop PIRQE-PIRQH #defines and code, not available on this chipset.
- Simplify some parts of the code (more will follow).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5824
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Uwe Hermann [Tue, 21 Sep 2010 21:16:27 +0000 (21:16 +0000)]
Cut the crap.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5823
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Zheng Bao [Tue, 21 Sep 2010 02:51:31 +0000 (02:51 +0000)]
Complete the code which was missing.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5822
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Zheng Bao [Tue, 21 Sep 2010 01:24:55 +0000 (01:24 +0000)]
Fix the typo. Field DisAutoRefresh is in DramTimngHi.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5821
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Keith Hui [Mon, 20 Sep 2010 23:41:37 +0000 (23:41 +0000)]
A number of cleanups for 440BX raminit code.
Resolves a number of TODOs items within, and clarified a number of other TODOs.
Change register_values[] from long to u8 (byte). For what we are doing
this is sufficient and makes it only 1/4 the size.
Remove a hard-coding of SDRAMC register that is redundant and now
incorrect, now that SDRAMC is conditioned on SDRAMPWR_4DIMM Kconfig
and set through register_values[].
This fixes all boards with 3 DIMM slots (e.g. ASUS P2B, A-Trend ATC-6220).
RPS registers are now set in runtime code; remove it from
register_values[] table.
Bring DUMPNORTH() back. The code it refers to is still there.
Move #define of NB up so the DUMPNORTH() macro can use it.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5820
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Uwe Hermann [Sun, 19 Sep 2010 21:12:05 +0000 (21:12 +0000)]
Make ASUS P3B-F RAM init actually work by enabling SPD access.
On this board all reads from SPD return 0xff by default, there's a custom
GPIO fiddling needed to enable access to the SPD SMBus offsets at
0x50-0x53. While coreboot actually sort of booted sometimes before r5193,
that was just sheer luck as the RAM init was hardcoded in certain ways.
Since the proper, more heavily SPD-based RAM init the brokenness of the
ASUS P3B-F RAM init was becoming visible.
This patch uses GPIOs to enable access to the SPD SMBus offsets,
and resets the GPIOs again after RAM init (this is needed to allow for
lm-sensors to work, for example).
Tested successfully on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819
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Scott Duplichan [Fri, 17 Sep 2010 21:38:40 +0000 (21:38 +0000)]
AMD Fam10 code breaks with gcc 4.5.0.
Root cause: After function STOP_CAR_AND_CPU disables cache as
ram, the cache as ram stack can no longer be used. Called
functions must be inlined to avoid stack usage. Also, the
compiler must keep local variables register based and not
allocated them from the stack. With gcc 4.5.0, some functions
declared as inline are not being inlined. This patch forces
these functions to always be inlined by adding the qualifier
__attribute__((always_inline)) to their declaration.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5818
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Arne Georg Gleditsch [Fri, 17 Sep 2010 00:13:52 +0000 (00:13 +0000)]
Clear bit 35 of msr c001_102a in Fam10 rev C cores.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5817
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Marc Jones [Thu, 16 Sep 2010 21:36:44 +0000 (21:36 +0000)]
Add default libpayload build, xcompile, and lpgcc setup to tint.
Signed-off-by: Marc Jones <marc.jones@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5816
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Marc Jones [Thu, 16 Sep 2010 21:04:54 +0000 (21:04 +0000)]
Add more Fam10 CPUID strings from the AMD revision guide. Includes
newer Phenom II.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5815
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Scott Duplichan [Tue, 14 Sep 2010 17:28:41 +0000 (17:28 +0000)]
This patch corrects a coding error in the original implementation
of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code
sets msr c001_102a bit 3 when bit 35 was intended.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814
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Marc Jones [Mon, 13 Sep 2010 19:31:21 +0000 (19:31 +0000)]
IEI Kino added to IEI mainboard Kconfig. I missed this in r5812
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5813
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Marc Jones [Mon, 13 Sep 2010 19:24:38 +0000 (19:24 +0000)]
IEI Kino mainboard support based on Mahogany Fam10.
svn copy amd/mahogany iei/kino-780am2-fam10; then apply the patch.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5812
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Myles Watson [Mon, 13 Sep 2010 17:46:13 +0000 (17:46 +0000)]
CONFIG_MMCONF_SUPPORT is always defined. Fix build.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5811
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Arne Georg Gleditsch [Mon, 13 Sep 2010 15:11:35 +0000 (15:11 +0000)]
Move initialization of MMCONF BAR to cache_as_ram setup phase, in order
to make sure MMCONF is set up before use. Otherwise, PCI config
accesses run before init_cpus() will be lost if MMCONF is enabled
(unless explicitly done as port-based accesses).
This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in
mcp55_early_setup, so reinsert.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810
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Juhana Helovuo [Mon, 13 Sep 2010 14:51:26 +0000 (14:51 +0000)]
Add support for Asus M4A785-M.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5809
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Mon, 13 Sep 2010 14:50:20 +0000 (14:50 +0000)]
Add reserved areas for fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5808
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Mon, 13 Sep 2010 14:49:02 +0000 (14:49 +0000)]
Port k8 UMA handling to fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5807
2b7e53f0-3cfb-0310-b3e9-
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Juhana Helovuo [Mon, 13 Sep 2010 14:47:22 +0000 (14:47 +0000)]
Generate multiboot tables from coreboot tables.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5806
2b7e53f0-3cfb-0310-b3e9-
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Juhana Helovuo [Mon, 13 Sep 2010 14:43:02 +0000 (14:43 +0000)]
Print an error and correct pci scan limits. Skip sb700 ISA DMA init if needed.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5805
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Mon, 13 Sep 2010 13:23:20 +0000 (13:23 +0000)]
Fix a typo reported by Sylvain Hitier.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5804
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Mon, 13 Sep 2010 13:14:48 +0000 (13:14 +0000)]
Convert i945 boards to use reserved resources instead of directly adding
coreboot table entries in every mainboard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Marc Jones [Fri, 10 Sep 2010 22:13:34 +0000 (22:13 +0000)]
Add F71859 SIO.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5802
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Fri, 10 Sep 2010 21:51:34 +0000 (21:51 +0000)]
Add support for LiPPERT Hurricane-LX (EPIC board with AMD Geode-LX,
CS5536, ITE IT8712F). Board support is based on the SpaceRunner-LX
(with tiny bits from the RoadRunner-LX) even though the hardware really
was the ancestor of our three other -LX boards and in fact among the
earliest Geode-LX boards on the market. (Might even have been the first
Geode-LX EPIC?)
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5801
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Fri, 10 Sep 2010 18:33:24 +0000 (18:33 +0000)]
Move memory type information out of some AMD sockets.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 9 Sep 2010 22:12:40 +0000 (22:12 +0000)]
Adapt comment, too. (trivial)
Noticed-by: Uwe Hermann
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5799
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Thu, 9 Sep 2010 20:37:00 +0000 (20:37 +0000)]
This patch avoids a timeout during PS/2 keyboard
initialization. It can reduce KBC init time by up to 400 ms on
real hardware, and by a minute or so on AMD simnow.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5798
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 9 Sep 2010 16:00:20 +0000 (16:00 +0000)]
Make huge macros inline functions for readability. Remove warnings. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5797
2b7e53f0-3cfb-0310-b3e9-
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Arne Georg Gleditsch [Thu, 9 Sep 2010 14:54:07 +0000 (14:54 +0000)]
Please find appended. This patch gets rid of the %gs magic altogether,
fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration). It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 9 Sep 2010 14:51:17 +0000 (14:51 +0000)]
Add support for reserved regions to resources and coreboot tables.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5795
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 9 Sep 2010 14:44:51 +0000 (14:44 +0000)]
Only try to beep when speaker support is compiled in.
Trivial change.
Reported-by: Aurelien Guillaume <aurelien@iwi.me>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5794
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 9 Sep 2010 14:42:58 +0000 (14:42 +0000)]
My Jmicron SATA card writes the name of the hard drive to the screen.
This redirects that output to the console and implements a basic
keyboard stub.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5793
2b7e53f0-3cfb-0310-b3e9-
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Arne Georg Gleditsch [Thu, 9 Sep 2010 10:35:52 +0000 (10:35 +0000)]
Also improve boot time on AMD for the DDR3 code path.
Fix a typo, too.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Arne Georg Gleditsch [Thu, 9 Sep 2010 09:56:19 +0000 (09:56 +0000)]
Apparently, it's not crucial to clear this at the exact moment we switch
to using ram, so something like the appended is perhaps more
appropriate. Confirmed to work on hw.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5791
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Thu, 9 Sep 2010 08:34:02 +0000 (08:34 +0000)]
Add a DRIVERS_PS2_KEYBOARD option which controls the PS2 keyboard
initialization. Not all payloads require it and some keyboards take a
long time to init.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5790
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Wed, 8 Sep 2010 21:30:07 +0000 (21:30 +0000)]
Trivial - remove stray characters from a comment block.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5789
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Wed, 8 Sep 2010 11:00:25 +0000 (11:00 +0000)]
Code must not access the smbus registers before the RTC power well is
ready (PSON gating). Some boards boot faster than this power well
stabilization, and thus see bad data when accessing the smbus
registers.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5788
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Wed, 8 Sep 2010 10:58:02 +0000 (10:58 +0000)]
Make timer2 the default choice for TSC initialization.
For boards where timer2 is unusable, there's still the IO based
initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kevin O'Connor [Wed, 8 Sep 2010 10:53:44 +0000 (10:53 +0000)]
It should not be necessary to read in the rom during CAR setup.
Removing the code preloading reduces the boot time.
Preload code is enabled when doing CARTEST (not exposed
to Kconfig given that it's a pure debugging measure)
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5786
2b7e53f0-3cfb-0310-b3e9-
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Liu Tao [Wed, 8 Sep 2010 10:27:13 +0000 (10:27 +0000)]
Changes to str*cmp functions. Fixes a couple more corner cases.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5785
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Tue, 7 Sep 2010 23:27:59 +0000 (23:27 +0000)]
My Jmicron SATA card depends on the BIOS not clearing AL when setting AH.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5784
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Tue, 7 Sep 2010 22:30:15 +0000 (22:30 +0000)]
Make a Kconfig option for debugging output from realmode emulation. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5783
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Tue, 7 Sep 2010 17:33:17 +0000 (17:33 +0000)]
Add support for LiPPERT Cool LiteRunner-LX (PC/104 board with AMD
Geode-LX, CS5536, ITE IT8712F), based on very similar SpaceRunner-LX.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5782
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Tue, 7 Sep 2010 09:18:08 +0000 (09:18 +0000)]
Remove unused ide0_enable and sata0_enable entries from SB7xx
and SB600.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5781
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Tue, 7 Sep 2010 07:53:26 +0000 (07:53 +0000)]
2ms is enough time to accurately obtain the clock rate.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5780
2b7e53f0-3cfb-0310-b3e9-
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Aurelien Guillaume [Tue, 7 Sep 2010 07:43:10 +0000 (07:43 +0000)]
Set up an arbitrary amount of system memory on Geode LX, so
coreboot_ram can be unpacked to 1MB. The value is quickly
replaced with the real value later, thus causing no harm.
Move RAMBASE to the default of 1MB for the affected boards
Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5779
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kevin O'Connor [Mon, 6 Sep 2010 20:20:47 +0000 (20:20 +0000)]
Instead of requiring users to modify qemu to allow writes to
0xc0000-0xfffff, have coreboot qemu support enable the memory range at
startup.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5778
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Sun, 5 Sep 2010 05:52:33 +0000 (05:52 +0000)]
Trivial. Currently the max frequency is preset as 400Mhz. We need to set a
platform specific value. Before that, we can set it manually if the boards
need to run in a higher frequency, which has been tested on Tilapia.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5777
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 4 Sep 2010 06:13:02 +0000 (06:13 +0000)]
AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Fri, 3 Sep 2010 15:16:36 +0000 (15:16 +0000)]
Update RoadRunner and SpaceRunner config to get in sync with current
standard BIOSes RRLX0013 and SRLX0013. Specifically move SPI and PME
I/Os to 0x1228 and 0x298 and switch SIO watchdog to ext. 48 MHz CLKIN.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5775
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Fri, 3 Sep 2010 14:54:50 +0000 (14:54 +0000)]
The AMD CS5536's USB controllers are located at device 0F, functions 4
and 5. They're not found if only function 0 is checked. So if a device
exists at all, try all its functions. usb_controller_initialize() will
silently skip all device classes != 0C03.
(changed to continue to use 32bit accesses -pg)
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5774
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 09:36:37 +0000 (09:36 +0000)]
Add support for dumping ACPI registers for i7
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5773
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 09:33:50 +0000 (09:33 +0000)]
Add support for dumping RCBA registers for i7
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5772
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 09:32:17 +0000 (09:32 +0000)]
Remove some errant spaces
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5771
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 09:31:13 +0000 (09:31 +0000)]
Add DMIBAR support for Intel X58 southbridge
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5770
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 08:57:32 +0000 (08:57 +0000)]
Add convenience rules for cscope to Makefile.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5769
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 3 Sep 2010 08:53:06 +0000 (08:53 +0000)]
The current workaround for binutils on mingw (or any non texinfo system) failed.
While we're at it, improve DESTDIR handling
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5768
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 2 Sep 2010 22:02:53 +0000 (22:02 +0000)]
Fix compilation for mtarvon. CAR initialization does early_mtrr_init,
jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5767
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 2 Sep 2010 20:30:31 +0000 (20:30 +0000)]
Trivial warning fix for adl855pc.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5766
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 2 Sep 2010 18:36:29 +0000 (18:36 +0000)]
Fix abuild to build all boards. Revision 5754 changed the way vendors and
boards were specified in Kconfig, and abuild depended on that. Since that rev
it has only built qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5765
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 2 Sep 2010 18:29:31 +0000 (18:29 +0000)]
Revert 5762. It silently broke a lot of boards because abuild was broken.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5764
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Wed, 1 Sep 2010 21:03:03 +0000 (21:03 +0000)]
Simplify last_dev_p so that it matches comments.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5763
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 1 Sep 2010 16:27:13 +0000 (16:27 +0000)]
Fix race condition in option_table.h generation by moving the include statement
to those files that actually need it. This significantly reduces the number of
dependencies, so it's no longer extremely ugly to specify them manually (see
the src/pc80/Makefile.inc portion)
Also, drop the AMD DBM690T work around for the issue.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5762
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Wed, 1 Sep 2010 03:40:57 +0000 (03:40 +0000)]
Add support for dumping GPIOS on Intel ICH10R. This information comes from the Intel ICH10 Family Datasheet.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5761
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Tue, 31 Aug 2010 19:19:16 +0000 (19:19 +0000)]
SMC_CONFIG is needed before the device tree is ready and some people
would rather not have mainboard settings like sio_gp1x_config in the
device tree anyway. So found a nice united home for both in Kconfig,
where users can change them without having to mess around in the C code.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5760
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Jens Rottmann [Tue, 31 Aug 2010 19:02:45 +0000 (19:02 +0000)]
Make ALIX.2D3 support 2D2 as well.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5759
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Zheng Bao [Tue, 31 Aug 2010 06:10:54 +0000 (06:10 +0000)]
Get Byte65/66 for register manufacture ID code. RegMan1Present will
be used in write levelization training.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5758
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Myles Watson [Mon, 30 Aug 2010 21:52:38 +0000 (21:52 +0000)]
Make yabel work for non-zero bus numbers. The link_num is not the bus number.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5757
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Stefan Reinauer [Mon, 30 Aug 2010 17:53:13 +0000 (17:53 +0000)]
We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756
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Stefan Reinauer [Mon, 30 Aug 2010 16:52:48 +0000 (16:52 +0000)]
Fix intel mtarvon compilation by switching it over to CAR.
This should be unproblematic, as there are other boards with the same "socket"
that work with CAR already. Tests are highly appreciated though!
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755
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Jens Rottmann [Mon, 30 Aug 2010 16:36:51 +0000 (16:36 +0000)]
Restructured all vendors' Kconfig files to no longer source the boards'
Kconfigs from within the choice/endchoice block. This makes it possible to
define user visible board specific options. Moved all vendor names and PCI
ids to the vendors' Kconfigs. Now all options in each file depend on the same
symbol, so replaced all "depends on"s with a single "if". Sorted boards
(sort -d), cleaned whitespace.
This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
always "y" and never used. It it simply needed to have something to attach
the boards' "select" statements to.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754
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Andreas Schultz [Mon, 30 Aug 2010 16:32:23 +0000 (16:32 +0000)]
This file was missing from r5751.
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5753
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Andreas Schultz [Mon, 30 Aug 2010 16:22:22 +0000 (16:22 +0000)]
Support for Lanner EM-8510 Board
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
---
src/mainboard/Kconfig | 8 ++
src/mainboard/lanner/Kconfig | 8 ++
src/mainboard/lanner/em8510/Kconfig | 38 +++++++++++
src/mainboard/lanner/em8510/Makefile.inc | 21 ++++++
src/mainboard/lanner/em8510/chip.h | 23 +++++++
src/mainboard/lanner/em8510/cmos.layout | 74 +++++++++++++++++++++
src/mainboard/lanner/em8510/devicetree.cb | 60 +++++++++++++++++
src/mainboard/lanner/em8510/irq_tables.c | 56 ++++++++++++++++
src/mainboard/lanner/em8510/mainboard.c | 27 ++++++++
src/mainboard/lanner/em8510/romstage.c | 103 +++++++++++++++++++++++++++++
10 files changed, 418 insertions(+), 0 deletions(-)
create mode 100644 src/mainboard/lanner/Kconfig
create mode 100644 src/mainboard/lanner/em8510/Kconfig
create mode 100644 src/mainboard/lanner/em8510/Makefile.inc
create mode 100644 src/mainboard/lanner/em8510/chip.h
create mode 100644 src/mainboard/lanner/em8510/cmos.layout
create mode 100644 src/mainboard/lanner/em8510/devicetree.cb
create mode 100644 src/mainboard/lanner/em8510/irq_tables.c
create mode 100644 src/mainboard/lanner/em8510/mainboard.c
create mode 100644 src/mainboard/lanner/em8510/romstage.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752
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Andreas Schultz [Mon, 30 Aug 2010 16:19:04 +0000 (16:19 +0000)]
Rework i855GM/i855GME support
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
---
src/northbridge/intel/i855/Kconfig | 30 +
src/northbridge/intel/i855/i855.h | 76 +++
src/northbridge/intel/i855/northbridge.c | 21 +
src/northbridge/intel/i855/raminit.c | 1036 +++++++++++++++++++++++++-----
src/northbridge/intel/i855/raminit.h | 14 +-
5 files changed, 1002 insertions(+), 175 deletions(-)
create mode 100644 src/northbridge/intel/i855/i855.h
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751
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