Make ASUS P3B-F RAM init actually work by enabling SPD access.

On this board all reads from SPD return 0xff by default, there's a custom
GPIO fiddling needed to enable access to the SPD SMBus offsets at
0x50-0x53. While coreboot actually sort of booted sometimes before r5193,
that was just sheer luck as the RAM init was hardcoded in certain ways.
Since the proper, more heavily SPD-based RAM init the brokenness of the
ASUS P3B-F RAM init was becoming visible.

This patch uses GPIOs to enable access to the SPD SMBus offsets,
and resets the GPIOs again after RAM init (this is needed to allow for
lm-sensors to work, for example).

Tested successfully on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index 0867886fa03d930eb2dc4a8f79c6778c8947ac3c..cde5400ff4d9c860b2d24780b2e5c79080720eef 100644 (file)
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -29,6 +29,7 @@
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "southbridge/intel/i82371eb/i82371eb_early_pm.c"
 #include "northbridge/intel/i440bx/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
@@ -49,6 +50,37 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "northbridge/intel/i440bx/raminit.c"
 #include "northbridge/intel/i440bx/debug.c"
 
+/*
+ * ASUS P3B-F specific SPD enable magic.
+ *
+ * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the
+ * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
+ * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
+ * will make RAM init fail.
+ *
+ * Tested values for PM I/O offset 0x37:
+ * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible
+ * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible
+ * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible
+ *
+ * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs
+ * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28
+ * control which SMBus/I2C offsets can be accessed.
+ */
+static void enable_spd(void)
+{
+       outb(0x6f, PM_IO_BASE + 0x37);
+}
+
+/*
+ * Disable SPD access after RAM init to allow access to SMBus/I2C offsets
+ * 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
+ */
+static void disable_spd(void)
+{
+       outb(0x67, PM_IO_BASE + 0x37);
+}
+
 static void main(unsigned long bist)
 {
        if (bist == 0)
@@ -64,10 +96,16 @@ static void main(unsigned long bist)
        i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
 
        enable_smbus();
+       enable_pm();
+
+       enable_spd();
+
        /* dump_spd_registers(); */
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
        /* ram_check(0, 640 * 1024); */
+
+       disable_spd();
 }
 

diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index cb4356ef8ae252de36affb2e4e314e94d36f6d6c..1093766dbef4764d54216138871801d605d29b7e 100644 (file)
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -72,5 +72,6 @@ void i82371eb_hard_reset(void);
 #define SSDE1                  (1 << 3)  /* Secondary Drive 1 UDMA/33 */
 #define ISA                    (1 << 0)  /* Select ISA */
 #define EIO                    (0 << 0)  /* Select EIO */
+#define PMIOSE                 (1 << 0)  /* PM I/O Space Enable */
 
 #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */

diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_pm.c b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
new file mode 100644 (file)
index 0000000..e6dd68e
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+#define PM_IO_BASE 0xe400
+
+static void enable_pm(void)
+{
+       device_t dev;
+       u8 reg8;
+       u16 reg16;
+
+       /* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */
+       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+                               PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
+
+       if (dev == PCI_DEV_INVALID)
+               die("SMBus/PM controller not found\n");
+
+       /* Set the PM I/O base. */
+       pci_write_config32(dev, PMBA, PM_IO_BASE | 1);
+
+       /* Enable access to the PM I/O space. */
+       reg16 = pci_read_config16(dev, PCI_COMMAND);
+       reg16 |= PCI_COMMAND_IO;
+       pci_write_config16(dev, PCI_COMMAND, reg16);
+
+       /* PM I/O Space Enable (PMIOSE). */
+       reg8 = pci_read_config8(dev, PMREGMISC);
+       reg8 |= PMIOSE;
+       pci_write_config8(dev, PMREGMISC, reg8);
+}
+

diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
index ada781ec261c82e239d042a01783cd26a1f8f6ee..76ae9f50b23b6ce9df912bf37f490e5b5bf48db8 100644 (file)
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
@@ -33,14 +33,12 @@ static void enable_smbus(void)
        u8 reg8;
        u16 reg16;
 
-       /* Check for SMBus device PCI ID on the 82371AB/EB/MB. */
+       /* Check for SMBus/PM device PCI ID on the 82371AB/EB/MB. */
        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
                                PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
 
        if (dev == PCI_DEV_INVALID)
-               die("SMBus controller not found\n");
-
-       print_spew("SMBus controller enabled\n");
+               die("SMBus/PM controller not found\n");
 
        /* Set the SMBus I/O base. */
        pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);