smmobj-y += vtxprintf.o
initobj-y += vtxprintf.o
-initobj-$(CONFIG_USE_DCACHE_RAM) += console.o
+initobj-$(CONFIG_CACHE_AS_RAM) += console.o
driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.o
driver-$(CONFIG_USBDEBUG) += usbdebug_console.o
source src/cpu/via/Kconfig
source src/cpu/x86/Kconfig
-config USE_DCACHE_RAM
+config CACHE_AS_RAM
bool
default !ROMCC
config CPU_AMD_MODEL_10XXX
bool
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select SSE
select SSE2
config CPU_AMD_MODEL_FXX
bool
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select MMX
select SSE
select SSE2
void SystemPreInit(void)
{
/* they want a jump ... */
-#ifndef CONFIG_USE_DCACHE_RAM
+#ifndef CONFIG_CACHE_AS_RAM
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif
StartTimer1();
{
/* they want a jump ... */
-#ifndef CONFIG_USE_DCACHE_RAM
+#ifndef CONFIG_CACHE_AS_RAM
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif
StartTimer1();
select CPU_INTEL_MODEL_68X
select MMX
select SSE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select TINY_BOOTBLOCK
config DCACHE_RAM_BASE
enable_cache();
}
-#if !defined(CONFIG_USE_DCACHE_RAM) || (CONFIG_USE_DCACHE_RAM == 0)
+#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0)
/* the fixed and variable MTTRs are power-up with random values,
* clear them to MTRR_TYPE_UNCACHEABLE for safty.
*/
#ifndef __ASSERT_H__
#define __ASSERT_H__
-#if defined(__PRE_RAM__) && !CONFIG_USE_DCACHE_RAM
+#if defined(__PRE_RAM__) && !CONFIG_CACHE_AS_RAM
/* ROMCC versions */
#define ASSERT(x) { \
static void report_bist_failure(u32 bist)
{
if (bist != 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_EMERG, "BIST failed: %08x", bist);
#else
print_emerg("BIST failed: ");
static inline void print_debug_sdram_8(const char *strval, uint32_t val)
{
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%s%02x\n", strval, val);
#else
print_debug(strval); print_debug_hex8(val); print_debug("\n");
/*
* Fill.
*/
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop);
#else
print_debug("DRAM fill: ");
for(addr = start; addr < stop ; addr += 4) {
/* Display address being filled */
if (!(addr & 0xfffff)) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx \r", addr);
#else
print_debug_hex32(addr);
write_phys(addr, (u32)addr);
};
/* Display final address */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr);
#else
print_debug_hex32(addr);
/*
* Verify.
*/
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop);
#else
print_debug("DRAM verify: ");
unsigned long value;
/* Display address being tested */
if (!(addr & 0xfffff)) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx \r", addr);
#else
print_debug_hex32(addr);
value = read_phys(addr);
if (value != addr) {
/* Display address with error */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value);
#else
print_err("Fail: @0x");
#endif
i++;
if(i>256) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "Aborting.\n");
#else
print_debug("Aborting.\n");
}
}
/* Display final address */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx", addr);
#else
print_debug_hex32(addr);
#endif
if (i) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
#else
print_debug("\nDRAM did _NOT_ verify!\n");
die("DRAM ERROR");
}
else {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\nDRAM range verified.\n");
#else
print_debug("\nDRAM range verified.\n");
* test than a "Is my DRAM faulty?" test. Not all bits
* are tested. -Tyson
*/
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop);
#else
print_debug("Testing DRAM : ");
/* Make sure we don't read before we wrote */
phys_memory_barrier();
ram_verify(start, stop);
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "Done.\n");
#else
print_debug("Done.\n");
#if !defined(__ROMCC__)
#include <console/console.h>
#else
-#if CONFIG_USE_DCACHE_RAM==0
+#if CONFIG_CACHE_AS_RAM==0
#define printk(BIOS_DEBUG, fmt, arg...) do {} while(0)
#endif
#endif
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
select HAVE_OPTION_TABLE
select HAVE_MAINBOARD_RESOURCES
select HAVE_BUS_CONFIG
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select BOARD_ROMSIZE_KB_1024
select HAVE_MAINBOARD_RESOURCES
select HAVE_BUS_CONFIG
select LIFT_BSP_APIC_ID
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select BOARD_ROMSIZE_KB_1024
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select WAIT_BEFORE_CPUS_INIT
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
#select AP_CODE_IN_CAR
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select SERIAL_CPU_INIT
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select HAVE_PIRQ_TABLE
select HAVE_OPTION_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select BOARD_ROMSIZE_KB_512
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
select LIFT_BSP_APIC_ID
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select BOARD_ROMSIZE_KB_1024
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_512
select SOUTHBRIDGE_VIA_VT8237R
select SOUTHBRIDGE_VIA_K8T890
select SUPERIO_WINBOND_W83627EHG
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
select HAVE_MP_TABLE
select SOUTHBRIDGE_VIA_VT8237R
select SOUTHBRIDGE_VIA_K8M890
select SUPERIO_ITE_IT8712F
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_512
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select HAVE_PIRQ_TABLE
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_1024
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select TINY_BOOTBLOCK
config MAINBOARD_DIR
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
select UDELAY_LAPIC
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_1024
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select GFXUMA
select TINY_BOOTBLOCK
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select K8_REV_F_SUPPORT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select HAVE_ACPI_TABLES
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select BOARD_ROMSIZE_KB_512
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_512
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select GFXUMA
select TINY_BOOTBLOCK
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select WAIT_BEFORE_CPUS_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select WAIT_BEFORE_CPUS_INIT
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
select HAVE_ACPI_TABLES
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_512
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select GFXUMA
select TINY_BOOTBLOCK
select NORTHBRIDGE_INTEL_I3100
select SOUTHBRIDGE_INTEL_I3100
select SUPERIO_INTEL_I3100
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select HAVE_PIRQ_TABLE
select HAVE_OPTION_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select WAIT_BEFORE_CPUS_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select WAIT_BEFORE_CPUS_INIT
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_1024
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select GFXUMA
select TINY_BOOTBLOCK
select HAVE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
select GFXUMA
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select HAVE_PIRQ_TABLE
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_512
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select TINY_BOOTBLOCK
config MAINBOARD_DIR
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5535
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select K8_REV_F_SUPPORT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select BOARD_ROMSIZE_KB_512
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select K8_REV_F_SUPPORT
select BOARD_ROMSIZE_KB_512
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_512
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_512
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select K8_REV_F_SUPPORT
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
select HAVE_MAINBOARD_RESOURCES
select HAVE_SMI_HANDLER
select GFXUMA
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select TINY_BOOTBLOCK
config MAINBOARD_DIR
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_1024
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
#select AP_CODE_IN_CAR
select LIFT_BSP_APIC_ID
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select BOARD_ROMSIZE_KB_1024
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select AMDMCT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select AMDMCT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select WAIT_BEFORE_CPUS_INIT
select HAVE_MAINBOARD_RESOURCES
select HAVE_SMI_HANDLER
select GFXUMA
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select TINY_BOOTBLOCK
config MAINBOARD_DIR
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_1024
config MAINBOARD_DIR
select HAVE_MP_TABLE
select UDELAY_TSC
select HAVE_OPTION_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select USE_WATCHDOG_ON_BOOT
select BOARD_ROMSIZE_KB_512
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select K8_REV_F_SUPPORT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select LIFT_BSP_APIC_ID
select BOARD_ROMSIZE_KB_1024
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_512
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_512
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select HAVE_HARD_RESET
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select TINY_BOOTBLOCK
config MAINBOARD_DIR
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select BOARD_ROMSIZE_KB_512
config MAINBOARD_DIR
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select UDELAY_TSC
- select USE_DCACHE_RAM
+ select CACHE_AS_RAM
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_256
for(i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x:",i);
#else
print_debug("\n");
#endif
}
val = pci_read_config8(dev, i);
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x", val);
#else
print_debug_char(' ');
device = ctrl->channel0[i];
if (device) {
int j;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
#else
print_debug("dimm: ");
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ", j);
#else
print_debug("\n");
break;
}
byte = status & 0xff;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
device = ctrl->channel1[i];
if (device) {
int j;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
#else
print_debug("dimm: ");
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ", j);
#else
print_debug("\n");
break;
}
byte = status & 0xff;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "smbus: %02x", device);
#else
print_debug("smbus: ");
break;
}
if ((j & 0xf) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ",j);
#else
print_debug("\n");
#endif
}
byte = status & 0xff;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
{
int i;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%04x:\n", port);
#else
print_debug_hex16(port);
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x:", i);
#else
print_debug_hex8(i);
#endif
}
val = inb(port);
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x",val);
#else
print_debug_char(' ');
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%08x:", i);
#else
print_debug("\n");
print_debug(":");
#endif
}
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
-#if CONFIG_USE_DCACHE_RAM == 0
+#if CONFIG_CACHE_AS_RAM == 0
cache_lbmem(MTRR_TYPE_WRBACK);
#endif
}
obj-$(CONFIG_UDELAY_IO) += udelay_io.o
obj-y += keyboard.o
initobj-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.o
-initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o
+initobj-$(CONFIG_CACHE_AS_RAM) += serial.o
subdirs-y += vga
$(obj)/pc80/mc146818rtc.o : $(OPTION_TABLE_H)
#define UART_LCS CONFIG_TTYS0_LCS
-#if CONFIG_USE_DCACHE_RAM == 0
+#if CONFIG_CACHE_AS_RAM == 0
/* Data */
#define UART_RBR 0x00
}
#else
-/* CONFIG_USE_DCACHE_RAM == 1 */
+/* CONFIG_CACHE_AS_RAM == 1 */
extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
void uart_init(void)
projects / coreboot.git / commitdiff