Drop per-board ram_check() calls for now.

Every board had a slightly different invokation, very often commented out
anyway. We could either decide that this is only to be used by developers
during bringup (and thus added manually to romstage.c and removed before
the board gets committed). This method seems to be preferred from what I
have heard on IRC / mailing list in the past.

Or, we add the ram_check() somewhere globally and allow the user to enable
it via menuconfig (possibly only if EXPERT is selected).

Either way, the current method of spreading the calls all over the place is
not really the way to go.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c
index 5a0d1a889f5fb1536d263ccc06d62eaa318a5bca..3c77b11e2a621210453ab8728a6c2c26a066bf49 100644 (file)
--- a/src/mainboard/advantech/pcm-5820/romstage.c
+++ b/src/mainboard/advantech/pcm-5820/romstage.c
@@ -24,7 +24,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
@@ -40,5 +39,4 @@ static void main(unsigned long bist)
        report_bist_failure(bist);
        cs5530_enable_rom();
        sdram_init();
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c
index a51b64e937de49d614093ddd60e1340a522d21c6..8b7027189bda01cc1685930dab1e07ec1811b2af 100644 (file)
--- a/src/mainboard/amd/db800/romstage.c
+++ b/src/mainboard/amd/db800/romstage.c
@@ -83,9 +83,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0x00000000, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index ce4cd1b920f24d0bf46bc85db68dfea912d05197..9079044919adca98c281619ab9933d6a3657db68 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -217,9 +217,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();

diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c
index 8d108b3d89dc312d9e6b815523272ba4f7609cd5..f60313842aa03e1d3fa0d740b86c0de8cf4b0f4e 100644 (file)
--- a/src/mainboard/amd/norwich/romstage.c
+++ b/src/mainboard/amd/norwich/romstage.c
@@ -84,9 +84,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0x00000000, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index 86491c0e1b264a5162702bb01ea035722c0a91ad..ade6f62d0fa34d7f8ab7252c63b10346b6a33f59 100644 (file)
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -56,7 +56,4 @@ void main(unsigned long bist)
        sdram_initialize(1, memctrl);
 
        msr_init();
-
-       /* Check all of memory */
-       //ram_check(0x00000000, 640*1024);
 }

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index f7f194a7bef25010002b0b46e362763e60cb5994..5274ef2e4aaa1aeecf25f3cbbfbc7272354dabcc 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -328,9 +328,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
 //     die("After MCT init before CAR disabled.");
 
        post_code(0x42);

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index e58fa1203692187ca3b83a4f998c3f000888b630..5c7858c19bba2e6601523353d28de14456651221 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -217,10 +217,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();

diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index a8dc6cde59337daf140f0cf9115bb7aa8d5bb9f6..7b213bf1c748bf7dc075bcd849e13ec20c9ae3d5 100644 (file)
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -133,8 +133,4 @@ void main(unsigned long bist)
        msr = rdmsr(MC_CF8F_DATA);
        print_debug(" \n");
 #endif
-
-       /* Check memory. */
-       // ram_check(0x00000000, 640 * 1024);
-       // ram_check(1024 * 1024, 2 * 1024 * 1024);
 }

diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c
index 3b7b199f49bd5364a3f1d230da8d292aa89f000a..3d3367aa858afff83e63a0c0fba1462da23a5f0d 100644 (file)
--- a/src/mainboard/asi/mb_5blgp/romstage.c
+++ b/src/mainboard/asi/mb_5blgp/romstage.c
@@ -24,7 +24,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
@@ -40,5 +39,4 @@ static void main(unsigned long bist)
        report_bist_failure(bist);
        cs5530_enable_rom();
        sdram_init();
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c
index 118ded48a33c73ed9d9ce2bfda8b171b921422de..f79c2437b93f92338635bd5607565d76a53fc1ac 100644 (file)
--- a/src/mainboard/asi/mb_5blmp/romstage.c
+++ b/src/mainboard/asi/mb_5blmp/romstage.c
@@ -25,7 +25,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"
 #include "cpu/x86/bist.h"
@@ -41,5 +40,4 @@ static void main(unsigned long bist)
        report_bist_failure(bist);
        cs5530_enable_rom();
        sdram_init();
-       /* ram_check(0x00000000, 0x4000); */
 }

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index ea93eee4121921b17628077664eff9f1fd675be4..540ada64321fda57f55377a02535351f52397757 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -218,10 +218,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();

diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c
index 8074c874e14f732ee55864469a001635cc0a34b6..f5eeab3c296b560de904d9cf9b7158fb63a92234 100644 (file)
--- a/src/mainboard/axus/tc320/romstage.c
+++ b/src/mainboard/axus/tc320/romstage.c
@@ -25,7 +25,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
@@ -41,5 +40,4 @@ static void main(unsigned long bist)
        report_bist_failure(bist);
        cs5530_enable_rom();
        sdram_init();
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c
index 8074c874e14f732ee55864469a001635cc0a34b6..f5eeab3c296b560de904d9cf9b7158fb63a92234 100644 (file)
--- a/src/mainboard/bcom/winnet100/romstage.c
+++ b/src/mainboard/bcom/winnet100/romstage.c
@@ -25,7 +25,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
@@ -41,5 +40,4 @@ static void main(unsigned long bist)
        report_bist_failure(bist);
        cs5530_enable_rom();
        sdram_init();
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 802645365ab5d6745104f3037d4e0f71ea0d295e..7d9a5a7d572262527729f17ae4134e136a14612a 100644 (file)
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -99,6 +99,4 @@ void main(unsigned long bist)
        enable_mainboard_devices();
 
        ddr_ram_setup(&ctrl);
-
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c
index 04a7cf3f46657409a14849a0bb5e9348b1760c33..3927cd2f338c2c37192abf9085f6ef5b7b5fdbbe 100644 (file)
--- a/src/mainboard/dell/s1850/romstage.c
+++ b/src/mainboard/dell/s1850/romstage.c
@@ -6,7 +6,6 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc8374/pc8374_early_init.c"
@@ -323,17 +322,4 @@ static void main(unsigned long bist)
        dump_pci_device(PCI_DEV(0, 0x00, 0));
 //     dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#if 1 // temporarily disabled
-       /* Check the first 1M */
-//     ram_check(0x00000000, 0x000100000);
-//     ram_check(0x00000000, 0x000a0000);
-//     ram_check(0x00100000, 0x01000000);
-       ram_check(0x00100000, 0x00100100);
-       /* check the first 1M in the 3rd Gig */
-//     ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
-       ram_check(0x00000000, 0x02000000);
-#endif
 }

diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index a75d60f07a2d74c591d1daf2c57126baf40fa543..823e5effa4b3a6e50b16fcc63031478747eed30b 100644 (file)
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -62,12 +62,5 @@ void main(unsigned long bist)
 #if 0
        dump_pci_devices();
        dump_pci_device(PCI_DEV(0, 0, 0));
-
-       // Check all of memory
-       ram_check(0x00000000, msr.lo+(msr.hi<<32));
-       // Check 16MB of memory @ 0
-       ram_check(0x00000000, 0x01000000);
-       // Check 16MB of memory @ 2GB
-       ram_check(0x80000000, 0x81000000);
 #endif
 }

diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c
index 4e6462d1e4b0efca2d7052082f314cdb252ed2d8..a4994f1f4b3f184544a4de4a7017043df3875a2b 100644 (file)
--- a/src/mainboard/digitallogic/msm586seg/romstage.c
+++ b/src/mainboard/digitallogic/msm586seg/romstage.c
@@ -6,7 +6,6 @@
 #include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 
 void setup_pars(void)
@@ -203,16 +202,6 @@ static void main(unsigned long bist)
        dump_pci_device(PCI_DEV(0, 0, 0));
 #endif
 
-#if 0
-       print_err("RAM CHECK!\n");
-       // Check 16MB of memory @ 0
-       ram_check(0x00000000, 0x01000000);
-#endif
-#if 0
-       print_err("RAM CHECK for 32 MB!\n");
-       // Check 32MB of memory @ 0
-       ram_check(0x00000000, 0x02000000);
-#endif
 #if 1
        {
          volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000;

diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 14f04941f79104300f6bbeae1495ef3f99268862..4429914d7461e5d6401c533498e2ceb8734fd7f6 100644 (file)
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -66,9 +66,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check all of memory */
-       ram_check(0x00000000, 640*1024);
-
        /* Switch from Cache as RAM to real RAM */
        /* There are two ways we could think about this.
         1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.

diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c
index 3d99873bc9f9aa997b8028ffb3833ad75dba34c9..16ea548ff5f33e88df5d7eca2c9395c7819b38f9 100644 (file)
--- a/src/mainboard/eaglelion/5bcm/romstage.c
+++ b/src/mainboard/eaglelion/5bcm/romstage.c
@@ -6,7 +6,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 7b7f239d0e003e977f01cf8221d3024d5f403b11..1f6ebdd1aad82f9f14dd847181f3073eac38dcd6 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -214,10 +214,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 9a753b9201314e0072381d7d943504c8534ad9cf..21f80c25672a859a841a873777d205fc4b82e366 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -216,9 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();

diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c
index 6bde6756c4db541557d8597d3364ec4169043221..a5019ce0954e67f47054b3e2f29e65dc68f4f2e1 100644 (file)
--- a/src/mainboard/iei/juki-511p/romstage.c
+++ b/src/mainboard/iei/juki-511p/romstage.c
@@ -25,7 +25,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
 #include "cpu/x86/bist.h"
@@ -47,5 +46,4 @@ static void main(unsigned long bist)
 
        cs5530_enable_rom();
        sdram_init();
-       /* ram_check(0x00000000, 640 * 1024); */
 }

diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 5afa651e058fe168c3f43c8f2bc66186312f1922..8ef205aab787c14127745f205eb6463cc1219f66 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -219,9 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();

diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c
index 0900f4ba3eef1e61ce7df632a593ae5e76fdfc55..1d991972937df06313c0ff339f7aa3f73aedc5ed 100644 (file)
--- a/src/mainboard/iei/nova4899r/romstage.c
+++ b/src/mainboard/iei/nova4899r/romstage.c
@@ -25,7 +25,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
 #include "cpu/x86/bist.h"
@@ -42,5 +41,4 @@ static void main(unsigned long bist)
        report_bist_failure(bist);
        cs5530_enable_rom();
        sdram_init();
-       /* ram_check(0x00000000, 640 * 1024); */
 }

diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index 4e27f9bbbd00e21589d6133f2c45e86ec9bbd730..0c06fd2432ecf553bcbd9e95f0ab1cd0811bfab9 100644 (file)
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -87,8 +87,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* ram_check(0, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 5d33b10633841b5b8aa0c7831a1310b04fda2775..e3ab67940ef8fa3e8fd8d769e99825979cea127d 100644 (file)
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -6,7 +6,6 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
@@ -105,17 +104,4 @@ static void main(unsigned long bist)
        dump_pci_device(PCI_DEV(0, 0x00, 0));
        dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#if 0 // temporarily disabled
-       /* Check the first 1M */
-//     ram_check(0x00000000, 0x000100000);
-//     ram_check(0x00000000, 0x000a0000);
-       ram_check(0x00100000, 0x01000000);
-       /* check the first 1M in the 3rd Gig */
-       ram_check(0x30100000, 0x31000000);
-#if 0
-       ram_check(0x00000000, 0x02000000);
-#endif
-
-#endif
 }

diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 525f02e7a0610728234d21d7d31dbd08153619c0..856c69950d7478eb20391775d6dd7f91bd6d5872 100644 (file)
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -118,6 +118,4 @@ void main(unsigned long bist)
        /* dump_pci_devices(); */
        /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */
        /* dump_bar14(PCI_DEV(0, 0x00, 0)); */
-
-       ram_check(0, 1024 * 1024);
 }

diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index c75ce3e732af7c6f423621d63ca6ddb80230461f..d6ee7c582fa72a1437f2b156cafa688df43ff62e 100644 (file)
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -28,7 +28,6 @@
 #include <pc80/mc146818rtc.h>
 #include "pc80/udelay_io.c"
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"
 #include "northbridge/intel/i3100/raminit_ep80579.h"
@@ -98,9 +97,4 @@ static void main(unsigned long bist)
 #ifdef TRUXTON_DEBUG
        dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#ifdef TRUXTON_DEBUG
-       ram_fill(0x00000000, 0x02000000);
-       ram_verify(0x00000000, 0x02000000);
-#endif
 }

diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index f393c301a36a3937f5984145c2bf98540a528615..e6fb83f4a69ffae4fad2b248538d769353d22e5d 100644 (file)
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -8,7 +8,6 @@
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
 #include "cpu/x86/lapic/boot_cpu.c"

diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index daacd1bebd62fbe8474264df647d947443ee062e..b0c14968b962571c9c1b0daa685f8c9a4c7090ec 100644 (file)
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -104,6 +104,4 @@ void main(unsigned long bist)
        enable_mainboard_devices();
 
        ddr_ram_setup(&ctrl);
-
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 990c87898761fe6a48ceee284ed7639bb4c2d89b..a1688dfcb781a3b9f1f89011d646a9f40ce9f968 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -224,9 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 */
 
-//     ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//     ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
 //     die("After MCT init before CAR disabled.");
 
        rs780_before_pci_init();

diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index 24008bcfe632059fd8ee27891949fed2eec98153..5406b7d05f9a39eb79a4ffc5ba727aac4b6daad5 100644 (file)
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -80,16 +80,4 @@ void main(unsigned long bist)
                sdram_set_spd_registers();
                sdram_enable();
        }
-
-#if 0
-       dump_pci_devices();
-       dump_pci_device(PCI_DEV(0, 0, 0));
-
-       // Check all of memory
-       ram_check(0x00000000, msr.lo+(msr.hi<<32));
-       // Check 16MB of memory @ 0
-       ram_check(0x00000000, 0x01000000);
-       // Check 16MB of memory @ 2GB
-       ram_check(0x80000000, 0x81000000);
-#endif
 }

diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index 1d63e492434b664a8f16e67d66824b969847a632..0abdde4372b96673a2a8b3ebf6790d897e2350b3 100644 (file)
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -127,8 +127,4 @@ void main(unsigned long bist)
        outb( temp, 0x4F);
        temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
        print_debug_hex8(temp);print_debug("\n");
-       /* Check all of memory */
-//     ram_check(0, 16384);
-       ram_check(0x20000, 0x24000);
-//     ram_check(0x00000000, 640*1024);
 }

diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 42f93410ad05c90cd384b35374a72d0f5b6efdde..35f8fe5c319ddf05353f20b24364b5855567f178 100644 (file)
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -157,9 +157,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 714411c57df4cd047afcbb3b3cb2cd0953d028a8..afe5bd7c091e200a3a4b43947afb9e688a6ce11c 100644 (file)
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -197,9 +197,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c
index 0100caedc372bbca9f55af42821fd02dd0042999..32f3b3e3041461916078ad4fd49d260709ee97e9 100644 (file)
--- a/src/mainboard/lippert/roadrunner-lx/romstage.c
+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c
@@ -122,9 +122,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0x00000000, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index ffd9e4ed06b757bb5b6acb01c99e86ed6b9a99f3..5f940e56617083a563d87a5670863483ec32c69a 100644 (file)
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -194,9 +194,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 209485ec64085e4f719c219276133594420c6e40..ed9324ea447b8b0532af0a03a5fcee430447df2b 100644 (file)
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -142,10 +142,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory */
-       /* Enable this only if you are having questions. */
-       /* ram_check(0, 640 * 1024); */
-
        /* Switch from Cache as RAM to real RAM.
         *
         * There are two ways we could think about this.

diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 9fd001ca17320442d47ffa40ff53b70c090161a2..ec775371133ca04fc1a5fad4704491318b56b554 100644 (file)
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -166,10 +166,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory */
-       /* Enable this only if you are having questions. */
-       /* ram_check(0, 640 * 1024); */
-
        /* Switch from Cache as RAM to real RAM.
         *
         * There are two ways we could think about this.

diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index 65d6bdea69d9343452dd23ae2985a69de3e76467..1fb1440a1b10bf817245e319ee6c00d2a8f32317 100644 (file)
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -121,8 +121,4 @@ void main(unsigned long bist)
 
        /* Initialize memory */
        sdram_initialize();
-
-       /* Check RAM. */
-       /* ram_check(0, 640 * 1024); */
-       /* ram_check(64512 * 1024, 65536 * 1024); */
 }

diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index 2873d8af994dcbda705de3c1d83ce5b9b5d8a77f..9ae30b0e0a72ce7e2c67fe4629c7075dbd21c58b 100644 (file)
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -6,7 +6,6 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
@@ -99,16 +98,4 @@ static void main(unsigned long bist)
        dump_pci_device(PCI_DEV(0, 0x00, 0));
 //     dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#if 0 // temporarily disabled
-       /* Check the first 1M */
-//     ram_check(0x00000000, 0x000100000);
-//     ram_check(0x00000000, 0x000a0000);
-       ram_check(0x00100000, 0x01000000);
-       /* check the first 1M in the 3rd Gig */
-       ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
-       ram_check(0x00000000, 0x02000000);
-#endif
 }

diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index c5107d9fc1961554bacb202e7c3180307c224ee8..1865a08dac05f91532c3f8772d25646844de39a8 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -6,7 +6,6 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "southbridge/intel/esb6300/esb6300_early_smbus.c"
@@ -103,16 +102,4 @@ static void main(unsigned long bist)
        dump_pci_device(PCI_DEV(0, 0x00, 0));
        dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#if 0 // temporarily disabled
-       /* Check the first 1M */
-//     ram_check(0x00000000, 0x000100000);
-//     ram_check(0x00000000, 0x000a0000);
-       ram_check(0x00100000, 0x01000000);
-       /* check the first 1M in the 3rd Gig */
-       ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
-       ram_check(0x00000000, 0x02000000);
-#endif
 }

diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c
index af042477d2c6a87ba2f3c76710900e4f9dcde2f0..fb71fa5f2c571847f439897c74065da290b291e6 100644 (file)
--- a/src/mainboard/supermicro/x6dhe_g2/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c
@@ -6,7 +6,6 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/nsc/pc87427/pc87427.h"
@@ -103,16 +102,4 @@ static void main(unsigned long bist)
        dump_pci_device(PCI_DEV(0, 0x00, 0));
        //dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#if 0 // temporarily disabled
-       /* Check the first 1M */
-//     ram_check(0x00000000, 0x000100000);
-//     ram_check(0x00000000, 0x000a0000);
-       ram_check(0x00100000, 0x01000000);
-       /* check the first 1M in the 3rd Gig */
-       ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
-       ram_check(0x00000000, 0x02000000);
-#endif
 }

diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 839be041842c49c21d2784bde242627b5d21be01..794234ea718c60b58ac8e316fd8dc741655ae46f 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -6,7 +6,6 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
@@ -48,12 +47,6 @@ static void main(unsigned long bist)
        static const struct mem_controller mch[] = {
                {
                        .node_id = 0,
-                       /*
-                       .f0 = PCI_DEV(0, 0x00, 0),
-                       .f1 = PCI_DEV(0, 0x00, 1),
-                       .f2 = PCI_DEV(0, 0x00, 2),
-                       .f3 = PCI_DEV(0, 0x00, 3),
-                       */
                        .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
                        .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
                }
@@ -110,17 +103,4 @@ static void main(unsigned long bist)
        dump_pci_device(PCI_DEV(0, 0x00, 0));
        dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#if 0 // temporarily disabled
-       /* Check the first 1M */
-//     ram_check(0x00000000, 0x000100000);
-//     ram_check(0x00000000, 0x000a0000);
-//     ram_check(0x00100000, 0x01000000);
-       ram_check(0x00100000, 0x00100100);
-       /* check the first 1M in the 3rd Gig */
-//     ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
-       ram_check(0x00000000, 0x02000000);
-#endif
 }

diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index 76c94b228f531aad3731d73b922337b8fc20df34..5e54fa66fa179d7794afd89d7e9a8f05ae65f984 100644 (file)
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -6,7 +6,6 @@
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"
 #include "superio/winbond/w83627hf/w83627hf.h"
@@ -102,17 +101,4 @@ static void main(unsigned long bist)
        dump_pci_device(PCI_DEV(0, 0x00, 0));
        dump_bar14(PCI_DEV(0, 0x00, 0));
 #endif
-
-#if 0 // temporarily disabled
-       /* Check the first 1M */
-//     ram_check(0x00000000, 0x000100000);
-//     ram_check(0x00000000, 0x000a0000);
-//     ram_check(0x00100000, 0x01000000);
-       ram_check(0x00100000, 0x00100100);
-       /* check the first 1M in the 3rd Gig */
-//     ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
-       ram_check(0x00000000, 0x02000000);
-#endif
 }

diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c
index 66bfdfc53c2a8ecac681830f43efda9a0a1f2590..ff296ec23ecca25f94b6b58487ed862c09a07aec 100644 (file)
--- a/src/mainboard/technologic/ts5300/romstage.c
+++ b/src/mainboard/technologic/ts5300/romstage.c
@@ -12,7 +12,6 @@
 #include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 
 #define TS5300_LED_OFF outb((inb(0x77)&0xfe), 0x77)
@@ -162,12 +161,5 @@ static void main(unsigned long bist)
        identify_system();
 #endif
 
-#if 0
-       // Check 32MB of memory @ 0 (very slow!)
-       print_err("Checking memory:\n");
-       ram_check(0x00000000, 0x000a0000);
-       ram_check(0x000b0000, 0x02000000);
-#endif
-
        TS5300_LED_OFF;
 }

diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c
index 8074c874e14f732ee55864469a001635cc0a34b6..f5eeab3c296b560de904d9cf9b7158fb63a92234 100644 (file)
--- a/src/mainboard/televideo/tc7020/romstage.c
+++ b/src/mainboard/televideo/tc7020/romstage.c
@@ -25,7 +25,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"
 #include "cpu/x86/bist.h"
@@ -41,5 +40,4 @@ static void main(unsigned long bist)
        report_bist_failure(bist);
        cs5530_enable_rom();
        sdram_init();
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
index e399dd128f9621f25fe324ccacab2ffd539caddd..c9ec8a80b2630d01c45d18c832f3455eda9ba8f8 100644 (file)
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ b/src/mainboard/thomson/ip1000/romstage.c
@@ -124,7 +124,4 @@ void main(unsigned long bist)
 #if CONFIG_LLSHELL
        llshell();
 #endif
-       /* Check RAM. */
-       /* ram_check(0, 640 * 1024); */
-       /* ram_check(64512 * 1024, 65536 * 1024); */
 }

diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
index f6a4ccfece5fe14ef60d152ffc9f89b8873141f3..3e4ffb5c4c1f7e28bc1503ce4059c1951f52b717 100644 (file)
--- a/src/mainboard/traverse/geos/romstage.c
+++ b/src/mainboard/traverse/geos/romstage.c
@@ -85,9 +85,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0x00000000, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 1d37ced6d98ab560486e42f5a75f59aaa1efd216..20b4c0567546752114fbbdd81808cf59036aa8d5 100644 (file)
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -93,5 +93,4 @@ void main(unsigned long bist)
        report_bist_failure(bist);
        enable_mainboard_devices();
        ddr_ram_setup(&ctrl);
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c
index 508d298604b23b80fdac427b9c3870d5882c80f1..2d887b3f921890a0bbe5a6c537c0756e47865489 100644 (file)
--- a/src/mainboard/via/epia-m/romstage.c
+++ b/src/mainboard/via/epia-m/romstage.c
@@ -7,7 +7,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/via/vt8623/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
@@ -105,20 +104,6 @@ static void main(unsigned long bist)
 
        ddr_ram_setup((const struct mem_controller *)0);
 
-       /* Check all of memory */
-#if 0
-       static const struct {
-               unsigned long lo, hi;
-       } check_addrs[] = {
-               /* Check 16MB of memory @ 0*/
-               { 0x00000000, 0x01000000 },
-       };
-       int i;
-       for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
-               ram_check(check_addrs[i].lo, check_addrs[i].hi);
-       }
-#endif
-
        if (bist == 0)
                early_mtrr_init();
 

diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c
index 90d92383ad6fde4349b4e036c8bcb291d2218e2a..30ea0f2a3a253d6f0376adb221ed040ced571955 100644 (file)
--- a/src/mainboard/via/epia-n/romstage.c
+++ b/src/mainboard/via/epia-n/romstage.c
@@ -27,7 +27,6 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/via/cn400/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
@@ -134,6 +133,4 @@ static void main(unsigned long bist)
 
        if (bist == 0)
                early_mtrr_init();
-
-       //ram_check(0, 640 * 1024);
 }

diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c
index 2bae6c4c81fe707a220063fc90c188bf6e9505fe..870c4e763033e118c837a71e91ae359e21e52371 100644 (file)
--- a/src/mainboard/via/epia/romstage.c
+++ b/src/mainboard/via/epia/romstage.c
@@ -6,7 +6,6 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "northbridge/via/vt8601/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
@@ -95,25 +94,4 @@ static void main(unsigned long bist)
        sdram_set_registers((const struct mem_controller *) 0);
        sdram_set_spd_registers((const struct mem_controller *) 0);
        sdram_enable(0, (const struct mem_controller *) 0);
-
-       /* Check all of memory */
-#if 0
-       ram_check(0x00000000, msr.lo);
-#endif
-#if 0
-       static const struct {
-               unsigned long lo, hi;
-       } check_addrs[] = {
-               /* Check 16MB of memory @ 0*/
-               { 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
-               /* Check 16MB of memory @ 2GB */
-               { 0x80000000, 0x81000000 },
-#endif
-       };
-       int i;
-       for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
-               ram_check(check_addrs[i].lo, check_addrs[i].hi);
-       }
-#endif
 }

diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index 657b3cde6b4a9721f2680eced7e15ec51584080e..2b653f79d2a7ae45b3c84c633de4638d823ee35f 100644 (file)
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -67,5 +67,4 @@ void main(unsigned long bist)
        smbus_fixup(&ctrl);
        report_bist_failure(bist);
        ddr_ram_setup(&ctrl);
-       /* ram_check(0, 640 * 1024); */
 }

diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index becd698c0a83ef6adf74941568ceac8beba57823..cd615efa4b8a2dd47a5888ebbb1139f6cd5f9e7d 100644 (file)
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -86,9 +86,6 @@ void main(unsigned long bist)
 
        sdram_initialize(1, memctrl);
 
-       /* Check memory. */
-       /* ram_check(0x00000000, 640 * 1024); */
-
        /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
        return;
 }

diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index b1ece302febe3c99954bb399edece3b039d120d2..f8761243362a00fbe36943afa8c67c1827d1b5ee 100644 (file)
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -78,7 +78,4 @@ void main(unsigned long bist)
        print_err("ram setup done\n");
 
        msr_init();
-
-       /* Check all of memory */
-       /*ram_check(0x00000000, 640*1024);*/
 }