src/mainboard/intel/jarrell/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/nsc/pc87427/pc87427.h"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "watchdog.c"
  16 #include "reset.c"
  17 #include "power_reset_check.c"
  18 #include "jarrell_fixups.c"
  19 #include "superio/nsc/pc87427/pc87427_early_init.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22 #include <spd.h>
  23
  24 #define SIO_GPIO_BASE 0x680
  25 #define SIO_XBUS_BASE 0x4880
  26
  27 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
  28 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP1)
  29
  30 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
  31 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  32
  33 static inline int spd_read_byte(unsigned device, unsigned address)
  34 {
  35         return smbus_read_byte(device, address);
  36 }
  37
  38 #include "northbridge/intel/e7520/raminit.c"
  39 #include "lib/generic_sdram.c"
  40 #include "debug.c"
  41 #include "arch/i386/lib/stages.c"
  42
  43 static void main(unsigned long bist)
  44 {
  45         static const struct mem_controller mch[] = {
  46                 {
  47                         .node_id = 0,
  48                         .channel0 = { DIMM2, DIMM1, DIMM0, 0 },
  49                         .channel1 = { DIMM6, DIMM5, DIMM4, 0 },
  50                 }
  51         };
  52
  53         if (bist == 0) {
  54                 /* Skip this if there was a built in self test failure */
  55                 early_mtrr_init();
  56                 if (memory_initialized())
  57                         skip_romstage();
  58         }
  59
  60         /* Setup the console */
  61         pc87427_disable_dev(CONSOLE_SERIAL_DEV);
  62         pc87427_disable_dev(HIDDEN_SERIAL_DEV);
  63         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  64         /* Enable Serial 2 lines instead of GPIO */
  65         outb(0x2c, 0x2e);
  66         outb((inb(0x2f) & (~1<<1)), 0x2f);
  67         uart_init();
  68         console_init();
  69
  70         /* Halt if there was a built in self test failure */
  71         report_bist_failure(bist);
  72
  73         pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
  74
  75         pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
  76         xbus_cfg(PC87427_XBUS_DEV);
  77
  78         /* MOVE ME TO A BETTER LOCATION !!! */
  79         /* config LPC decode for flash memory access */
  80         device_t dev;
  81         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
  82         if (dev == PCI_DEV_INVALID)
  83                 die("Missing ich5?");
  84         pci_write_config32(dev, 0xe8, 0x00000000);
  85         pci_write_config8(dev, 0xf0, 0x00);
  86
  87 #if 0
  88         print_pci_devices();
  89 #endif
  90         enable_smbus();
  91 #if 0
  92 //      dump_spd_registers(&cpu[0]);
  93         int i;
  94         for(i = 0; i < 1; i++)
  95                 dump_spd_registers();
  96 #endif
  97         disable_watchdogs();
  98         power_down_reset_check();
  99 //      dump_ipmi_registers();
 100         mainboard_set_e7520_leds();
 101         sdram_initialize(ARRAY_SIZE(mch), mch);
 102         ich5_watchdog_on();
 103 #if 0
 104         dump_pci_devices();
 105         dump_pci_device(PCI_DEV(0, 0x00, 0));
 106         dump_bar14(PCI_DEV(0, 0x00, 0));
 107 #endif
 108
 109 #if 0 // temporarily disabled
 110         /* Check the first 1M */
 111 //      ram_check(0x00000000, 0x000100000);
 112 //      ram_check(0x00000000, 0x000a0000);
 113         ram_check(0x00100000, 0x01000000);
 114         /* check the first 1M in the 3rd Gig */
 115         ram_check(0x30100000, 0x31000000);
 116 #if 0
 117         ram_check(0x00000000, 0x02000000);
 118 #endif
 119
 120 #endif
 121 }