2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <device/pci_def.h>
23 #include <device/pci_ids.h>
25 #include <device/pnp_def.h>
26 #include <arch/romcc_io.h>
27 #include <cpu/x86/lapic.h>
28 #include <pc80/mc146818rtc.h>
29 #include "pc80/udelay_io.c"
30 #include <console/console.h>
31 #include "southbridge/intel/i3100/i3100_early_smbus.c"
32 #include "southbridge/intel/i3100/i3100_early_lpc.c"
33 #include "northbridge/intel/i3100/raminit_ep80579.h"
34 #include "superio/intel/i3100/i3100.h"
35 #include "cpu/x86/lapic/boot_cpu.c"
36 #include "cpu/x86/mtrr/earlymtrr.c"
37 #include "superio/intel/i3100/i3100_early_serial.c"
38 #include "cpu/x86/bist.h"
41 #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
43 static inline int spd_read_byte(u16 device, u8 address)
45 return smbus_read_byte(device, address);
48 #include "northbridge/intel/i3100/raminit_ep80579.c"
49 #include "lib/generic_sdram.c"
50 #include "../../intel/jarrell/debug.c"
51 #include "arch/i386/lib/stages.c"
53 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
55 static void main(unsigned long bist)
59 static const struct mem_controller mch[] = {
62 .f0 = PCI_DEV(0, 0x00, 0),
63 .channel0 = { DIMM2, DIMM3 },
68 /* Skip this if there was a built in self test failure */
70 if (memory_initialized())
74 /* Set up the console */
75 i3100_enable_superio();
76 i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
77 i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26);
82 /* Prevent the TCO timer from rebooting us */
83 i3100_halt_tco_timer();
85 /* Halt if there was a built in self test failure */
86 report_bist_failure(bist);
94 sdram_initialize(ARRAY_SIZE(mch), mch);
96 dump_pci_device(PCI_DEV(0, 0x00, 0));
98 dump_bar14(PCI_DEV(0, 0x00, 0));