src/mainboard/supermicro/x6dhr_ig2/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/winbond/w83627hf/w83627hf.h"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "debug.c"
  16 #include "watchdog.c"
  17 #include "reset.c"
  18 #include "x6dhr2_fixups.c"
  19 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22 #include <spd.h>
  23
  24 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  25 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, W83627HF_SP2)
  26
  27 #define DEVPRES_CONFIG  ( \
  28         DEVPRES_D0F0 | \
  29         DEVPRES_D1F0 | \
  30         DEVPRES_D2F0 | \
  31         DEVPRES_D3F0 | \
  32         DEVPRES_D4F0 | \
  33         DEVPRES_D6F0 | \
  34         0 )
  35 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  36
  37 static inline int spd_read_byte(unsigned device, unsigned address)
  38 {
  39         return smbus_read_byte(device, address);
  40 }
  41
  42 #include "northbridge/intel/e7520/raminit.c"
  43 #include "lib/generic_sdram.c"
  44 #include "arch/i386/lib/stages.c"
  45
  46 static void main(unsigned long bist)
  47 {
  48         static const struct mem_controller mch[] = {
  49                 {
  50                         .node_id = 0,
  51                         .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
  52                         .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
  53                 }
  54         };
  55
  56         if (bist == 0) {
  57                 /* Skip this if there was a built in self test failure */
  58                 early_mtrr_init();
  59                 if (memory_initialized())
  60                         skip_romstage();
  61         }
  62
  63         /* Setup the console */
  64         outb(0x87,0x2e);
  65         outb(0x87,0x2e);
  66         pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
  67         w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  68         uart_init();
  69         console_init();
  70
  71         /* Halt if there was a built in self test failure */
  72 //      report_bist_failure(bist);
  73
  74         /* MOVE ME TO A BETTER LOCATION !!! */
  75         /* config LPC decode for flash memory access */
  76         device_t dev;
  77         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
  78         if (dev == PCI_DEV_INVALID)
  79                 die("Missing ich5?");
  80         pci_write_config32(dev, 0xe8, 0x00000000);
  81         pci_write_config8(dev, 0xf0, 0x00);
  82
  83 #if 0
  84         display_cpuid_update_microcode();
  85         print_pci_devices();
  86 #endif
  87 #if 1
  88         enable_smbus();
  89 #endif
  90 #if 0
  91 //      dump_spd_registers(&cpu[0]);
  92         int i;
  93         for(i = 0; i < 1; i++)
  94                 dump_spd_registers();
  95 #endif
  96         disable_watchdogs();
  97 //      dump_ipmi_registers();
  98         mainboard_set_e7520_leds();
  99         sdram_initialize(ARRAY_SIZE(mch), mch);
 100 #if 0
 101         dump_pci_devices();
 102         dump_pci_device(PCI_DEV(0, 0x00, 0));
 103         dump_bar14(PCI_DEV(0, 0x00, 0));
 104 #endif
 105
 106 #if 0 // temporarily disabled
 107         /* Check the first 1M */
 108 //      ram_check(0x00000000, 0x000100000);
 109 //      ram_check(0x00000000, 0x000a0000);
 110 //      ram_check(0x00100000, 0x01000000);
 111         ram_check(0x00100000, 0x00100100);
 112         /* check the first 1M in the 3rd Gig */
 113 //      ram_check(0x30100000, 0x31000000);
 114 #endif
 115 #if 0
 116         ram_check(0x00000000, 0x02000000);
 117 #endif
 118 }