src/mainboard/via/epia-m/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <device/pci_ids.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <arch/hlt.h>
   8 #include <stdlib.h>
   9 #include <console/console.h>
  10 #include "northbridge/via/vt8623/raminit.h"
  11 #include "cpu/x86/mtrr/earlymtrr.c"
  12 #include "cpu/x86/bist.h"
  13 #include "pc80/udelay_io.c"
  14 #include "lib/delay.c"
  15 #include "cpu/x86/lapic/boot_cpu.c"
  16 #include "lib/debug.c"
  17 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
  18 #include "southbridge/via/vt8235/vt8235_early_serial.c"
  19
  20 static inline int spd_read_byte(unsigned device, unsigned address)
  21 {
  22         return smbus_read_byte(device, address);
  23 }
  24
  25 #include "northbridge/via/vt8623/raminit.c"
  26
  27 static void enable_mainboard_devices(void)
  28 {
  29         device_t dev;
  30
  31         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
  32                                        PCI_DEVICE_ID_VIA_8235), 0);
  33
  34         if (dev == PCI_DEV_INVALID) {
  35                 die("Southbridge not found!!!\n");
  36         }
  37         pci_write_config8(dev, 0x50, 0x80);
  38         pci_write_config8(dev, 0x51, 0x1f);
  39 #if 0
  40         // This early setup switches IDE into compatibility mode before PCI gets
  41         // a chance to assign I/Os
  42         // movl    $CONFIG_ADDR(0, 0x89, 0x42), %eax
  43         // //      movb    $0x09, %dl
  44         // movb    $0x00, %dl
  45         // PCI_WRITE_CONFIG_BYTE
  46 #endif
  47         /* we do this here as in V2, we can not yet do raw operations
  48          * to pci!
  49          */
  50         dev += 0x100; /* ICKY */
  51
  52         pci_write_config8(dev, 0x04, 7);
  53         pci_write_config8(dev, 0x40, 3);
  54         pci_write_config8(dev, 0x42, 0);
  55         pci_write_config8(dev, 0x3c, 0xe);
  56         pci_write_config8(dev, 0x3d, 0);
  57 }
  58
  59 static void enable_shadow_ram(void)
  60 {
  61         device_t dev = 0; /* no need to look up 0:0.0 */
  62         unsigned char shadowreg;
  63         /* dev 0 for southbridge */
  64         shadowreg = pci_read_config8(dev, 0x63);
  65         /* 0xf0000-0xfffff */
  66         shadowreg |= 0x30;
  67         pci_write_config8(dev, 0x63, shadowreg);
  68 }
  69
  70 static void main(unsigned long bist)
  71 {
  72         device_t dev;
  73
  74         /* Enable VGA; 32MB buffer. */
  75         pci_write_config8(0, 0xe1, 0xdd);
  76
  77         /*
  78          * Disable the firewire stuff, which apparently steps on IO 0+ on
  79          * reset. Doh!
  80          */
  81         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
  82                                 PCI_DEVICE_ID_VIA_6305), 0);
  83         if (dev != PCI_DEV_INVALID)
  84                 pci_write_config8(dev, 0x15, 0x1c);
  85
  86         enable_vt8235_serial();
  87         uart_init();
  88         console_init();
  89
  90         enable_smbus();
  91
  92         /* Halt if there was a built in self test failure */
  93         report_bist_failure(bist);
  94
  95         // init_timer();
  96
  97         post_code(0x05);
  98
  99         print_debug(" Enabling mainboard devices\n");
 100         enable_mainboard_devices();
 101
 102         print_debug(" Enabling shadow ram\n");
 103         enable_shadow_ram();
 104
 105         ddr_ram_setup((const struct mem_controller *)0);
 106
 107         if (bist == 0)
 108                 early_mtrr_init();
 109
 110         //dump_pci_devices();
 111 }