2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
5 * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 /* Based on romstage.c from the SpaceRunner-LX mainboard. */
26 #include <device/pci_def.h>
28 #include <device/pnp_def.h>
30 #include <console/console.h>
31 #include "cpu/x86/bist.h"
32 #include "cpu/x86/msr.h"
33 #include <cpu/amd/lxdef.h>
34 #include <cpu/amd/geode_post_code.h>
35 #include "southbridge/amd/cs5536/cs5536.h"
37 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
38 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
39 #include "superio/ite/it8712f/it8712f_early_serial.c"
41 /* Bit0 enables Spread Spectrum. */
42 #define SMC_CONFIG 0x01
44 #define ManualConf 1 /* No automatic strapped PLL config */
45 #define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
46 #define PLLMSRlo 0x00DE6001
48 static inline int spd_read_byte(unsigned int device, unsigned int address)
51 return 0xFF; /* No DIMM1, don't even try. */
53 return smbus_read_byte(device, address);
56 #if !CONFIG_BOARD_OLD_REVISION
57 /* Send config data to System Management Controller via SMB. */
58 static int smc_send_config(unsigned char config_data)
60 if (smbus_check_stop_condition(SMBUS_IO_BASE))
62 if (smbus_start_condition(SMBUS_IO_BASE))
64 if (smbus_send_slave_address(SMBUS_IO_BASE, 0x50)) // SMC address
66 if (smbus_send_command(SMBUS_IO_BASE, 0x28)) // set config data
68 if (smbus_send_command(SMBUS_IO_BASE, 0x01)) // data length
70 if (smbus_send_command(SMBUS_IO_BASE, config_data))
72 smbus_stop_condition(SMBUS_IO_BASE);
77 #include "northbridge/amd/lx/raminit.h"
78 #include "northbridge/amd/lx/pll_reset.c"
79 #include "northbridge/amd/lx/raminit.c"
80 #include "lib/generic_sdram.c"
81 #include "cpu/amd/model_lx/cpureginit.c"
82 #include "cpu/amd/model_lx/syspreinit.c"
83 #include "cpu/amd/model_lx/msrinit.c"
85 static const u16 sio_init_table[] = { // hi=data, lo=index
86 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...)
87 0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled
88 0x1423, // don't delay PoWeROK1/2
89 0x9072, // watchdog triggers PWROK, counts seconds
90 #if !CONFIG_USE_WATCHDOG_ON_BOOT
91 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
93 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
94 0xBF27, 0xFF28, 0x2D29, // (GP36=FAN_CTL3 (PWM), GP23,22,16,15=SPI, GP13=PWROK1)
95 0x66B8, 0x0CB9, // enable pullups on SPI, RS485_EN
96 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE
97 0x06C8, // config GP12,11 as output, GP10 as input
98 0x2DF5, // map Hw Monitor Thermal Output to GP55
99 #if CONFIG_BOARD_OLD_REVISION
100 0x1F2A, 0xC072, // switch GP13 to GPIO, WDT output from PWROK to KRST
104 /* Early mainboard specific GPIO setup. */
105 static void mb_gpio_init(void)
109 /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */
110 it8712f_enter_conf();
111 for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
112 u16 val = sio_init_table[i];
113 outb((u8)val, SIO_INDEX);
114 outb(val >> 8, SIO_DATA);
119 void main(unsigned long bist)
123 static const struct mem_controller memctrl[] = {
124 {.channel0 = {DIMM0, DIMM1}}
130 cs5536_early_setup();
133 * Note: Must do this AFTER the early_setup! It is counting on some
134 * early MSR setup for CS5536.
136 it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
141 /* Halt if there was a built in self test failure */
142 report_bist_failure(bist);
144 pll_reset(ManualConf);
146 cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
148 #if !CONFIG_BOARD_OLD_REVISION
150 /* bit0 = Spread Spectrum */
151 if ((err = smc_send_config(SMC_CONFIG))) {
153 print_err_char('0'+err);
154 print_err(" sending config data to SMC\n");
158 sdram_initialize(1, memctrl);
160 /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */