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(parent: cb91e15) | patch
Add support for Intel Panther Point PCH
authorStefan Reinauer <stefan.reinauer@coreboot.org>
Tue, 3 Apr 2012 22:07:22 +0000 (00:07 +0200)
committerStefan Reinauer <stefan.reinauer@coreboot.org>
Wed, 4 Apr 2012 17:10:51 +0000 (19:10 +0200)
commit8e073829ec69ee89b3e91f4c040c96988084a526
tree2e2b378ec66aa3ecd563b253726aae6e71db043atree | snapshot
parentcb91e1525eb0b81f9bc2e24e3404d6a9efc1cce3commit | diff
Add support for Intel Panther Point PCH

Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/853
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
43 files changed:
src/Kconfig diff | blob | history
src/southbridge/intel/Kconfig diff | blob | history
src/southbridge/intel/Makefile.inc diff | blob | history
src/southbridge/intel/bd82x6x/Kconfig [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/Makefile.inc [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/audio.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/irqlinks.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/lpc.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/pch.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/pcie.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/sata.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/sleepstates.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/smbus.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/acpi/usb.asl [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/azalia.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/bootblock.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/chip.h [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/early_me.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/early_smbus.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/early_usb.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/finalize.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/gpio.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/gpio.h [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/lpc.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/me.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/me.h [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/me_8.x.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/me_status.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/nvs.h [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/pch.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/pch.h [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/pci.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/pcie.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/reset.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/sata.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/smbus.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/smbus.h [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/smi.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/smihandler.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/usb_debug.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/usb_ehci.c [new file with mode: 0644] blob
src/southbridge/intel/bd82x6x/watchdog.c [new file with mode: 0644] blob
my coreboot WIP stuff (asus m5a99x-evo board)