2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
25 #define ME_RETRY 100000 /* 1 second */
26 #define ME_DELAY 10 /* 10 us */
29 * Management Engine PCI registers
32 #define PCI_CPU_DEVICE PCI_DEV(0,0,0)
33 #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
34 #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
36 #define PCI_ME_HFS 0x40
37 #define ME_HFS_CWS_RESET 0
38 #define ME_HFS_CWS_INIT 1
39 #define ME_HFS_CWS_REC 2
40 #define ME_HFS_CWS_NORMAL 5
41 #define ME_HFS_CWS_WAIT 6
42 #define ME_HFS_CWS_TRANS 7
43 #define ME_HFS_CWS_INVALID 8
44 #define ME_HFS_STATE_PREBOOT 0
45 #define ME_HFS_STATE_M0_UMA 1
46 #define ME_HFS_STATE_M3 4
47 #define ME_HFS_STATE_M0 5
48 #define ME_HFS_STATE_BRINGUP 6
49 #define ME_HFS_STATE_ERROR 7
50 #define ME_HFS_ERROR_NONE 0
51 #define ME_HFS_ERROR_UNCAT 1
52 #define ME_HFS_ERROR_IMAGE 3
53 #define ME_HFS_ERROR_DEBUG 4
54 #define ME_HFS_MODE_NORMAL 0
55 #define ME_HFS_MODE_DEBUG 2
56 #define ME_HFS_MODE_DIS 3
57 #define ME_HFS_MODE_OVER_JMPR 4
58 #define ME_HFS_MODE_OVER_MEI 5
59 #define ME_HFS_BIOS_DRAM_ACK 1
60 #define ME_HFS_ACK_NO_DID 0
61 #define ME_HFS_ACK_RESET 1
62 #define ME_HFS_ACK_PWR_CYCLE 2
63 #define ME_HFS_ACK_S3 3
64 #define ME_HFS_ACK_S4 4
65 #define ME_HFS_ACK_S5 5
66 #define ME_HFS_ACK_GBL_RESET 6
67 #define ME_HFS_ACK_CONTINUE 7
73 u32 operation_state: 3;
74 u32 fw_init_complete: 1;
76 u32 update_in_progress: 1;
78 u32 operation_mode: 4;
80 u32 boot_options_present: 1;
83 } __attribute__ ((packed));
85 #define PCI_ME_UMA 0x44
93 } __attribute__ ((packed));
95 #define PCI_ME_H_GS 0x4c
96 #define ME_INIT_DONE 1
97 #define ME_INIT_STATUS_SUCCESS 0
98 #define ME_INIT_STATUS_NOMEM 1
99 #define ME_INIT_STATUS_ERROR 2
106 } __attribute__ ((packed));
108 #define PCI_ME_GMES 0x48
109 #define ME_GMES_PHASE_ROM 0
110 #define ME_GMES_PHASE_BUP 1
111 #define ME_GMES_PHASE_UKERNEL 2
112 #define ME_GMES_PHASE_POLICY 3
113 #define ME_GMES_PHASE_MODULE 4
114 #define ME_GMES_PHASE_UNKNOWN 5
115 #define ME_GMES_PHASE_HOST 6
118 u32 bist_in_prog : 1;
119 u32 icc_prog_sts : 2;
121 u32 cpu_replaced_sts : 1;
124 u32 warm_rst_req_for_df : 1;
125 u32 cpu_replaced_valid : 1;
129 u32 current_state: 8;
130 u32 current_pmevent: 4;
131 u32 progress_code: 4;
132 } __attribute__ ((packed));
134 #define PCI_ME_HERES 0xbc
135 #define PCI_ME_EXT_SHA1 0x00
136 #define PCI_ME_EXT_SHA256 0x02
137 #define PCI_ME_HER(x) (0xc0+(4*(x)))
140 u32 extend_reg_algorithm: 4;
142 u32 extend_feature_present: 1;
143 u32 extend_reg_valid: 1;
144 } __attribute__ ((packed));
147 * Management Engine MEI registers
150 #define MEI_H_CB_WW 0x00
151 #define MEI_H_CSR 0x04
152 #define MEI_ME_CB_RW 0x08
153 #define MEI_ME_CSR_HA 0x0c
156 u32 interrupt_enable: 1;
157 u32 interrupt_status: 1;
158 u32 interrupt_generate: 1;
162 u32 buffer_read_ptr: 8;
163 u32 buffer_write_ptr: 8;
165 } __attribute__ ((packed));
167 #define MEI_ADDRESS_CORE 0x01
168 #define MEI_ADDRESS_AMT 0x02
169 #define MEI_ADDRESS_RESERVED 0x03
170 #define MEI_ADDRESS_WDT 0x04
171 #define MEI_ADDRESS_MKHI 0x07
172 #define MEI_ADDRESS_ICC 0x08
173 #define MEI_ADDRESS_THERMAL 0x09
175 #define MEI_HOST_ADDRESS 0
178 u32 client_address: 8;
183 } __attribute__ ((packed));
185 #define MKHI_GROUP_ID_CBM 0x00
186 #define MKHI_GROUP_ID_FWCAPS 0x03
187 #define MKHI_GROUP_ID_MDES 0x08
188 #define MKHI_GROUP_ID_GEN 0xff
190 #define MKHI_GLOBAL_RESET 0x0b
192 #define MKHI_FWCAPS_GET_RULE 0x02
194 #define MKHI_MDES_ENABLE 0x09
196 #define MKHI_GET_FW_VERSION 0x02
197 #define MKHI_END_OF_POST 0x0c
198 #define MKHI_FEATURE_OVERRIDE 0x14
206 } __attribute__ ((packed));
208 struct me_fw_version {
211 u16 code_build_number;
215 u16 recovery_build_number;
216 u16 recovery_hot_fix;
217 } __attribute__ ((packed));
220 #define HECI_EOP_STATUS_SUCCESS 0x0
221 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
223 #define CBM_RR_GLOBAL_RESET 0x01
225 #define GLOBAL_RESET_BIOS_MRC 0x01
226 #define GLOBAL_RESET_BIOS_POST 0x02
227 #define GLOBAL_RESET_MEBX 0x03
229 struct me_global_reset {
232 } __attribute__ ((packed));
238 ME_RECOVERY_BIOS_PATH,
239 ME_DISABLE_BIOS_PATH,
240 ME_FIRMWARE_UPDATE_BIOS_PATH,
243 /* Defined in me_status.c for both romstage and ramstage */
244 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
247 void intel_early_me_status(void);
248 int intel_early_me_init(void);
249 int intel_early_me_uma_size(void);
250 int intel_early_me_init_done(u8 status);
252 /* ME Kernel Host Interface Messages */
253 int mkhi_end_of_post(void);
254 int mkhi_global_reset(void);
258 void intel_me_finalize_smm(void);
261 u32 major_version : 16;
262 u32 minor_version : 16;
263 u32 hotfix_version : 16;
264 u32 build_version : 16;
265 } __attribute__ ((packed)) mbp_fw_version_name;
269 u8 icc_profile_soft_strap;
270 u8 icc_profile_index;
272 u32 register_lock_mask[3];
273 } __attribute__ ((packed)) mbp_icc_profile;
278 u32 manageability : 1;
279 u32 small_business : 1;
280 u32 l3manageability : 1;
285 u32 icc_over_clocking : 1;
296 } __attribute__ ((packed)) mefwcaps_sku;
300 u16 authenticate_module : 1;
301 u16 s3authentication : 1;
302 u16 flash_wear_out : 1;
303 u16 flash_variable_security : 1;
304 u16 wwan3gpresent : 1;
307 } __attribute__ ((packed)) tdt_state_flag;
311 u8 last_theft_trigger;
312 tdt_state_flag flags;
313 } __attribute__ ((packed)) tdt_state_info;
316 u32 platform_target_usage_type : 4;
317 u32 platform_target_market_type : 2;
320 u32 intel_me_fw_image_type : 4;
321 u32 platform_brand : 4;
323 } __attribute__ ((packed)) platform_type_rule_data;
326 mefwcaps_sku fw_capabilities;
334 } __attribute__ ((packed)) mbp_rom_bist_data;
341 platform_type_rule_data rule_data;
346 mbp_fw_version_name fw_version_name;
347 mbp_fw_caps fw_caps_sku;
348 mbp_rom_bist_data rom_bist_data;
349 mbp_platform_key platform_key;
350 mbp_plat_type fw_plat_type;
351 mbp_icc_profile icc_profile;
352 tdt_state_info at_state;
360 } __attribute__ ((packed)) mbp_header;
367 } __attribute__ ((packed)) mbp_item_header;
372 mefwcaps_sku caps_sku;
374 } __attribute__ ((packed));
376 #endif /* _INTEL_ME_H */