src/southbridge/intel/bd82x6x/sata.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <arch/io.h>
  22 #include <console/console.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include "pch.h"
  27
  28 typedef struct southbridge_intel_bd82x6x_config config_t;
  29
  30 static void sata_init(struct device *dev)
  31 {
  32         u32 reg32;
  33         u16 reg16;
  34         /* Get the chip configuration */
  35         config_t *config = dev->chip_info;
  36
  37         printk(BIOS_DEBUG, "pch_sata: initializing...\n");
  38
  39         if (config == NULL) {
  40                 printk(BIOS_ERR, "pch_sata: error: device not in devicetree.cb!\n");
  41                 return;
  42         }
  43
  44         /* SATA configuration */
  45
  46         /* Enable BARs */
  47         pci_write_config16(dev, PCI_COMMAND, 0x0007);
  48
  49         if (config->ide_legacy_combined) {
  50                 printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
  51                 /* Combine IDE - SATA configuration */
  52                 pci_write_config16(dev, 0x90, 0x0000);
  53
  54                 /* No AHCI: clear AHCI base */
  55                 pci_write_config32(dev, 0x24, 0x00000000);
  56                 /* And without AHCI BAR no memory decoding */
  57                 reg16 = pci_read_config16(dev, PCI_COMMAND);
  58                 reg16 &= ~PCI_COMMAND_MEMORY;
  59                 pci_write_config16(dev, PCI_COMMAND, reg16);
  60
  61                 pci_write_config8(dev, 0x09, 0x80);
  62
  63                 /* Set timings */
  64                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
  65                                 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
  66                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
  67                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
  68                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
  69
  70                 /* Sync DMA */
  71                 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
  72                 pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
  73
  74                 /* Set IDE I/O Configuration */
  75                 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
  76                 pci_write_config32(dev, IDE_CONFIG, reg32);
  77
  78                 /* Port enable */
  79                 reg16 = pci_read_config16(dev, 0x92);
  80                 reg16 &= ~0x3f;
  81                 reg16 |= config->sata_port_map;
  82                 pci_write_config16(dev, 0x92, reg16);
  83
  84                 /* SATA Initialization register */
  85                 pci_write_config32(dev, 0x94,
  86                            ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
  87         } else if(config->sata_ahci) {
  88                 u32 abar;
  89
  90                 printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
  91                 /* Set Sata Controller Mode. */
  92                 pci_write_config16(dev, 0x90, 0x0060 |
  93                                    ((config->sata_port_map ^ 0x3f) << 8));
  94
  95                 /* Set Interrupt Line */
  96                 /* Interrupt Pin is set by D31IP.PIP */
  97                 pci_write_config8(dev, INTR_LN, 0x0a);
  98
  99                 /* Set timings */
 100                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 101                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 102                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
 103                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 104                                 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
 105
 106                 /* Sync DMA */
 107                 pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
 108                 pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
 109
 110                 /* Set IDE I/O Configuration */
 111                 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
 112                 pci_write_config32(dev, IDE_CONFIG, reg32);
 113
 114                 /* for AHCI, Port Enable is managed in memory mapped space */
 115                 reg16 = pci_read_config16(dev, 0x92);
 116                 reg16 &= ~0x3f; /* 6 ports SKU + ORM */
 117                 reg16 |= 0x8000 | config->sata_port_map;
 118                 pci_write_config16(dev, 0x92, reg16);
 119
 120                 /* SATA Initialization register */
 121                 pci_write_config32(dev, 0x94,
 122                            ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
 123
 124                 /* Initialize AHCI memory-mapped space */
 125                 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 126                 printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
 127                 /* CAP (HBA Capabilities) : enable power management */
 128                 reg32 = read32(abar + 0x00);
 129                 reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
 130                 reg32 &= ~0x00020060; // clear SXS+EMS+PMS
 131                 write32(abar + 0x00, reg32);
 132                 /* PI (Ports implemented) */
 133                 write32(abar + 0x0c, config->sata_port_map);
 134                 (void) read32(abar + 0x0c); /* Read back 1 */
 135                 (void) read32(abar + 0x0c); /* Read back 2 */
 136                 /* CAP2 (HBA Capabilities Extended)*/
 137                 reg32 = read32(abar + 0x24);
 138                 reg32 &= ~0x00000002;
 139                 write32(abar + 0x24, reg32);
 140                 /* VSP (Vendor Specific Register */
 141                 reg32 = read32(abar + 0xa0);
 142                 reg32 &= ~0x00000005;
 143                 write32(abar + 0xa0, reg32);
 144         } else {
 145                 printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
 146                 /* Set Sata Controller Mode. No Mapping(?) */
 147                 pci_write_config16(dev, 0x90, 0x0000);
 148
 149                 /* No AHCI: clear AHCI base */
 150                 pci_write_config32(dev, 0x24, 0x00000000);
 151
 152                 /* And without AHCI BAR no memory decoding */
 153                 reg16 = pci_read_config16(dev, PCI_COMMAND);
 154                 reg16 &= ~PCI_COMMAND_MEMORY;
 155                 pci_write_config16(dev, PCI_COMMAND, reg16);
 156
 157                 /* Native mode capable on both primary and secondary (0xa)
 158                  * or'ed with enabled (0x50) = 0xf
 159                  */
 160                 pci_write_config8(dev, 0x09, 0x8f);
 161
 162                 /* Set Interrupt Line */
 163                 /* Interrupt Pin is set by D31IP.PIP */
 164                 pci_write_config8(dev, INTR_LN, 0xff);
 165
 166                 /* Set timings */
 167                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 168                                 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 169                                 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
 170                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 171                                 IDE_SITRE | IDE_ISP_3_CLOCKS |
 172                                 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
 173
 174                 /* Sync DMA */
 175                 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
 176                 pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
 177
 178                 /* Set IDE I/O Configuration */
 179                 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
 180                 pci_write_config32(dev, IDE_CONFIG, reg32);
 181
 182                 /* Port enable */
 183                 reg16 = pci_read_config16(dev, 0x92);
 184                 reg16 &= ~0x3f;
 185                 reg16 |= config->sata_port_map;
 186                 pci_write_config16(dev, 0x92, reg16);
 187
 188                 /* SATA Initialization register */
 189                 pci_write_config32(dev, 0x94,
 190                            ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
 191         }
 192 }
 193
 194 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 195 {
 196         if (!vendor || !device) {
 197                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 198                                 pci_read_config32(dev, PCI_VENDOR_ID));
 199         } else {
 200                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 201                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 202         }
 203 }
 204
 205 static struct pci_operations sata_pci_ops = {
 206         .set_subsystem    = sata_set_subsystem,
 207 };
 208
 209 static struct device_operations sata_ops = {
 210         .read_resources         = pci_dev_read_resources,
 211         .set_resources          = pci_dev_set_resources,
 212         .enable_resources       = pci_dev_enable_resources,
 213         .init                   = sata_init,
 214         .scan_bus               = 0,
 215         .ops_pci                = &sata_pci_ops,
 216 };
 217
 218 /* Non-AHCI and Non-RAID Mode */
 219 static const struct pci_driver pch_sata_normal_driver __pci_driver = {
 220         .ops    = &sata_ops,
 221         .vendor = PCI_VENDOR_ID_INTEL,
 222         .device = 0x1c00,
 223 };
 224 static const struct pci_driver pch_sata_mobile_normal_driver __pci_driver = {
 225         .ops    = &sata_ops,
 226         .vendor = PCI_VENDOR_ID_INTEL,
 227         .device = 0x1c01,
 228 };
 229
 230 /* AHCI Mode */
 231 static const struct pci_driver pch_sata_ahci_driver __pci_driver = {
 232         .ops    = &sata_ops,
 233         .vendor = PCI_VENDOR_ID_INTEL,
 234         .device = 0x1c02,
 235 };
 236 static const struct pci_driver pch_sata_mobile_ahci_driver __pci_driver = {
 237         .ops    = &sata_ops,
 238         .vendor = PCI_VENDOR_ID_INTEL,
 239         .device = 0x1c03,
 240 };
 241 static const struct pci_driver pch_sata_mobile_ahci_driver_a __pci_driver = {
 242         .ops    = &sata_ops,
 243         .vendor = PCI_VENDOR_ID_INTEL,
 244         .device = 0x1e03,
 245 };
 246