2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * This is a ramstage driver for the Intel Management Engine found in the
24 * 6-series chipset. It handles the required boot-time messages over the
25 * MMIO-based Management Engine Interface to tell the ME that the BIOS is
26 * finished with POST. Additional messages are defined for debug but are
27 * not used unless the console loglevel is high enough.
30 #include <arch/acpi.h>
33 #include <console/console.h>
34 #include <device/pci_ids.h>
35 #include <device/pci_def.h>
40 # include <arch/romcc_io.h>
41 # include <northbridge/intel/sandybridge/pcie_config.c>
43 # include <device/device.h>
44 # include <device/pci.h>
51 #include <vendorcode/google/chromeos/gnvs.h>
55 /* Path that the BIOS should take based on ME state */
56 static const char *me_bios_path_values[] = {
57 [ME_NORMAL_BIOS_PATH] = "Normal",
58 [ME_S3WAKE_BIOS_PATH] = "S3 Wake",
59 [ME_ERROR_BIOS_PATH] = "Error",
60 [ME_RECOVERY_BIOS_PATH] = "Recovery",
61 [ME_DISABLE_BIOS_PATH] = "Disable",
62 [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
66 /* MMIO base address for MEI interface */
67 static u32 mei_base_address;
69 #if CONFIG_DEBUG_INTEL_ME
70 static void mei_dump(void *ptr, int dword, int offset, const char *type)
74 printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
81 printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword);
84 printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u "
85 "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth,
86 csr->buffer_read_ptr, csr->buffer_write_ptr,
87 csr->ready, csr->reset, csr->interrupt_generate,
88 csr->interrupt_status, csr->interrupt_enable);
92 printk(BIOS_SPEW, "CB: 0x%08x\n", dword);
95 printk(BIOS_SPEW, "0x%08x\n", offset);
100 # define mei_dump(ptr,dword,offset,type) do {} while (0)
104 * ME/MEI access helpers using memcpy to avoid aliasing.
107 static inline void mei_read_dword_ptr(void *ptr, int offset)
109 u32 dword = read32(mei_base_address + offset);
110 memcpy(ptr, &dword, sizeof(dword));
111 mei_dump(ptr, dword, offset, "READ");
114 static inline void mei_write_dword_ptr(void *ptr, int offset)
117 memcpy(&dword, ptr, sizeof(dword));
118 write32(mei_base_address + offset, dword);
119 mei_dump(ptr, dword, offset, "WRITE");
123 static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
125 u32 dword = pci_read_config32(dev, offset);
126 memcpy(ptr, &dword, sizeof(dword));
127 mei_dump(ptr, dword, offset, "PCI READ");
131 static inline void read_host_csr(struct mei_csr *csr)
133 mei_read_dword_ptr(csr, MEI_H_CSR);
136 static inline void write_host_csr(struct mei_csr *csr)
138 mei_write_dword_ptr(csr, MEI_H_CSR);
141 static inline void read_me_csr(struct mei_csr *csr)
143 mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
146 static inline void write_cb(u32 dword)
148 write32(mei_base_address + MEI_H_CB_WW, dword);
149 mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
152 static inline u32 read_cb(void)
154 u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
155 mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
159 /* Wait for ME ready bit to be asserted */
160 static int mei_wait_for_me_ready(void)
163 unsigned try = ME_RETRY;
172 printk(BIOS_ERR, "ME: failed to become ready\n");
176 static void mei_reset(void)
180 if (mei_wait_for_me_ready() < 0)
183 /* Reset host and ME circular buffers for next message */
184 read_host_csr(&host);
186 host.interrupt_generate = 1;
187 write_host_csr(&host);
189 if (mei_wait_for_me_ready() < 0)
192 /* Re-init and indicate host is ready */
193 read_host_csr(&host);
194 host.interrupt_generate = 1;
197 write_host_csr(&host);
200 static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
207 /* Number of dwords to write, ignoring MKHI */
208 ndata = mei->length >> 2;
210 /* Pad non-dword aligned request message length */
214 printk(BIOS_DEBUG, "ME: request does not include MKHI\n");
217 ndata++; /* Add MEI header */
220 * Make sure there is still room left in the circular buffer.
221 * Reset the buffer pointers if the requested message will not fit.
223 read_host_csr(&host);
224 if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
225 printk(BIOS_ERR, "ME: circular buffer full, resetting...\n");
227 read_host_csr(&host);
231 * This implementation does not handle splitting large messages
232 * across multiple transactions. Ensure the requested length
233 * will fit in the available circular buffer depth.
235 if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
236 printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n",
237 ndata + 2, host.buffer_depth);
241 /* Write MEI header */
242 mei_write_dword_ptr(mei, MEI_H_CB_WW);
245 /* Write MKHI header */
246 mei_write_dword_ptr(mkhi, MEI_H_CB_WW);
249 /* Write message data */
251 for (n = 0; n < ndata; ++n)
254 /* Generate interrupt to the ME */
255 read_host_csr(&host);
256 host.interrupt_generate = 1;
257 write_host_csr(&host);
259 /* Make sure ME is ready after sending request data */
260 return mei_wait_for_me_ready();
263 static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
264 void *rsp_data, int rsp_bytes)
266 struct mei_header mei_rsp;
267 struct mkhi_header mkhi_rsp;
268 struct mei_csr me, host;
273 /* Total number of dwords to read from circular buffer */
274 expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2;
279 * The interrupt status bit does not appear to indicate that the
280 * message has actually been received. Instead we wait until the
281 * expected number of dwords are present in the circular buffer.
283 for (n = ME_RETRY; n; --n) {
285 if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected)
290 printk(BIOS_ERR, "ME: timeout waiting for data: expected "
291 "%u, available %u\n", expected,
292 me.buffer_write_ptr - me.buffer_read_ptr);
296 /* Read and verify MEI response header from the ME */
297 mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW);
298 if (!mei_rsp.is_complete) {
299 printk(BIOS_ERR, "ME: response is not complete\n");
303 /* Handle non-dword responses and expect at least MKHI header */
304 ndata = mei_rsp.length >> 2;
305 if (mei_rsp.length & 3)
307 if (ndata != (expected - 1)) {
308 printk(BIOS_ERR, "ME: response is missing data\n");
312 /* Read and verify MKHI response header from the ME */
313 mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW);
314 if (!mkhi_rsp.is_response ||
315 mkhi->group_id != mkhi_rsp.group_id ||
316 mkhi->command != mkhi_rsp.command) {
317 printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, "
318 "command %u ?= %u, is_response %u\n", mkhi->group_id,
319 mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command,
320 mkhi_rsp.is_response);
323 ndata--; /* MKHI header has been read */
325 /* Make sure caller passed a buffer with enough space */
326 if (ndata != (rsp_bytes >> 2)) {
327 printk(BIOS_ERR, "ME: not enough room in response buffer: "
328 "%u != %u\n", ndata, rsp_bytes >> 2);
332 /* Read response data from the circular buffer */
334 for (n = 0; n < ndata; ++n)
337 /* Tell the ME that we have consumed the response */
338 read_host_csr(&host);
339 host.interrupt_status = 1;
340 host.interrupt_generate = 1;
341 write_host_csr(&host);
343 return mei_wait_for_me_ready();
346 static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
347 void *req_data, void *rsp_data, int rsp_bytes)
349 if (mei_send_msg(mei, mkhi, req_data) < 0)
351 if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0)
356 /* Send END OF POST message to the ME */
357 int mkhi_end_of_post(void)
359 struct mkhi_header mkhi = {
360 .group_id = MKHI_GROUP_ID_GEN,
361 .command = MKHI_END_OF_POST,
363 struct mei_header mei = {
365 .host_address = MEI_HOST_ADDRESS,
366 .client_address = MEI_ADDRESS_MKHI,
367 .length = sizeof(mkhi),
370 /* Send request and wait for response */
371 if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) {
372 printk(BIOS_ERR, "ME: END OF POST message failed\n");
376 printk(BIOS_INFO, "ME: END OF POST message successful\n");
380 #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__)
381 /* Get ME firmware version */
382 static int mkhi_get_fw_version(void)
384 struct me_fw_version version;
385 struct mkhi_header mkhi = {
386 .group_id = MKHI_GROUP_ID_GEN,
387 .command = MKHI_GET_FW_VERSION,
389 struct mei_header mei = {
391 .host_address = MEI_HOST_ADDRESS,
392 .client_address = MEI_ADDRESS_MKHI,
393 .length = sizeof(mkhi),
396 /* Send request and wait for response */
397 if (mei_sendrecv(&mei, &mkhi, NULL, &version, sizeof(version)) < 0) {
398 printk(BIOS_ERR, "ME: GET FW VERSION message failed\n");
402 printk(BIOS_INFO, "ME: Firmware Version %u.%u.%u.%u (code) "
403 "%u.%u.%u.%u (recovery)\n",
404 version.code_major, version.code_minor,
405 version.code_build_number, version.code_hot_fix,
406 version.recovery_major, version.recovery_minor,
407 version.recovery_build_number, version.recovery_hot_fix);
412 static inline void print_cap(const char *name, int state)
414 printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n",
415 name, state ? "en" : "dis");
418 /* Get ME Firmware Capabilities */
419 static int mkhi_get_fwcaps(void)
422 struct me_fwcaps cap;
423 struct mkhi_header mkhi = {
424 .group_id = MKHI_GROUP_ID_FWCAPS,
425 .command = MKHI_FWCAPS_GET_RULE,
427 struct mei_header mei = {
429 .host_address = MEI_HOST_ADDRESS,
430 .client_address = MEI_ADDRESS_MKHI,
431 .length = sizeof(mkhi) + sizeof(rule_id),
434 /* Send request and wait for response */
435 if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap, sizeof(cap)) < 0) {
436 printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
440 print_cap("Full Network manageability", cap.caps_sku.full_net);
441 print_cap("Regular Network manageability", cap.caps_sku.std_net);
442 print_cap("Manageability", cap.caps_sku.manageability);
443 print_cap("Small business technology", cap.caps_sku.small_business);
444 print_cap("Level III manageability", cap.caps_sku.l3manageability);
445 print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at);
446 print_cap("IntelR Capability Licensing Service (CLS)",
447 cap.caps_sku.intel_cls);
448 print_cap("IntelR Power Sharing Technology (MPC)",
449 cap.caps_sku.intel_mpc);
450 print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
451 print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
452 print_cap("IPV6", cap.caps_sku.ipv6);
453 print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
454 print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
455 print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan);
456 print_cap("TLS", cap.caps_sku.tls);
457 print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan);
463 /* Tell ME to issue a global reset */
464 int mkhi_global_reset(void)
466 struct me_global_reset reset = {
467 .request_origin = GLOBAL_RESET_BIOS_POST,
468 .reset_type = CBM_RR_GLOBAL_RESET,
470 struct mkhi_header mkhi = {
471 .group_id = MKHI_GROUP_ID_CBM,
472 .command = MKHI_GLOBAL_RESET,
474 struct mei_header mei = {
476 .length = sizeof(mkhi) + sizeof(reset),
477 .host_address = MEI_HOST_ADDRESS,
478 .client_address = MEI_ADDRESS_MKHI,
481 printk(BIOS_NOTICE, "ME: Requesting global reset\n");
483 /* Send request and wait for response */
484 if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
485 /* No response means reset will happen shortly... */
489 /* If the ME responded it rejected the reset request */
490 printk(BIOS_ERR, "ME: Global Reset failed\n");
496 void intel_me_finalize_smm(void)
502 pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
504 /* S3 path will have hidden this device already */
505 if (!mei_base_address || mei_base_address == 0xfffffff0)
508 /* Make sure ME is in a mode that expects EOP */
509 reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
510 memcpy(&hfs, ®32, sizeof(u32));
512 /* Abort and leave device alone if not normal mode */
514 hfs.working_state != ME_HFS_CWS_NORMAL ||
515 hfs.operation_mode != ME_HFS_MODE_NORMAL)
518 /* Try to send EOP command so ME stops accepting other commands */
521 /* Make sure IO is disabled */
522 reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
523 reg32 &= ~(PCI_COMMAND_MASTER |
524 PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
525 pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
527 /* Hide the PCI device */
528 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
533 /* Determine the path that we should take based on ME status */
534 static me_bios_path intel_me_path(device_t dev)
536 me_bios_path path = ME_DISABLE_BIOS_PATH;
540 #if CONFIG_HAVE_ACPI_RESUME
541 /* S3 wake skips all MKHI messages */
542 if (acpi_slp_type == 3) {
543 return ME_S3WAKE_BIOS_PATH;
547 pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
548 pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
550 /* Check and dump status */
551 intel_me_status(&hfs, &gmes);
553 /* Check for valid firmware */
555 return ME_ERROR_BIOS_PATH;
557 /* Check Current Working State */
558 switch (hfs.working_state) {
559 case ME_HFS_CWS_NORMAL:
560 path = ME_NORMAL_BIOS_PATH;
563 path = ME_RECOVERY_BIOS_PATH;
566 path = ME_DISABLE_BIOS_PATH;
570 /* Check Current Operation Mode */
571 switch (hfs.operation_mode) {
572 case ME_HFS_MODE_NORMAL:
574 case ME_HFS_MODE_DEBUG:
575 case ME_HFS_MODE_DIS:
576 case ME_HFS_MODE_OVER_JMPR:
577 case ME_HFS_MODE_OVER_MEI:
579 path = ME_DISABLE_BIOS_PATH;
583 /* Check for any error code */
585 path = ME_ERROR_BIOS_PATH;
590 /* Prepare ME for MEI messages */
591 static int intel_mei_setup(device_t dev)
593 struct resource *res;
597 /* Find the MMIO base for the ME interface */
598 res = find_resource(dev, PCI_BASE_ADDRESS_0);
599 if (!res || res->base == 0 || res->size == 0) {
600 printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
603 mei_base_address = res->base;
605 /* Ensure Memory and Bus Master bits are set */
606 reg32 = pci_read_config32(dev, PCI_COMMAND);
607 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
608 pci_write_config32(dev, PCI_COMMAND, reg32);
610 /* Clean up status for next message */
611 read_host_csr(&host);
612 host.interrupt_generate = 1;
615 write_host_csr(&host);
620 /* Read the Extend register hash of ME firmware */
621 static int intel_me_extend_valid(device_t dev)
623 struct me_heres status;
627 pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
628 if (!status.extend_feature_present) {
629 printk(BIOS_ERR, "ME: Extend Feature not present\n");
633 if (!status.extend_reg_valid) {
634 printk(BIOS_ERR, "ME: Extend Register not valid\n");
638 switch (status.extend_reg_algorithm) {
639 case PCI_ME_EXT_SHA1:
641 printk(BIOS_DEBUG, "ME: Extend SHA-1: ");
643 case PCI_ME_EXT_SHA256:
645 printk(BIOS_DEBUG, "ME: Extend SHA-256: ");
648 printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n",
649 status.extend_reg_algorithm);
653 for (i = 0; i < count; ++i) {
654 extend[i] = pci_read_config32(dev, PCI_ME_HER(i));
655 printk(BIOS_DEBUG, "%08x", extend[i]);
657 printk(BIOS_DEBUG, "\n");
660 /* Save hash in NVS for the OS to verify */
661 chromeos_set_me_hash(extend, count);
667 /* Hide the ME virtual PCI devices */
668 static void intel_me_hide(device_t dev)
674 /* Check whether ME is present and do basic init */
675 static void intel_me_init(device_t dev)
677 me_bios_path path = intel_me_path(dev);
679 /* Do initial setup and determine the BIOS path */
680 printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]);
683 case ME_S3WAKE_BIOS_PATH:
687 case ME_NORMAL_BIOS_PATH:
688 /* Validate the extend register */
689 if (intel_me_extend_valid(dev) < 0)
690 break; /* TODO: force recovery mode */
692 /* Prepare MEI MMIO interface */
693 if (intel_mei_setup(dev) < 0)
696 #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
697 /* Print ME firmware version */
698 mkhi_get_fw_version();
699 /* Print ME firmware capabilities */
704 * Leave the ME unlocked in this path.
705 * It will be locked via SMI command later.
709 case ME_ERROR_BIOS_PATH:
710 case ME_RECOVERY_BIOS_PATH:
711 case ME_DISABLE_BIOS_PATH:
712 case ME_FIRMWARE_UPDATE_BIOS_PATH:
714 * TODO(dlaurie) Force recovery mode if ME is unhappy?
720 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
722 if (!vendor || !device) {
723 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
724 pci_read_config32(dev, PCI_VENDOR_ID));
726 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
727 ((device & 0xffff) << 16) | (vendor & 0xffff));
731 static struct pci_operations pci_ops = {
732 .set_subsystem = set_subsystem,
735 static struct device_operations device_ops = {
736 .read_resources = pci_dev_read_resources,
737 .set_resources = pci_dev_set_resources,
738 .enable_resources = pci_dev_enable_resources,
739 .init = intel_me_init,
740 .scan_bus = scan_static_bus,
744 static const struct pci_driver intel_me __pci_driver = {
746 .vendor = PCI_VENDOR_ID_INTEL,
750 #endif /* !__SMM__ */