2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
5 * Copyright (C) 2011 Google Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
22 #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
24 /* PCH stepping values for LPC device */
33 * It does not matter where we put the SMBus I/O base, as long as we
34 * keep it consistent and don't interfere with other devices. Stage2
35 * will relocate this anyways.
36 * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
37 * again. But handling static BARs is a generic problem that should be
38 * solved in the device allocator.
40 #define SMBUS_IO_BASE 0x0400
41 #define SMBUS_SLAVE_ADDR 0x24
42 /* TODO Make sure these don't get changed by stage2 */
43 #define DEFAULT_GPIOBASE 0x0480
44 #define DEFAULT_PMBASE 0x0500
46 #define HPET_ADDR 0xfed00000
47 #define DEFAULT_RCBA 0xfed1c000
50 #define DEBUG_PERIODIC_SMIS 0
52 #if defined (__SMM__) && !defined(__ASSEMBLER__)
53 void intel_pch_finalize_smm(void);
56 #if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
57 #if !defined(__PRE_RAM__) && !defined(__SMM__)
59 int pch_silicon_revision(void);
60 void pch_enable(device_t dev);
61 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
63 void enable_smbus(void);
64 void enable_usb_bar(void);
65 int smbus_read_byte(unsigned device, unsigned address);
69 #define MAINBOARD_POWER_OFF 0
70 #define MAINBOARD_POWER_ON 1
71 #define MAINBOARD_POWER_KEEP 2
73 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
74 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
77 /* PCI Configuration Space (D30:F0): PCI2PCI */
87 #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
88 #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
89 #define PCH_ME_DEV PCI_DEV(0, 0x16, 0)
90 #define PCH_PCIE_DEV_SLOT 28
92 /* PCI Configuration Space (D31:F0): LPC */
93 #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
94 #define SERIRQ_CNTL 0x64
96 #define GEN_PMCON_1 0xa0
97 #define GEN_PMCON_2 0xa2
98 #define GEN_PMCON_3 0xa4
100 #define ETR3_CWORWRE (1 << 18)
101 #define ETR3_CF9GR (1 << 20)
103 /* GEN_PMCON_3 bits */
104 #define RTC_BATTERY_DEAD (1 << 2)
105 #define RTC_POWER_FAILED (1 << 1)
106 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
109 #define ACPI_CNTL 0x44
110 #define BIOS_CNTL 0xDC
111 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
112 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
113 #define GPIO_ROUT 0xb8
115 #define PIRQA_ROUT 0x60
116 #define PIRQB_ROUT 0x61
117 #define PIRQC_ROUT 0x62
118 #define PIRQD_ROUT 0x63
119 #define PIRQE_ROUT 0x68
120 #define PIRQF_ROUT 0x69
121 #define PIRQG_ROUT 0x6A
122 #define PIRQH_ROUT 0x6B
124 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
125 #define LPC_EN 0x82 /* LPC IF Enables Register */
126 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
127 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
128 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
129 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
130 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
131 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
132 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
133 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
134 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
135 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
136 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
137 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
138 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
139 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
141 /* PCI Configuration Space (D31:F1): IDE */
142 #define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1)
143 #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2)
144 #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5)
146 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */
147 #define IDE_DECODE_ENABLE (1 << 15)
148 #define IDE_SITRE (1 << 14)
149 #define IDE_ISP_5_CLOCKS (0 << 12)
150 #define IDE_ISP_4_CLOCKS (1 << 12)
151 #define IDE_ISP_3_CLOCKS (2 << 12)
152 #define IDE_RCT_4_CLOCKS (0 << 8)
153 #define IDE_RCT_3_CLOCKS (1 << 8)
154 #define IDE_RCT_2_CLOCKS (2 << 8)
155 #define IDE_RCT_1_CLOCKS (3 << 8)
156 #define IDE_DTE1 (1 << 7)
157 #define IDE_PPE1 (1 << 6)
158 #define IDE_IE1 (1 << 5)
159 #define IDE_TIME1 (1 << 4)
160 #define IDE_DTE0 (1 << 3)
161 #define IDE_PPE0 (1 << 2)
162 #define IDE_IE0 (1 << 1)
163 #define IDE_TIME0 (1 << 0)
164 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
166 #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
167 #define IDE_SSDE1 (1 << 3)
168 #define IDE_SSDE0 (1 << 2)
169 #define IDE_PSDE1 (1 << 1)
170 #define IDE_PSDE0 (1 << 0)
172 #define IDE_SDMA_TIM 0x4a
174 #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
175 #define SIG_MODE_SEC_NORMAL (0 << 18)
176 #define SIG_MODE_SEC_TRISTATE (1 << 18)
177 #define SIG_MODE_SEC_DRIVELOW (2 << 18)
178 #define SIG_MODE_PRI_NORMAL (0 << 16)
179 #define SIG_MODE_PRI_TRISTATE (1 << 16)
180 #define SIG_MODE_PRI_DRIVELOW (2 << 16)
181 #define FAST_SCB1 (1 << 15)
182 #define FAST_SCB0 (1 << 14)
183 #define FAST_PCB1 (1 << 13)
184 #define FAST_PCB0 (1 << 12)
185 #define SCB1 (1 << 3)
186 #define SCB0 (1 << 2)
187 #define PCB1 (1 << 1)
188 #define PCB0 (1 << 0)
190 #define SATA_SP 0xd0 /* Scratchpad */
192 /* PCI Configuration Space (D31:F3): SMBus */
193 #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
194 #define SMB_BASE 0x20
196 #define SMB_RCV_SLVA 0x09
199 #define I2C_EN (1 << 2)
200 #define SMB_SMI_EN (1 << 1)
201 #define HST_EN (1 << 0)
203 /* SMBus I/O bits. */
204 #define SMBHSTSTAT 0x0
205 #define SMBHSTCTL 0x2
206 #define SMBHSTCMD 0x3
207 #define SMBXMITADD 0x4
208 #define SMBHSTDAT0 0x5
209 #define SMBHSTDAT1 0x6
210 #define SMBBLKDAT 0x7
211 #define SMBTRNSADD 0x9
212 #define SMBSLVDATA 0xa
213 #define SMLINK_PIN_CTL 0xe
214 #define SMBUS_PIN_CTL 0xf
216 #define SMBUS_TIMEOUT (10 * 1000 * 100)
219 /* Southbridge IO BARs */
221 #define GPIOBASE 0x48
225 /* Root Complex Register Block */
228 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
229 #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
230 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
232 #define RCBA_AND_OR(bits, x, and, or) \
233 RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
234 #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
235 #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
236 #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
237 #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
239 #define VCH 0x0000 /* 32bit */
240 #define VCAP1 0x0004 /* 32bit */
241 #define VCAP2 0x0008 /* 32bit */
242 #define PVC 0x000c /* 16bit */
243 #define PVS 0x000e /* 16bit */
245 #define V0CAP 0x0010 /* 32bit */
246 #define V0CTL 0x0014 /* 32bit */
247 #define V0STS 0x001a /* 16bit */
249 #define V1CAP 0x001c /* 32bit */
250 #define V1CTL 0x0020 /* 32bit */
251 #define V1STS 0x0026 /* 16bit */
253 #define RCTCL 0x0100 /* 32bit */
254 #define ESD 0x0104 /* 32bit */
255 #define ULD 0x0110 /* 32bit */
256 #define ULBA 0x0118 /* 64bit */
258 #define RP1D 0x0120 /* 32bit */
259 #define RP1BA 0x0128 /* 64bit */
260 #define RP2D 0x0130 /* 32bit */
261 #define RP2BA 0x0138 /* 64bit */
262 #define RP3D 0x0140 /* 32bit */
263 #define RP3BA 0x0148 /* 64bit */
264 #define RP4D 0x0150 /* 32bit */
265 #define RP4BA 0x0158 /* 64bit */
266 #define HDD 0x0160 /* 32bit */
267 #define HDBA 0x0168 /* 64bit */
268 #define RP5D 0x0170 /* 32bit */
269 #define RP5BA 0x0178 /* 64bit */
270 #define RP6D 0x0180 /* 32bit */
271 #define RP6BA 0x0188 /* 64bit */
273 #define RPC 0x0224 /* 32bit */
274 #define RPFN 0x0238 /* 32bit */
276 #define TRSR 0x1e00 /* 8bit */
277 #define TRCR 0x1e10 /* 64bit */
278 #define TWDR 0x1e18 /* 64bit */
280 #define IOTR0 0x1e80 /* 64bit */
281 #define IOTR1 0x1e88 /* 64bit */
282 #define IOTR2 0x1e90 /* 64bit */
283 #define IOTR3 0x1e98 /* 64bit */
285 #define TCTL 0x3000 /* 8bit */
293 #define DIR_IDR 12 /* Interrupt D Pin Offset */
294 #define DIR_ICR 8 /* Interrupt C Pin Offset */
295 #define DIR_IBR 4 /* Interrupt B Pin Offset */
296 #define DIR_IAR 0 /* Interrupt A Pin Offset */
307 /* IO Buffer Programming */
308 #define IOBPIRI 0x2330
311 #define IOBPS_RW_BX ((1 << 9)|(1 << 10))
312 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
313 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
315 #define D31IP 0x3100 /* 32bit */
316 #define D31IP_TTIP 24 /* Thermal Throttle Pin */
317 #define D31IP_SIP2 20 /* SATA Pin 2 */
318 #define D31IP_SMIP 12 /* SMBUS Pin */
319 #define D31IP_SIP 8 /* SATA Pin */
320 #define D30IP 0x3104 /* 32bit */
321 #define D30IP_PIP 0 /* PCI Bridge Pin */
322 #define D29IP 0x3108 /* 32bit */
323 #define D29IP_E1P 0 /* EHCI #1 Pin */
324 #define D28IP 0x310c /* 32bit */
325 #define D28IP_P8IP 28 /* PCI Express Port 8 */
326 #define D28IP_P7IP 24 /* PCI Express Port 7 */
327 #define D28IP_P6IP 20 /* PCI Express Port 6 */
328 #define D28IP_P5IP 16 /* PCI Express Port 5 */
329 #define D28IP_P4IP 12 /* PCI Express Port 4 */
330 #define D28IP_P3IP 8 /* PCI Express Port 3 */
331 #define D28IP_P2IP 4 /* PCI Express Port 2 */
332 #define D28IP_P1IP 0 /* PCI Express Port 1 */
333 #define D27IP 0x3110 /* 32bit */
334 #define D27IP_ZIP 0 /* HD Audio Pin */
335 #define D26IP 0x3114 /* 32bit */
336 #define D26IP_E2P 0 /* EHCI #2 Pin */
337 #define D25IP 0x3118 /* 32bit */
338 #define D25IP_LIP 0 /* GbE LAN Pin */
339 #define D22IP 0x3124 /* 32bit */
340 #define D22IP_KTIP 12 /* KT Pin */
341 #define D22IP_IDERIP 8 /* IDE-R Pin */
342 #define D22IP_MEI2IP 4 /* MEI #2 Pin */
343 #define D22IP_MEI1IP 0 /* MEI #1 Pin */
344 #define D31IR 0x3140 /* 16bit */
345 #define D30IR 0x3142 /* 16bit */
346 #define D29IR 0x3144 /* 16bit */
347 #define D28IR 0x3146 /* 16bit */
348 #define D27IR 0x3148 /* 16bit */
349 #define D26IR 0x314c /* 16bit */
350 #define D25IR 0x3150 /* 16bit */
351 #define D22IR 0x315c /* 16bit */
352 #define OIC 0x31fe /* 16bit */
354 #define DIR_ROUTE(x,a,b,c,d) \
355 RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
356 ((b) << DIR_IBR) | ((a) << DIR_IAR))
358 #define RC 0x3400 /* 32bit */
359 #define HPTC 0x3404 /* 32bit */
360 #define GCS 0x3410 /* 32bit */
361 #define BUC 0x3414 /* 32bit */
362 #define PCH_DISABLE_GBE (1 << 5)
363 #define FD 0x3418 /* 32bit */
364 #define DISPBDF 0x3424 /* 16bit */
365 #define FD2 0x3428 /* 32bit */
366 #define CG 0x341c /* 32bit */
368 /* Function Disable 1 RCBA 0x3418 */
369 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27))
370 #define PCH_DISABLE_P2P (1 << 1)
371 #define PCH_DISABLE_SATA1 (1 << 2)
372 #define PCH_DISABLE_SMBUS (1 << 3)
373 #define PCH_DISABLE_HD_AUDIO (1 << 4)
374 #define PCH_DISABLE_EHCI2 (1 << 13)
375 #define PCH_DISABLE_LPC (1 << 14)
376 #define PCH_DISABLE_EHCI1 (1 << 15)
377 #define PCH_DISABLE_PCIE(x) (1 << (16 + x))
378 #define PCH_DISABLE_THERMAL (1 << 24)
379 #define PCH_DISABLE_SATA2 (1 << 25)
381 /* Function Disable 2 RCBA 0x3428 */
382 #define PCH_DISABLE_KT (1 << 4)
383 #define PCH_DISABLE_IDER (1 << 3)
384 #define PCH_DISABLE_MEI2 (1 << 2)
385 #define PCH_DISABLE_MEI1 (1 << 1)
386 #define PCH_ENABLE_DBDF (1 << 0)
389 #define GPIO_USE_SEL 0x00
390 #define GP_IO_SEL 0x04
392 #define GPO_BLINK 0x18
394 #define GPIO_USE_SEL2 0x30
395 #define GP_IO_SEL2 0x34
397 #define GPIO_USE_SEL3 0x40
398 #define GP_IO_SEL3 0x44
400 #define GP_RST_SEL1 0x60
401 #define GP_RST_SEL2 0x64
402 #define GP_RST_SEL3 0x68
406 #define WAK_STS (1 << 15)
407 #define PCIEXPWAK_STS (1 << 14)
408 #define PRBTNOR_STS (1 << 11)
409 #define RTC_STS (1 << 10)
410 #define PWRBTN_STS (1 << 8)
411 #define GBL_STS (1 << 5)
412 #define BM_STS (1 << 4)
413 #define TMROF_STS (1 << 0)
415 #define PCIEXPWAK_DIS (1 << 14)
416 #define RTC_EN (1 << 10)
417 #define PWRBTN_EN (1 << 8)
418 #define GBL_EN (1 << 5)
419 #define TMROF_EN (1 << 0)
421 #define SLP_EN (1 << 13)
422 #define SLP_TYP (7 << 10)
428 #define GBL_RLS (1 << 2)
429 #define BM_RLD (1 << 1)
430 #define SCI_EN (1 << 0)
432 #define PROC_CNT 0x10
436 #define PM2_CNT 0x50 // mobile only
437 #define GPE0_STS 0x20
438 #define PME_B0_STS (1 << 13)
439 #define PME_STS (1 << 11)
440 #define BATLOW_STS (1 << 10)
441 #define PCI_EXP_STS (1 << 9)
442 #define RI_STS (1 << 8)
443 #define SMB_WAK_STS (1 << 7)
444 #define TCOSCI_STS (1 << 6)
445 #define SWGPE_STS (1 << 2)
446 #define HOT_PLUG_STS (1 << 1)
448 #define PME_B0_EN (1 << 13)
449 #define PME_EN (1 << 11)
451 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
452 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
453 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
454 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
455 #define MCSMI_EN (1 << 11) // Trap microcontroller range access
456 #define BIOS_RLS (1 << 7) // asserts SCI on bit set
457 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
458 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
459 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
460 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
461 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
462 #define EOS (1 << 1) // End of SMI (deassert SMI#)
463 #define GBL_SMI_EN (1 << 0) // SMI# generation at all?
465 #define ALT_GP_SMI_EN 0x38
466 #define ALT_GP_SMI_STS 0x3a
467 #define GPE_CNTL 0x42
468 #define DEVACT_STS 0x44
473 * SPI Opcode Menu setup for SPIBAR lockdown
474 * should support most common flash chips.
477 #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
478 #define SPI_OPTYPE_0 0x01 /* Write, no address */
480 #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
481 #define SPI_OPTYPE_1 0x03 /* Write, address required */
483 #define SPI_OPMENU_2 0x03 /* READ: Read Data */
484 #define SPI_OPTYPE_2 0x02 /* Read, address required */
486 #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
487 #define SPI_OPTYPE_3 0x00 /* Read, no address */
489 #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
490 #define SPI_OPTYPE_4 0x03 /* Write, address required */
492 #define SPI_OPMENU_5 0x9f /* RDID: Read ID */
493 #define SPI_OPTYPE_5 0x00 /* Read, no address */
495 #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
496 #define SPI_OPTYPE_6 0x03 /* Write, address required */
498 #define SPI_OPMENU_7 0x52 /* BE52: Block Erase 0x52 */
499 #define SPI_OPTYPE_7 0x03 /* Write, address required */
501 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
502 (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
503 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
504 (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
506 #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
507 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
508 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
509 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
511 #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
513 #endif /* __ACPI__ */
514 #endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */
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