src/southbridge/intel/bd82x6x/chip.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
  21 #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
  22
  23 struct southbridge_intel_bd82x6x_config {
  24         /**
  25          * Interrupt Routing configuration
  26          * If bit7 is 1, the interrupt is disabled.
  27          */
  28         uint8_t pirqa_routing;
  29         uint8_t pirqb_routing;
  30         uint8_t pirqc_routing;
  31         uint8_t pirqd_routing;
  32         uint8_t pirqe_routing;
  33         uint8_t pirqf_routing;
  34         uint8_t pirqg_routing;
  35         uint8_t pirqh_routing;
  36
  37         /**
  38          * GPI Routing configuration
  39          *
  40          * Only the lower two bits have a meaning:
  41          * 00: No effect
  42          * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
  43          * 10: SCI (if corresponding GPIO_EN bit is also set)
  44          * 11: reserved
  45          */
  46         uint8_t gpi0_routing;
  47         uint8_t gpi1_routing;
  48         uint8_t gpi2_routing;
  49         uint8_t gpi3_routing;
  50         uint8_t gpi4_routing;
  51         uint8_t gpi5_routing;
  52         uint8_t gpi6_routing;
  53         uint8_t gpi7_routing;
  54         uint8_t gpi8_routing;
  55         uint8_t gpi9_routing;
  56         uint8_t gpi10_routing;
  57         uint8_t gpi11_routing;
  58         uint8_t gpi12_routing;
  59         uint8_t gpi13_routing;
  60         uint8_t gpi14_routing;
  61         uint8_t gpi15_routing;
  62
  63         uint32_t gpe0_en;
  64         uint16_t alt_gp_smi_en;
  65
  66         /* IDE configuration */
  67         uint32_t ide_legacy_combined;
  68         uint32_t sata_ahci;
  69         uint8_t sata_port_map;
  70
  71         uint32_t gen1_dec;
  72         uint32_t gen2_dec;
  73         uint32_t gen3_dec;
  74         uint32_t gen4_dec;
  75 };
  76
  77 extern struct chip_operations southbridge_intel_bd82x6x_ops;
  78
  79 #endif                          /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */