2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <arch/romcc_io.h>
28 void setup_pch_gpios(const struct pch_gpio_map *gpio)
30 u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
34 outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL);
36 outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
37 if (gpio->set1.direction)
38 outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL);
40 outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1);
41 if (gpio->set1.invert)
42 outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV);
44 outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK);
48 outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2);
50 outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
51 if (gpio->set2.direction)
52 outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2);
54 outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2);
58 outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3);
60 outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
61 if (gpio->set3.direction)
62 outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3);
64 outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3);