src/southbridge/intel/bd82x6x/acpi/lpc.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 // Intel LPC Bus Device  - 0:1f.0
  23
  24 Device (LPCB)
  25 {
  26         Name(_ADR, 0x001f0000)
  27
  28         OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
  29         Field (LPC0, AnyAcc, NoLock, Preserve)
  30         {
  31                 Offset (0x40),
  32                 PMBS,   16,     // PMBASE
  33                 Offset (0x60),  // Interrupt Routing Registers
  34                 PRTA,   8,
  35                 PRTB,   8,
  36                 PRTC,   8,
  37                 PRTD,   8,
  38                 Offset (0x68),
  39                 PRTE,   8,
  40                 PRTF,   8,
  41                 PRTG,   8,
  42                 PRTH,   8,
  43
  44                 Offset (0x80),  // IO Decode Ranges
  45                 IOD0,   8,
  46                 IOD1,   8,
  47
  48                 Offset (0xb8),  // GPIO Routing Control
  49                 GR00,    2,
  50                 GR01,    2,
  51                 GR02,    2,
  52                 GR03,    2,
  53                 GR04,    2,
  54                 GR05,    2,
  55                 GR06,    2,
  56                 GR07,    2,
  57                 GR08,    2,
  58                 GR09,    2,
  59                 GR10,    2,
  60                 GR11,    2,
  61                 GR12,    2,
  62                 GR13,    2,
  63                 GR14,    2,
  64                 GR15,    2,
  65
  66                 Offset (0xf0),  // RCBA
  67                 RCEN,   1,
  68                 ,       13,
  69                 RCBA,   18,
  70         }
  71
  72         #include "irqlinks.asl"
  73
  74         #include "acpi/ec.asl"
  75
  76         Device (DMAC)           // DMA Controller
  77         {
  78                 Name(_HID, EISAID("PNP0200"))
  79                 Name(_CRS, ResourceTemplate()
  80                 {
  81                         IO (Decode16, 0x00, 0x00, 0x01, 0x20)
  82                         IO (Decode16, 0x81, 0x81, 0x01, 0x11)
  83                         IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
  84                         IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
  85                         DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
  86                 })
  87         }
  88
  89         Device (FWH)            // Firmware Hub
  90         {
  91                 Name (_HID, EISAID("INT0800"))
  92                 Name (_CRS, ResourceTemplate()
  93                 {
  94                         Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
  95                 })
  96         }
  97
  98         Device (HPET)
  99         {
 100                 Name (_HID, EISAID("PNP0103"))
 101                 Name (_CID, 0x010CD041)
 102
 103                 Name(BUF0, ResourceTemplate()
 104                 {
 105                         Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)
 106                 })
 107
 108                 Method (_STA, 0)        // Device Status
 109                 {
 110                         If (HPTE) {
 111                                 // Note: Ancient versions of Windows don't want
 112                                 // to see the HPET in order to work right
 113                                 If (LGreaterEqual(OSYS, 2001)) {
 114                                         Return (0xf)    // Enable and show device
 115                                 } Else {
 116                                         Return (0xb)    // Enable and don't show device
 117                                 }
 118                         }
 119
 120                         Return (0x0)    // Not enabled, don't show.
 121                 }
 122
 123                 Method (_CRS, 0, Serialized) // Current resources
 124                 {
 125                         If (HPTE) {
 126                                 CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
 127                                 If (Lequal(HPAS, 1)) {
 128                                         Store(0xfed01000, HPT0)
 129                                 }
 130
 131                                 If (Lequal(HPAS, 2)) {
 132                                         Store(0xfed02000, HPT0)
 133                                 }
 134
 135                                 If (Lequal(HPAS, 3)) {
 136                                         Store(0xfed03000, HPT0)
 137                                 }
 138                         }
 139
 140                         Return (BUF0)
 141                 }
 142         }
 143
 144         Device(PIC)     // 8259 Interrupt Controller
 145         {
 146                 Name(_HID,EISAID("PNP0000"))
 147                 Name(_CRS, ResourceTemplate()
 148                 {
 149                         IO (Decode16, 0x20, 0x20, 0x01, 0x02)
 150                         IO (Decode16, 0x24, 0x24, 0x01, 0x02)
 151                         IO (Decode16, 0x28, 0x28, 0x01, 0x02)
 152                         IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
 153                         IO (Decode16, 0x30, 0x30, 0x01, 0x02)
 154                         IO (Decode16, 0x34, 0x34, 0x01, 0x02)
 155                         IO (Decode16, 0x38, 0x38, 0x01, 0x02)
 156                         IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
 157                         IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
 158                         IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
 159                         IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
 160                         IO (Decode16, 0xac, 0xac, 0x01, 0x02)
 161                         IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
 162                         IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
 163                         IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
 164                         IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
 165                         IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
 166                         IRQNoFlags () { 2 }
 167                 })
 168         }
 169
 170         Device(MATH)    // FPU
 171         {
 172                 Name (_HID, EISAID("PNP0C04"))
 173                 Name (_CRS, ResourceTemplate()
 174                 {
 175                         IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
 176                         IRQNoFlags() { 13 }
 177                 })
 178         }
 179
 180         Device(LDRC)    // LPC device: Resource consumption
 181         {
 182                 Name (_HID, EISAID("PNP0C02"))
 183                 Name (_UID, 2)
 184                 Name (_CRS, ResourceTemplate()
 185                 {
 186                         IO (Decode16, 0x2e, 0x2e, 0x1, 0x02)            // First SuperIO
 187                         IO (Decode16, 0x4e, 0x4e, 0x1, 0x02)            // Second SuperIO
 188                         IO (Decode16, 0x61, 0x61, 0x1, 0x01)            // NMI Status
 189                         IO (Decode16, 0x63, 0x63, 0x1, 0x01)            // CPU Reserved
 190                         IO (Decode16, 0x65, 0x65, 0x1, 0x01)            // CPU Reserved
 191                         IO (Decode16, 0x67, 0x67, 0x1, 0x01)            // CPU Reserved
 192                         IO (Decode16, 0x80, 0x80, 0x1, 0x01)            // Port 80 Post
 193                         IO (Decode16, 0x92, 0x92, 0x1, 0x01)            // CPU Reserved
 194                         IO (Decode16, 0xb2, 0xb2, 0x1, 0x02)            // SWSMI
 195                         //IO (Decode16, 0x800, 0x800, 0x1, 0x10)                // ACPI I/O trap
 196                         IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80)        // ICH7-M ACPI
 197                         IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40)    // ICH7-M GPIO
 198                 })
 199         }
 200
 201         Device (RTC)    // Real Time Clock
 202         {
 203                 Name (_HID, EISAID("PNP0B00"))
 204                 Name (_CRS, ResourceTemplate()
 205                 {
 206                         IO (Decode16, 0x70, 0x70, 1, 8)
 207 // Disable as Windows doesn't like it, and systems don't seem to use it.
 208 //                      IRQNoFlags() { 8 }
 209                 })
 210         }
 211
 212         Device (TIMR)   // Intel 8254 timer
 213         {
 214                 Name(_HID, EISAID("PNP0100"))
 215                 Name(_CRS, ResourceTemplate()
 216                 {
 217                         IO (Decode16, 0x40, 0x40, 0x01, 0x04)
 218                         IO (Decode16, 0x50, 0x50, 0x10, 0x04)
 219                         IRQNoFlags() {0}
 220                 })
 221         }
 222
 223         #include "acpi/superio.asl"
 224
 225 #ifdef ENABLE_TPM
 226         Device (TPM)            // Trusted Platform Module
 227         {
 228                 Name(_HID, EISAID("IFX0102"))
 229                 Name(_CID, 0x310cd041)
 230                 Name(_UID, 1)
 231
 232                 Method(_STA, 0)
 233                 {
 234                         If (TPMP) {
 235                                 Return (0xf)
 236                         }
 237                         Return (0x0)
 238                 }
 239
 240                 Name(_CRS, ResourceTemplate() {
 241                         IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
 242                         IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
 243                         Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
 244                         IRQ (Edge, Activehigh, Exclusive) { 6 }
 245                 })
 246         }
 247 #endif
 248 }