Add support for Intel Panther Point PCH
[coreboot.git] / src / southbridge / intel / bd82x6x / smbus.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2008-2009 coresystems GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; version 2 of
9  * the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
19  */
20
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/path.h>
24 #include <device/smbus.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
27 #include <device/pci_ops.h>
28 #include <arch/io.h>
29 #include "pch.h"
30 #include "smbus.h"
31
32 static void pch_smbus_init(device_t dev)
33 {
34         struct resource *res;
35         u16 reg16;
36
37         /* Enable clock gating */
38         reg16 = pci_read_config32(dev, 0x80);
39         reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
40         pci_write_config32(dev, 0x80, reg16);
41
42         /* Set Receive Slave Address */
43         res = find_resource(dev, PCI_BASE_ADDRESS_4);
44         if (res)
45                 outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
46 }
47
48 static int lsmbus_read_byte(device_t dev, u8 address)
49 {
50         u16 device;
51         struct resource *res;
52         struct bus *pbus;
53
54         device = dev->path.i2c.device;
55         pbus = get_pbus_smbus(dev);
56         res = find_resource(pbus->dev, 0x20);
57
58         return do_smbus_read_byte(res->base, device, address);
59 }
60
61 static struct smbus_bus_operations lops_smbus_bus = {
62         .read_byte      = lsmbus_read_byte,
63 };
64
65 static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
66 {
67         if (!vendor || !device) {
68                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
69                                 pci_read_config32(dev, PCI_VENDOR_ID));
70         } else {
71                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
72                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
73         }
74 }
75
76 static struct pci_operations smbus_pci_ops = {
77         .set_subsystem    = smbus_set_subsystem,
78 };
79
80 static void smbus_read_resources(device_t dev)
81 {
82         struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
83         res->base = SMBUS_IO_BASE;
84         res->size = 32;
85         res->limit = res->base + res->size - 1;
86         res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
87                      IORESOURCE_STORED | IORESOURCE_ASSIGNED;
88
89         /* Also add MMIO resource */
90         res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
91 }
92
93 static struct device_operations smbus_ops = {
94         .read_resources         = smbus_read_resources,
95         .set_resources          = pci_dev_set_resources,
96         .enable_resources       = pci_dev_enable_resources,
97         .scan_bus               = scan_static_bus,
98         .init                   = pch_smbus_init,
99         .ops_smbus_bus          = &lops_smbus_bus,
100         .ops_pci                = &smbus_pci_ops,
101 };
102
103 static const struct pci_driver pch_smbus __pci_driver = {
104         .ops    = &smbus_ops,
105         .vendor = PCI_VENDOR_ID_INTEL,
106         .device = 0x1c22,
107 };
108
109 static const struct pci_driver pch_smbus_a __pci_driver = {
110         .ops    = &smbus_ops,
111         .vendor = PCI_VENDOR_ID_INTEL,
112         .device = 0x1e22,
113 };