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stack op
2010-12-20
Stefan Rebernig
stack op
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2010-12-19
Stefan Rebernig
uart und extension anbindung
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2010-12-19
Stefan Rebernig
kleinigkeiten
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2010-12-19
Stefan Rebernig
modelsim lauffähig
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2010-12-19
Stefan Rebernig
version not running!
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tree
2010-12-17
Stefan Rebernig
7seg small changes
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2010-12-17
Stefan Rebernig
nochmal...
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2010-12-17
Stefan Rebernig
instr mem durch case, fibonacci als programm, 7seg...
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2010-12-17
Stefan REBERNIG
writeback_stage: differenzieren zwischen memory und...
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2010-12-17
Stefan REBERNIG
wb extension
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2010-12-17
Stefan REBERNIG
uart: blinkt zwar nur am led aber des is schon net...
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2010-12-14
Stefan Rebernig
fmax incr
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2010-12-11
Stefan Rebernig
added todo-vhdl.txt
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2010-12-11
Stefan Rebernig
fibonacci die 2.
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2010-12-11
Stefan Rebernig
fibonacci tested rc1, 107 cycles, 1k2le, 57MHz
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2010-12-11
Stefan Rebernig
fib 1
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2010-12-11
Stefan Rebernig
fib
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2010-12-11
Stefan Rebernig
call/return
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2010-12-11
Stefan Rebernig
return - erster versuch
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tree
2010-12-11
Stefan Rebernig
decoder for st-op
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2010-12-02
Stefan Rebernig
static branch - small bug fix
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2010-12-01
Stefan Rebernig
static branch - getestet, 58MHz lt quartus
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2010-12-01
Stefan Rebernig
static branch incl prediction rc1
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2010-12-01
Stefan Rebernig
static branch 1.0
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2010-11-29
Stefan Rebernig
stw.2
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2010-11-29
Stefan Rebernig
st
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2010-11-29
Stefan Rebernig
decoder add ldi
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2010-11-26
Stefan Rebernig
forward unit testcases (from assignments), everything...
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2010-11-17
Stefan Rebernig
kleine Änderungen
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2010-11-16
Stefan Rebernig
kleinigkeit ausgebessert
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2010-11-16
Stefan Rebernig
2nd forward unit - 58MHz with 31bit shift...
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2010-11-16
Stefan Rebernig
nop insertion added
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2010-11-15
Stefan Rebernig
pipeline erste version mit 31bit shifter (kostet 7MHz...
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2010-11-15
Stefan Rebernig
test pipe 2
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2010-11-15
Stefan Rebernig
pipe v1
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2010-11-15
Stefan Rebernig
blub
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2010-11-15
Stefan Rebernig
writeback stage
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2010-10-18
Stefan Rebernig
ARM up2date
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