fibonacci die 2.
authorStefan Rebernig <stefan.rebernig@gmail.com>
Sat, 11 Dec 2010 16:11:12 +0000 (17:11 +0100)
committerStefan Rebernig <stefan.rebernig@gmail.com>
Sat, 11 Dec 2010 16:11:12 +0000 (17:11 +0100)
cpu/src/core_top.vhd
cpu/src/writeback_stage_b.vhd

index 47eb124c0598186823acef49676ecdd5230f5d17..7a85f27d6954d529f5d4b73069001cf9139571a2 100644 (file)
@@ -49,8 +49,8 @@ architecture behav of core_top is
                  signal hword_pin  : std_logic;
                  signal byte_s_pin : std_logic;
                                 
-                                signal gpm_in_pin : extmod_rec;
-                                signal gpm_out_pin : gp_register_t;
+                signal gpm_in_pin : extmod_rec;
+                signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
 
 
index 5123f76a76bfb08c59ce09e0609667181e326d2b..c771c910909e8bc9da193d3c3c0f169f16ee9a95 100644 (file)
@@ -62,7 +62,7 @@ end process;
 
 
 
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en)
 
 begin
        wb_reg_nxt.address <= address;