fibonacci tested rc1, 107 cycles, 1k2le, 57MHz

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index 321364ee213fdf6f071ff19530c573929369edc0..cf8d69c0f8ce7b5389d37f2c6a422eb47935274a 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -72,5 +72,6 @@ add wave  -radix hexadecimal /pipeline_tb/addr_pin
 add wave  -radix hexadecimal /pipeline_tb/data_pin
 add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
 add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
+add wave  -radix decimal     /pipeline_tb/cycle_cnt
 
-run 5000 ns
+run 10000 ns

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index 01c11f07b82393499d2f094f7677825b52158672..911bd00678565ed0afc46de313a369fb8d92ef33 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -217,10 +217,15 @@ begin
                instr_s.reg_src1_addr := instruction(18 downto 15);
                instr_s.signext := instruction(2);
                instr_s.high_low := instruction(1);
+               instr_s.displacement(14 downto 0) := instruction(14 downto 0);
 
                instr_s.op_group := LDST_OP;
                instr_s.op_detail(NO_PSW_OPT) := '1';
 
+               if (instr_s.displacement(14) = '1') then
+                       instr_s.displacement(31 downto 15) := (others => '1');
+               end if;
+
                if (instr_s.opcode = "11010") then              --ldi
                        if (instr_s.high_low = '1') then
                                instr_s.immediate(31 downto 16) := instruction(18 downto 3);
@@ -275,6 +280,10 @@ begin
                instr_s.op_detail(NO_PSW_OPT) := '1';
                 instr_s.op_detail(ST_OPT) := '1';
                instr_s.op_group := LDST_OP;
+
+               if (instr_s.displacement(14) = '1') then
+                       instr_s.displacement(31 downto 15) := (others => '1');
+               end if;
        end if;
 
 --     when "10001" =>         --sth

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index fd86d721e9910f178d5ed2f58e90a803241d47d6..7392a95a350758f4750410e401947ced54d52c38 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -54,6 +54,8 @@ architecture behavior of pipeline_tb is
                                 signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
 
+                signal cycle_cnt : integer;
+
 
 begin
 
@@ -149,6 +151,18 @@ begin
     wait for cc/2;
   end process CLKGEN;
   
+
+  cnt : process(sys_clk_pin, sys_res_n_pin)
+
+  begin
+
+       if (sys_res_n_pin = '0') then
+               cycle_cnt <= 0;
+       elsif (sys_clk_pin'event and sys_clk_pin = '1') then
+               cycle_cnt <= cycle_cnt + 1;
+       end if;
+
+  end process cnt;
 -------------------------------------------------------------------------------
 -- test the design
 -------------------------------------------------------------------------------

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 1bbf460d73197714ee6f4904b974c42463e2b31d..fa01d93b0dfd11a77b06eec9fea8fe634017b345 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -14,56 +14,59 @@ architecture behaviour of r_w_ram is
 
        signal ram : RAM_TYPE := (
 
-       0 => "11101101000000000000000000000000",
-       1 => "11101101001000000000000000000000",
-       2 => "11100111101000000000000000000000",
+       0 => "11101101000000000000000000000000",        --ldi
+       1 => "11101101001000000000000000000000",        --ldi
+       2 => "11100111101000000000000000000000",        --stw
        3 => "11100001000000000000000000100001",
-       4 => "11101100100000000000010000000000",
+       4 => "11101100100000000000001100000000",
        5 => "00001011011111111111111010000011",
-
-6 => x"ed080048",      --;ldi r1, 9;;
-7 => x"ed500080",      --;ldil r10, list@lo ;; global pointer
-8 => x"fd500002",      --;ldih r10, list@hi;;
-9 => x"eb000107",      --;call+ fibcall;;
-10 => x"eb7ffe03",     --;br+ main;;
-               --2; fib(n) {
-               --2;   if (list[n] > 0) {
-               --2;    return list[n]
-               --2;   }
-               --2;   a = fib(n-1)
-               --2;   list[n] = a + list[n-2]
-               --2;   return list[n]
-               --2; }
-               --3;fibcall;
-               --2;update counter for aligned access
-11 => x"e5088800",     --;lls r1, r1, 2 ;; *4
-               --2;calculate adress of top element
-12 => x"e0150800",     --;add r2, r10, r1;;
-               --3;fibmem;
-               --2;load top element
-13 => x"e7010000",     --;ldw r0, 0(r2);;
-               --2;compare if set
-14 => x"ec800000",     --;cmpi r0, 0;;
-               --2;return if set
-15 => x"0b000008",     --;retnz-;;
-               --2;decrement adress for next lopp
-16 => x"e1910020",     --;subi r2, r2, 4;;
-               --2;iterative call for n-1 element
-17 => x"eb7ffe07",     --;call+ fibmem;;
-               --2;load n-2 element
-18 => x"e7197ffc",     --;ldw r3, 0-4(r2);;
-               --2;add n-1 and n-2 element
-19 => x"e0018000",     --;add r0, r3, r0;;
-               --2;increment address for n element
-               --2;is needed because after return
-               --2;we need r2 to be set to the address
-               --2;of element n
-20 => x"e1110020",     --;addi r2, r2, 4;;
-               --2;store fib n
-21 => x"e7810000",     --;stw r0, 0(r2);;
-22 => x"eb00000a",     --;ret+;;
-
-                                  
+       6 => "11101101000000000000000000001000",
+       7 => "11100111100000000000000000001111",
+       8 => "11100111100000000000000000010011",
+
+       9 => x"ed080048",       --;ldi r1, 9;;
+       10 => x"ed500080",      --;ldil r10, list@lo ;; global pointer
+       11 => x"fd500002",      --;ldih r10, list@hi;;
+       12 => x"eb000107",      --;call+ fibcall;;
+       --13 => x"eb7ffe03",    --;br+ main;;
+       13 => "11101011000000000000000000000010",       -- endless loop --2; fib(n) {
+                       --2;   if (list[n] > 0) {
+                       --2;    return list[n]
+                       --2;   }
+                       --2;   a = fib(n-1)
+                       --2;   list[n] = a + list[n-2]
+                       --2;   return list[n]
+                       --2; }
+                       --3;fibcall;
+                       --2;update counter for aligned access
+       14 => x"e5088800",      --;lls r1, r1, 2 ;; *4
+                       --2;calculate adress of top element
+       15 => x"e0150800",      --;add r2, r10, r1;;
+                       --3;fibmem;
+                       --2;load top element
+       16 => x"e7010000",      --;ldw r0, 0(r2);;
+                       --2;compare if set
+       17 => x"ec800000",      --;cmpi r0, 0;;
+                       --2;return if set
+       18 => x"0b000008",      --;retnz-;;
+                       --2;decrement adress for next lopp
+       19 => x"e1910020",      --;subi r2, r2, 4;;
+                       --2;iterative call for n-1 element
+       20 => x"eb7ffe07",      --;call+ fibmem;;
+                       --2;load n-2 element
+       21 => x"e7197ffc",      --;ldw r3, 0-4(r2);;
+                       --2;add n-1 and n-2 element
+       22 => x"e0018000",      --;add r0, r3, r0;;
+                       --2;increment address for n element
+                       --2;is needed because after return
+                       --2;we need r2 to be set to the address
+                       --2;of element n
+       23 => x"e1110020",      --;addi r2, r2, 4;;
+                       --2;store fib n
+       24 => x"e7810000",      --;stw r0, 0(r2);;
+       25 => x"eb00000a",      --;ret+;;
+
+-- 1 1 2 3 5 8 13 21 34        55                         
 
 
                                  others => x"F0000000");