set_location_assignment PIN_L1 -to sys_clk
set_location_assignment PIN_R22 -to sys_res
set_location_assignment PIN_G12 -to bus_tx
-
- set_location_assignment PIN_J2 -to sseg0[0]\r
- set_location_assignment PIN_J1 -to sseg0[1]\r
- set_location_assignment PIN_H2 -to sseg0[2]\r
- set_location_assignment PIN_H1 -to sseg0[3]\r
- set_location_assignment PIN_F2 -to sseg0[4]\r
- set_location_assignment PIN_F1 -to sseg0[5]\r
- set_location_assignment PIN_E2 -to sseg0[6]\r
-\r
- set_location_assignment PIN_E1 -to sseg1[0]\r
- set_location_assignment PIN_H6 -to sseg1[1]\r
- set_location_assignment PIN_H5 -to sseg1[2]\r
- set_location_assignment PIN_H4 -to sseg1[3]\r
- set_location_assignment PIN_G3 -to sseg1[4]\r
- set_location_assignment PIN_D2 -to sseg1[5]\r
- set_location_assignment PIN_D1 -to sseg1[6]\r
-\r
- set_location_assignment PIN_G5 -to sseg2[0]\r
- set_location_assignment PIN_G6 -to sseg2[1]\r
- set_location_assignment PIN_C2 -to sseg2[2]\r
- set_location_assignment PIN_C1 -to sseg2[3]\r
- set_location_assignment PIN_E3 -to sseg2[4]\r
- set_location_assignment PIN_E4 -to sseg2[5]\r
- set_location_assignment PIN_D3 -to sseg2[6]\r
-\r
- set_location_assignment PIN_F4 -to sseg3[0]\r
- set_location_assignment PIN_D5 -to sseg3[1]\r
- set_location_assignment PIN_D6 -to sseg3[2]\r
- set_location_assignment PIN_J4 -to sseg3[3]\r
- set_location_assignment PIN_L8 -to sseg3[4]\r
- set_location_assignment PIN_F3 -to sseg3[5]\r
- set_location_assignment PIN_D4 -to sseg3[6]\r
+ set_location_assignment PIN_F14 -to bus_rx
+
+ set_location_assignment PIN_J2 -to sseg0[0]
+ set_location_assignment PIN_J1 -to sseg0[1]
+ set_location_assignment PIN_H2 -to sseg0[2]
+ set_location_assignment PIN_H1 -to sseg0[3]
+ set_location_assignment PIN_F2 -to sseg0[4]
+ set_location_assignment PIN_F1 -to sseg0[5]
+ set_location_assignment PIN_E2 -to sseg0[6]
+
+ set_location_assignment PIN_E1 -to sseg1[0]
+ set_location_assignment PIN_H6 -to sseg1[1]
+ set_location_assignment PIN_H5 -to sseg1[2]
+ set_location_assignment PIN_H4 -to sseg1[3]
+ set_location_assignment PIN_G3 -to sseg1[4]
+ set_location_assignment PIN_D2 -to sseg1[5]
+ set_location_assignment PIN_D1 -to sseg1[6]
+
+ set_location_assignment PIN_G5 -to sseg2[0]
+ set_location_assignment PIN_G6 -to sseg2[1]
+ set_location_assignment PIN_C2 -to sseg2[2]
+ set_location_assignment PIN_C1 -to sseg2[3]
+ set_location_assignment PIN_E3 -to sseg2[4]
+ set_location_assignment PIN_E4 -to sseg2[5]
+ set_location_assignment PIN_D3 -to sseg2[6]
+
+ set_location_assignment PIN_F4 -to sseg3[0]
+ set_location_assignment PIN_D5 -to sseg3[1]
+ set_location_assignment PIN_D6 -to sseg3[2]
+ set_location_assignment PIN_J4 -to sseg3[3]
+ set_location_assignment PIN_L8 -to sseg3[4]
+ set_location_assignment PIN_F3 -to sseg3[5]
+ set_location_assignment PIN_D4 -to sseg3[6]
set_global_assignment -name FMAX_REQUIREMENT "80.00 MHz" -section_id sys_clk
add wave -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
add wave -radix hexadecimal /pipeline_tb/writeback_st/dmem_we
add wave -radix hexadecimal /pipeline_tb/writeback_st/data_addr
+
+add wave -radix hexadecimal /pipeline_tb/tx_pin
+add wave -radix hexadecimal /pipeline_tb/rx_pin
+
add wave -radix decimal /pipeline_tb/cycle_cnt
run 10000 ns
jump : out std_logic;
-- same here
bus_tx : out std_logic;
+ bus_rx : in std_logic;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
-- reg_wr_data : out gp_register_t
-- uart
bus_tx : out std_logic;
+ bus_rx : in std_logic;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
generic map('0', '1')
port map(sys_clk, sys_res, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
syn: process(sys_clk, sys_res)
instr_s.reg_src1_addr := instruction(18 downto 15); -- mem addr
instr_s.displacement(14 downto 0) := instruction(14 downto 0);
instr_s.op_detail(NO_PSW_OPT) := '1';
- instr_s.op_detail(ST_OPT) := '1';
+ instr_s.op_detail(ST_OPT) := '1';
instr_s.op_group := LDST_OP;
if (instr_s.displacement(14) = '1') then
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
---use work.math_pkg.all;\r
-use work.common_pkg.all;\r
-use work.core_pkg.all;\r
-\r
-use work.mem_pkg.all;\r
-use work.extension_pkg.all;\r
-use work.extension_7seg_pkg.all;\r
-\r
-architecture behav of extension_7seg is\r
-\r
-signal s_state, s_state_nxt : sseg_state_rec;\r
-signal ext_reg_r : extmod_rec;\r
-\r
-begin\r
-\r
-seg_syn: process(sys_clk, sys_res_n)\r
-\r
-begin\r
-\r
- if (sys_res_n = RESET_VALUE) then\r
- \r
- s_state.digit0 <= (others => '0');--set(0,7);\r
- s_state.digit1 <= (others => '0');--set(0,7);\r
- s_state.digit2 <= (others => '0');--set(0,7);\r
- s_state.digit3 <= (others => '0');--set(0,7);\r
-\r
- ext_reg_r.sel <='0';\r
- ext_reg_r.wr_en <= '0';\r
- ext_reg_r.byte_en <= (others => '0');\r
- ext_reg_r.data <= (others => '0');\r
- ext_reg_r.addr <= (others => '0');\r
- \r
- elsif rising_edge(sys_clk) then\r
- \r
- s_state <= s_state_nxt;\r
- ext_reg_r <= ext_reg;\r
- \r
- end if;\r
- \r
-end process; \r
-\r
-seg_asyn: process(s_state, ext_reg_r) \r
-\r
-begin\r
- s_state_nxt <= s_state; \r
-\r
- if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then\r
-\r
-\r
- case ext_reg_r.byte_en(1 downto 0) is\r
- when "00" => null;\r
- s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));\r
- s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));\r
- s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));\r
- s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));\r
- when others => \r
- s_state_nxt.digit0 <= (others => '1');\r
- s_state_nxt.digit1 <= (others => '1');\r
- s_state_nxt.digit2 <= (others => '1');\r
- s_state_nxt.digit3 <= (others => '1');\r
- end case;\r
-\r
-\r
- end if;\r
-\r
-end process; --ps2_next\r
-\r
-seg_out: process(s_state)\r
-begin\r
- \r
- o_digit0 <= not(s_state.digit0);\r
- o_digit1 <= not(s_state.digit1);\r
- o_digit2 <= not(s_state.digit2);\r
- o_digit3 <= not(s_state.digit3);\r
-\r
-end process;\r
-\r
-end behav;\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--use work.math_pkg.all;
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+use work.mem_pkg.all;
+use work.extension_pkg.all;
+use work.extension_7seg_pkg.all;
+
+architecture behav of extension_7seg is
+
+signal s_state, s_state_nxt : sseg_state_rec;
+signal ext_reg_r : extmod_rec;
+
+begin
+
+seg_syn: process(sys_clk, sys_res_n)
+
+begin
+
+ if (sys_res_n = RESET_VALUE) then
+
+ s_state.digit0 <= (others => '0');--set(0,7);
+ s_state.digit1 <= (others => '0');--set(0,7);
+ s_state.digit2 <= (others => '0');--set(0,7);
+ s_state.digit3 <= (others => '0');--set(0,7);
+
+ ext_reg_r.sel <='0';
+ ext_reg_r.wr_en <= '0';
+ ext_reg_r.byte_en <= (others => '0');
+ ext_reg_r.data <= (others => '0');
+ ext_reg_r.addr <= (others => '0');
+
+ elsif rising_edge(sys_clk) then
+
+ s_state <= s_state_nxt;
+ ext_reg_r <= ext_reg;
+
+ end if;
+
+end process;
+
+seg_asyn: process(s_state, ext_reg_r)
+
+begin
+ s_state_nxt <= s_state;
+
+ if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then
+
+
+-- case ext_reg_r.byte_en(1 downto 0) is
+-- when "00" => null;
+-- s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
+-- s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
+-- s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
+-- s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
+-- when others =>
+-- s_state_nxt.digit0 <= (others => '1');
+-- s_state_nxt.digit1 <= (others => '1');
+-- s_state_nxt.digit2 <= (others => '1');
+-- s_state_nxt.digit3 <= (others => '1');
+-- end case;
+
+ if (ext_reg_r.byte_en(0) = '1') then
+ s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
+ s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
+ end if;
+ if (ext_reg_r.byte_en(1) = '1') then
+ s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
+ s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
+ end if;
+
+ end if;
+
+end process; --ps2_next
+
+seg_out: process(s_state)
+begin
+
+ o_digit0 <= not(s_state.digit0);
+ o_digit1 <= not(s_state.digit1);
+ o_digit2 <= not(s_state.digit2);
+ o_digit3 <= not(s_state.digit3);
+
+end process;
+
+end behav;
rs232_rx_inst : rs232_rx
generic map(
- RESET_VALUE
+ RESET_VALUE,
+ 2
)
port map(
--System inputs
component rs232_rx is
generic (
-- active reset value
- RESET_VALUE : std_logic
+ RESET_VALUE : std_logic;
+ SYNC_STAGES : integer range 2 to integer'high
);
port(
sys_res_n : in std_logic;
--Bus
- bus_rx : in std_logic;
+ bus_rx_unsync : in std_logic;
--To sendlogic
new_rx_data : out std_logic;
-------------------------------------------------------------------------------
architecture behavior of pipeline_tb is
- constant cc : time := 30 ns; -- test clock period
-
+ constant cc : time := 20 ns; -- test clock period
+ constant SYS_CLOCK_FREQ : integer := 50000000;
+ constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
+
signal sys_clk_pin : std_logic;
signal sys_res_n_pin : std_logic;
--Data input
signal dmem_pin : std_logic;--memop
signal dmem_wr_en_pin : std_logic;
signal hword_pin : std_logic;
- signal byte_s_pin, tx_pin : std_logic;
+ signal byte_s_pin, tx_pin, rx_pin : std_logic;
signal gpm_in_pin : extmod_rec;
signal gpm_out_pin : gp_register_t;
generic map('0', '1')
port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, sseg0, sseg1, sseg2, sseg3);
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3);
wait until sys_clk_pin = '1' and sys_clk_pin'event;
end loop;
end;
+
+ procedure txd(trans_data : in std_logic_vector) is
+ begin
+ for i in 0 to 9 loop
+ rx_pin <= trans_data(i);
+ dummy <= not dummy;
+ wait on dummy;
+ icwait(BAUD_COUNT);
+ end loop;
+ end txd;
+
begin
-----------------------------------------------------------------------------
sys_res_n_pin <= '1';
wait until sys_res_n_pin = '1';
+ icwait(10);
+
+ txd("0100000101");
icwait(1000000000);
case rrrr_addr(10 downto 0) is
- when "00000000000" => data_out <= "11101101000000000000000000000000"; --
- when "00000000001" => data_out <= "11101101001000000000000000000000"; --
- when "00000000010" => data_out <= "11100111101000000000000000000000"; --
-
- when "00000000011" => data_out <= "11100001000000000000000000100001"; --
- when "00000000100" => data_out <= "11101100100000000000001100000000"; --
- when "00000000101" => data_out <= "00001011011111111111111010000011"; --
-
- when "00000000110" => data_out <= "11101101000000000000000000001000"; --
- when "00000000111" => data_out <= "11100111100000000000000000001111"; --
- when "00000001000" => data_out <= "11100111100000000000000000010011"; -- --
-
-
- when "00000001001" => data_out <= x"ed080080"; --x"ed080048"; --
- when "00000001010" => data_out <= x"ed500080"; --
- when "00000001011" => data_out <= x"fd500002"; --
- when "00000001100" => data_out <= x"eb000107";
- when "00000001101" => data_out <= "11101011000000000000011010000010"; --"11101011000000000000000000000010";
-
- when "00000001110" => data_out <= x"e5088800";
- when "00000001111" => data_out <= x"e0150800";
- when "00000010000" => data_out <= x"e7010000";
- when "00000010001" => data_out <= x"ec800000";
- when "00000010010" => data_out <= x"0b000008";
- when "00000010011" => data_out <= x"e1910020";
- when "00000010100" => data_out <= x"eb7ffe07";
- when "00000010101" => data_out <= x"e7197ffc";
- when "00000010110" => data_out <= x"e0018000";
-
- when "00000010111" => data_out <= x"e1110020";
- when "00000011000" => data_out <= x"e7810000";
- when "00000011001" => data_out <= x"eb00000a";
-
-
- when "00000011010" => data_out <= x"ed290080";
- when "00000011011" => data_out <= x"e1080000";
+ -- fibonacci
+-- when "00000000000" => data_out <= "11101101000000000000000000000000"; --
+-- when "00000000001" => data_out <= "11101101001000000000000000000000"; --
+-- when "00000000010" => data_out <= "11100111101000000000000000000000"; --
+--
+-- when "00000000011" => data_out <= "11100001000000000000000000100001"; --
+-- when "00000000100" => data_out <= "11101100100000000000001100000000"; --
+-- when "00000000101" => data_out <= "00001011011111111111111010000011"; --
+--
+-- when "00000000110" => data_out <= "11101101000000000000000000001000"; --
+-- when "00000000111" => data_out <= "11100111100000000000000000001111"; --
+-- when "00000001000" => data_out <= "11100111100000000000000000010011"; -- --
+--
+--
+-- when "00000001001" => data_out <= x"ed080048"; --x"ed080048"; --
+-- when "00000001010" => data_out <= x"ed500080"; --
+-- when "00000001011" => data_out <= x"fd500002"; --
+-- when "00000001100" => data_out <= x"eb000107";
+-- when "00000001101" => data_out <= "11101011000000000000011010000010"; --"11101011000000000000000000000010";
+--
+-- when "00000001110" => data_out <= x"e5088800";
+-- when "00000001111" => data_out <= x"e0150800";
+-- when "00000010000" => data_out <= x"e7010000";
+-- when "00000010001" => data_out <= x"ec800000";
+-- when "00000010010" => data_out <= x"0b000008";
+-- when "00000010011" => data_out <= x"e1910020";
+-- when "00000010100" => data_out <= x"eb7ffe07";
+-- when "00000010101" => data_out <= x"e7197ffc";
+-- when "00000010110" => data_out <= x"e0018000";
+--
+-- when "00000010111" => data_out <= x"e1110020";
+-- when "00000011000" => data_out <= x"e7810000";
+-- when "00000011001" => data_out <= x"eb00000a";
+--
+--
+-- when "00000011010" => data_out <= x"ed290080";
+-- when "00000011011" => data_out <= x"e1080000";
+--
+-- when "00000011100" => data_out <= x"e78a8000";
+--
+-- when "00000011101" => data_out <= x"ed510058";
+-- when "00000011110" => data_out <= x"e7850000";
+--
+ -- uart echo
+
+ when "00000000000" => data_out <= x"ed010058";
+ when "00000000001" => data_out <= x"ed090060";
+ when "00000000010" => data_out <= x"e7188000";
+ when "00000000011" => data_out <= x"ec1a0000";
+ when "00000000100" => data_out <= x"1b7ffe01";
+ when "00000000101" => data_out <= x"e7980000";
+ when "00000000110" => data_out <= x"e1218000";
+ when "00000000111" => data_out <= x"eb7ffc81";
- when "00000011100" => data_out <= x"e78a8000";
when others => data_out <= "11101011000000000000000000000010";
entity rs232_rx is
generic (
-- active reset value
- RESET_VALUE : std_logic
+ RESET_VALUE : std_logic;
+ SYNC_STAGES : integer range 2 to integer'high
);
port(
sys_res_n : in std_logic;
--Bus
- bus_rx : in std_logic;
+ bus_rx_unsync : in std_logic;
--To sendlogic
new_rx_data : out std_logic;
signal cnt, cnt_next : integer := 0;
signal baud_cnt, baud_cnt_next : std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
signal rx_data_int, rx_data_nxt, rx_data_res_int, rx_data_res_nxt : uart_data;
+ signal sync : std_logic_vector(1 to SYNC_STAGES);
+ signal bus_rx : std_logic;
begin
-- syncronisierungs Prozess
cnt <= 0;
rx_data_res_int <= x"00";
baud_cnt <= (others => '0');
+ sync <= (others => '1');
elsif rising_edge(sys_clk) then
-- sync Zustand, uebernehmen der next-Signale
rx_data_res_int <= rx_data_res_nxt;
new_rx_data <= new_rx_data_nxt;
+ sync(1) <= bus_rx_unsync;
+ for i in 2 to SYNC_STAGES loop
+ sync(i) <= sync(i - 1);
+ end loop;
+
end if;
end process;
-- setzen des Ausgangsignals, Rxt-Daten
rx_data <= rx_data_res_int;
+ bus_rx <= sync(SYNC_STAGES);
-- Zustandsmaschienen Prozess
rs232_states : process(sys_clk,state,cnt, bus_rx, bus_rx_last, baud_cnt,bus_rx_int,bd_rate)
jump : out std_logic;
-- hallo stefan mir adden da jetzt mal schnell an uart port :D
bus_tx : out std_logic;
+ bus_rx : in std_logic;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
signal ext_uart,ext_timer,ext_gpmp,ext_7seg : extmod_rec;
signal ext_uart_out, ext_timer_out, ext_gpmp_out : gp_register_t;
-signal sel_nxt, dmem_we, bus_rx, ext_anysel : std_logic;
+signal sel_nxt, dmem_we, ext_anysel : std_logic;
signal calc_mem_res : gp_register_t;
wb_reg.dmem_write_en <= '0';
wb_reg.hword <= '0';
wb_reg.byte_s <= '0';
- bus_rx <= '1';
wb_reg.byte_en <= (others => '0');
wb_reg.data <= (others =>'0');
elsif rising_edge(clk) then
wb_reg <= wb_reg_nxt;
- bus_rx <= '1';
end if;
end process;
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result, hword, byte_s)
variable reg_we_v : std_logic;
variable data_out : gp_register_t;
begin
data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
end if;
- data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
+
+ if wb_reg.hword = '1' or wb_reg.byte_s = '1' then
+ if wb_reg.address(1)='1' then
+ data_out(hword_t'range) := data_out(data_out'high downto (data_out'length/2));
+ end if;
+ data_out(data_out'high downto (data_out'length/2)) := (others => '0');
+ if byte_s = '1' then
+ if wb_reg.address(0) = '1' then
+ data_out(byte_t'range) := data_out(hword_t'high downto (hword_t'length/2));
+ end if;
+ data_out(hword_t'high downto (hword_t'length/2)) := (others => '0');
+ end if;
+ end if;
+
+
+-- data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
when EXT_UART_ADDR =>
ext_uart.sel <= enable;
ext_anysel <= enable;
+
-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
-- ext_uart.data <= ram_data;
-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
when EXT_7SEG_ADDR =>
ext_7seg.sel <= enable;
ext_anysel <= enable;
+
-- ext_7seg.wr_en <= wb_regdmem_write_en;
-- ext_7seg.data <= ram_data;
-- ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
Assembler report for dt
-Fri Dec 17 12:27:16 2010
+Sun Dec 19 20:36:48 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Fri Dec 17 12:27:16 2010 ;
+; Assembler Status ; Successful - Sun Dec 19 20:36:48 2010 ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
+----------------+-----------------+
; Device ; EP1C12Q240C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x001EAC07 ;
+; Checksum ; 0x002A3659 ;
+----------------+-----------------+
+--------------------+-------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x03AFD4AC ;
+; Checksum ; 0x03B3DAC6 ;
; Compression Ratio ; 1 ;
+--------------------+-------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 12:27:13 2010
+ Info: Processing started: Sun Dec 19 20:36:47 2010
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dt -c dt
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 230 megabytes
- Info: Processing ended: Fri Dec 17 12:27:16 2010
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:02
+ Info: Processing ended: Sun Dec 19 20:36:48 2010
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
-Fri Dec 17 12:27:19 2010
+Sun Dec 19 20:36:51 2010
Fitter report for dt
-Fri Dec 17 12:27:10 2010
+Sun Dec 19 20:36:44 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
-; Fitter Status ; Successful - Fri Dec 17 12:27:10 2010 ;
+; Fitter Status ; Successful - Sun Dec 19 20:36:44 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
-; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
-; Total pins ; 3 / 173 ( 2 % ) ;
+; Total logic elements ; 1,646 / 12,060 ( 14 % ) ;
+; Total pins ; 32 / 173 ( 18 % ) ;
; Total virtual pins ; 0 ;
-; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+; Total memory bits ; 66,560 / 239,616 ( 28 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-----------------------+-----------------------------------------------+
; Type ; Value ;
+---------------------+------------------------+
; Placement (by node) ; ;
-; -- Requested ; 0 / 1127 ( 0.00 % ) ;
-; -- Achieved ; 0 / 1127 ( 0.00 % ) ;
+; -- Requested ; 0 / 1777 ( 0.00 % ) ;
+; -- Achieved ; 0 / 1777 ( 0.00 % ) ;
; ; ;
; Routing (by net) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
-; Top ; 1125 ; 0 ; N/A ; Source File ;
+; Top ; 1775 ; 0 ; N/A ; Source File ;
; hard_block:auto_generated_inst ; 2 ; 0 ; N/A ; Source File ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in /homes/c0726283/calu/dt/dt.pin.
-
-
-+-----------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-------------------------------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------------------------------------------+
-; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
-; -- Combinational with no register ; 843 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 215 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 473 ;
-; -- 3 input functions ; 443 ;
-; -- 2 input functions ; 123 ;
-; -- 1 input functions ; 18 ;
-; -- 0 input functions ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 852 ;
-; -- arithmetic mode ; 206 ;
-; -- qfbk mode ; 76 ;
-; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 83 ;
-; -- asynchronous clear/load mode ; 203 ;
-; ; ;
-; Total registers ; 215 / 12,567 ( 2 % ) ;
-; Total LABs ; 111 / 1,206 ( 9 % ) ;
-; Logic elements in carry chains ; 214 ;
-; User inserted logic elements ; 0 ;
-; Virtual pins ; 0 ;
-; I/O pins ; 3 / 173 ( 2 % ) ;
-; -- Clock pins ; 1 / 2 ( 50 % ) ;
-; Global signals ; 2 ;
-; M4Ks ; 2 / 52 ( 4 % ) ;
-; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
-; Total RAM block bits ; 9,216 / 239,616 ( 4 % ) ;
-; PLLs ; 0 / 2 ( 0 % ) ;
-; Global clocks ; 2 / 8 ( 25 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; ASMI Blocks ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 5% / 5% / 4% ;
-; Peak interconnect usage (total/H/V) ; 17% / 19% / 14% ;
-; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 217 ;
-; Highest non-global fan-out signal ; execute_stage:exec_st|alu:alu_inst|Selector76~0 ;
-; Highest non-global fan-out ; 114 ;
-; Total fan-out ; 4182 ;
-; Average fan-out ; 3.93 ;
-+---------------------------------------------+-------------------------------------------------+
+The pin-out file can be found in /home/stefan/processor/calu/dt/dt.pin.
+
+
++-----------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+-------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-------------------------------------------+
+; Total logic elements ; 1,646 / 12,060 ( 14 % ) ;
+; -- Combinational with no register ; 1126 ;
+; -- Register only ; 26 ;
+; -- Combinational with a register ; 494 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 827 ;
+; -- 3 input functions ; 474 ;
+; -- 2 input functions ; 292 ;
+; -- 1 input functions ; 27 ;
+; -- 0 input functions ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 1470 ;
+; -- arithmetic mode ; 176 ;
+; -- qfbk mode ; 179 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 246 ;
+; -- asynchronous clear/load mode ; 492 ;
+; ; ;
+; Total registers ; 520 / 12,567 ( 4 % ) ;
+; Total LABs ; 174 / 1,206 ( 14 % ) ;
+; Logic elements in carry chains ; 184 ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 32 / 173 ( 18 % ) ;
+; -- Clock pins ; 1 / 2 ( 50 % ) ;
+; Global signals ; 2 ;
+; M4Ks ; 18 / 52 ( 35 % ) ;
+; Total memory bits ; 66,560 / 239,616 ( 28 % ) ;
+; Total RAM block bits ; 82,944 / 239,616 ( 35 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI Blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 12% / 12% / 11% ;
+; Peak interconnect usage (total/H/V) ; 42% / 44% / 40% ;
+; Maximum fan-out node ; sys_clk ;
+; Maximum fan-out ; 538 ;
+; Highest non-global fan-out signal ; execute_stage:exec_st|right_operand[0]~19 ;
+; Highest non-global fan-out ; 104 ;
+; Total fan-out ; 7140 ;
+; Average fan-out ; 4.20 ;
++---------------------------------------------+-------------------------------------------+
+---------------------------------------------------------------------------------------------------+
+---------------------------------------------+--------------------+--------------------------------+
; Difficulty Clustering Region ; Low ; Low ;
; ; ; ;
-; Total logic elements ; 1058 ; 0 ;
-; -- Combinational with no register ; 843 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 215 ; 0 ;
+; Total logic elements ; 1646 ; 0 ;
+; -- Combinational with no register ; 1126 ; 0 ;
+; -- Register only ; 26 ; 0 ;
+; -- Combinational with a register ; 494 ; 0 ;
; ; ; ;
; Logic element usage by number of LUT inputs ; ; ;
; -- 4 input functions ; 0 ; 0 ;
; -- synchronous clear/load mode ; 0 ; 0 ;
; -- asynchronous clear/load mode ; 0 ; 0 ;
; ; ; ;
-; Total registers ; 215 / 6030 ( 3 % ) ; 0 / 6030 ( 0 % ) ;
+; Total registers ; 520 / 6030 ( 8 % ) ; 0 / 6030 ( 0 % ) ;
; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 3 ; 0 ;
+; I/O pins ; 32 ; 0 ;
; DSP block 9-bit elements ; 0 ; 0 ;
-; Total memory bits ; 512 ; 0 ;
-; Total RAM block bits ; 9216 ; 0 ;
-; M4K ; 2 / 52 ( 3 % ) ; 0 / 52 ( 0 % ) ;
+; Total memory bits ; 66560 ; 0 ;
+; Total RAM block bits ; 82944 ; 0 ;
+; M4K ; 18 / 52 ( 34 % ) ; 0 / 52 ( 0 % ) ;
; ; ; ;
; Connections ; ; ;
; -- Input Connections ; 0 ; 0 ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
-; -- Total Connections ; 4355 ; 0 ;
-; -- Registered Connections ; 809 ; 0 ;
+; -- Total Connections ; 7455 ; 0 ;
+; -- Registered Connections ; 1762 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 0 ; 0 ;
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
; ; ; ;
; Partition Interface ; ; ;
-; -- Input Ports ; 2 ; 0 ;
-; -- Output Ports ; 1 ; 0 ;
+; -- Input Ports ; 3 ; 0 ;
+; -- Output Ports ; 29 ; 0 ;
; -- Bidir Ports ; 0 ; 0 ;
; ; ; ;
; Registered Ports ; ; ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 217 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
-; sys_res ; 42 ; 1 ; 0 ; 6 ; 0 ; 205 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+; bus_rx ; 17 ; 1 ; 0 ; 21 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; Fitter ;
+; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 538 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+; sys_res ; 42 ; 1 ; 0 ; 6 ; 0 ; 504 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
-+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-; bus_tx ; 166 ; 3 ; 53 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 10 pF ; - ; - ;
-+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
+; bus_tx ; 166 ; 3 ; 53 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 10 pF ; - ; - ;
+; sseg0[0] ; 83 ; 4 ; 14 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[1] ; 86 ; 4 ; 16 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[2] ; 144 ; 3 ; 53 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[3] ; 39 ; 1 ; 0 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[4] ; 213 ; 2 ; 18 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[5] ; 88 ; 4 ; 18 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[6] ; 214 ; 2 ; 16 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[0] ; 18 ; 1 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[1] ; 93 ; 4 ; 26 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[2] ; 94 ; 4 ; 28 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[3] ; 162 ; 3 ; 53 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[4] ; 207 ; 2 ; 28 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[5] ; 206 ; 2 ; 28 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[6] ; 95 ; 4 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[0] ; 21 ; 1 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[1] ; 201 ; 2 ; 32 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[2] ; 161 ; 3 ; 53 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[3] ; 202 ; 2 ; 32 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[4] ; 20 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[5] ; 200 ; 2 ; 32 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[6] ; 160 ; 3 ; 53 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[0] ; 87 ; 4 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[1] ; 84 ; 4 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[2] ; 38 ; 1 ; 0 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[3] ; 23 ; 1 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[4] ; 85 ; 4 ; 16 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[5] ; 215 ; 2 ; 16 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[6] ; 216 ; 2 ; 16 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-+----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+----------------+---------------+--------------+
-; 1 ; 3 / 44 ( 7 % ) ; 3.3V ; -- ;
-; 2 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
-; 3 ; 2 / 45 ( 4 % ) ; 3.3V ; -- ;
-; 4 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
-+----------+----------------+---------------+--------------+
++------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1 ; 10 / 44 ( 23 % ) ; 3.3V ; -- ;
+; 2 ; 9 / 42 ( 21 % ) ; 3.3V ; -- ;
+; 3 ; 6 / 45 ( 13 % ) ; 3.3V ; -- ;
+; 4 ; 9 / 42 ( 21 % ) ; 3.3V ; -- ;
++----------+------------------+---------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 14 ; 11 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 15 ; 12 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 13 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 17 ; 14 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 18 ; 15 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 17 ; 14 ; 1 ; bus_rx ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 18 ; 15 ; 1 ; sseg1[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 19 ; 16 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 20 ; 17 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 21 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 20 ; 17 ; 1 ; sseg2[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 21 ; 18 ; 1 ; sseg2[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 23 ; 28 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 23 ; 28 ; 1 ; sseg3[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 24 ; 29 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;
; 25 ; 30 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 26 ; 31 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; 35 ; 37 ; 1 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 36 ; 38 ; 1 ; ^DCLK ; bidir ; ; ; -- ; ; -- ; -- ;
; 37 ; 39 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;
-; 38 ; 40 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 39 ; 41 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 38 ; 40 ; 1 ; sseg3[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 39 ; 41 ; 1 ; sseg0[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 40 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 41 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; 53 ; 1 ; sys_res ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 80 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 81 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 82 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 83 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 84 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 85 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 86 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 87 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 83 ; 87 ; 4 ; sseg0[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 84 ; 88 ; 4 ; sseg3[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 85 ; 89 ; 4 ; sseg3[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 86 ; 90 ; 4 ; sseg0[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 87 ; 91 ; 4 ; sseg3[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 88 ; 92 ; 4 ; sseg0[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 89 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 90 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 91 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 92 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 93 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 94 ; 103 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 95 ; 104 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 93 ; 100 ; 4 ; sseg1[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 94 ; 103 ; 4 ; sseg1[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 95 ; 104 ; 4 ; sseg1[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 96 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 97 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 98 ; 106 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 141 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 142 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 143 ; 160 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 144 ; 161 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 144 ; 161 ; 3 ; sseg0[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 145 ; 162 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
; 146 ; 163 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
; 147 ; 164 ; 3 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 157 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 158 ; 180 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 159 ; 181 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 160 ; 182 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 161 ; 183 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 162 ; 184 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 160 ; 182 ; 3 ; sseg2[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 161 ; 183 ; 3 ; sseg2[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 162 ; 184 ; 3 ; sseg1[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 163 ; 185 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 164 ; 186 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 165 ; 187 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 197 ; 213 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 198 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 199 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 200 ; 222 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 201 ; 223 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 202 ; 224 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 222 ; 2 ; sseg2[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 201 ; 223 ; 2 ; sseg2[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 202 ; 224 ; 2 ; sseg2[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 203 ; 225 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 205 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 206 ; 227 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 207 ; 228 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 227 ; 2 ; sseg1[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 207 ; 228 ; 2 ; sseg1[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 208 ; 231 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 209 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 210 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 211 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 212 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 213 ; 239 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 214 ; 240 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 215 ; 241 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 216 ; 242 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 213 ; 239 ; 2 ; sseg0[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 214 ; 240 ; 2 ; sseg0[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 215 ; 241 ; 2 ; sseg3[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 216 ; 242 ; 2 ; sseg3[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 217 ; 243 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 218 ; 244 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 219 ; 245 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1058 (1) ; 215 ; 512 ; 2 ; 3 ; 0 ; 843 (1) ; 0 (0) ; 215 (0) ; 214 (0) ; 76 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 100 (94) ; 72 ; 512 ; 2 ; 0 ; 0 ; 28 (22) ; 0 (0) ; 72 (72) ; 11 (11) ; 5 (5) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
-; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
-; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
-; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 761 (146) ; 67 ; 0 ; 0 ; 0 ; 0 ; 694 (110) ; 0 (0) ; 67 (36) ; 171 (0) ; 70 (39) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 550 (228) ; 0 ; 0 ; 0 ; 0 ; 0 ; 550 (228) ; 0 (0) ; 0 (0) ; 141 (43) ; 31 (31) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:or_inst| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
-; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
-; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 31 (31) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
-; |fetch_stage:fetch_st| ; 33 (24) ; 17 ; 0 ; 0 ; 0 ; 0 ; 16 (13) ; 0 (0) ; 17 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 163 (48) ; 59 ; 0 ; 0 ; 0 ; 0 ; 104 (44) ; 0 (0) ; 59 (4) ; 32 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_uart:uart| ; 106 (12) ; 49 ; 0 ; 0 ; 0 ; 0 ; 57 (2) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
-; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
+; |core_top ; 1646 (0) ; 520 ; 66560 ; 18 ; 32 ; 0 ; 1126 (0) ; 26 (0) ; 494 (0) ; 184 (0) ; 179 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 212 (150) ; 106 ; 1024 ; 2 ; 0 ; 0 ; 106 (44) ; 0 (0) ; 106 (106) ; 11 (11) ; 3 (3) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (62) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 1024 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
+; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
+; |altsyncram:ram_rtl_2| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ; ;
+; |execute_stage:exec_st| ; 836 (137) ; 71 ; 0 ; 0 ; 0 ; 0 ; 765 (98) ; 1 (1) ; 70 (38) ; 108 (0) ; 68 (38) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 637 (324) ; 0 ; 0 ; 0 ; 0 ; 0 ; 637 (324) ; 0 (0) ; 0 (0) ; 78 (44) ; 30 (27) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 34 (34) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |exec_op:shift_inst| ; 246 (246) ; 0 ; 0 ; 0 ; 0 ; 0 ; 246 (246) ; 0 (0) ; 0 (0) ; 0 (0) ; 3 (3) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
+; |extension_gpm:gpmp_inst| ; 62 (62) ; 32 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 0 (0) ; 32 (32) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
+; |fetch_stage:fetch_st| ; 44 (23) ; 29 ; 0 ; 0 ; 0 ; 0 ; 15 (12) ; 0 (0) ; 29 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |rom:instruction_ram| ; 21 (21) ; 18 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 18 (18) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|rom:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 554 (141) ; 314 ; 65536 ; 16 ; 0 ; 0 ; 240 (77) ; 25 (0) ; 289 (64) ; 65 (0) ; 108 (106) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_7seg:sseg| ; 47 (47) ; 47 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (17) ; 30 (30) ; 0 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st|extension_7seg:sseg ; ;
+; |extension_uart:uart| ; 366 (144) ; 203 ; 0 ; 0 ; 0 ; 0 ; 163 (38) ; 8 (0) ; 195 (106) ; 65 (0) ; 1 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |rs232_rx:rs232_rx_inst| ; 158 (158) ; 73 ; 0 ; 0 ; 0 ; 0 ; 85 (85) ; 8 (8) ; 65 (65) ; 48 (48) ; 1 (1) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst ; ;
+; |rs232_tx:rs232_tx_inst| ; 64 (64) ; 24 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 24 (24) ; 17 (17) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
+; |r_w_ram:data_ram| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ; ;
+; |altsyncram_grk1:auto_generated| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ; ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-+----------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-; bus_tx ; Output ; -- ; -- ; -- ; -- ;
-; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
-; sys_res ; Input ; OFF ; ON ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-; sys_clk ; ; ;
-; sys_res ; ; ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[26] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0 ; 1 ; ON ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr_nxt[6]~3 ; 1 ; ON ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X39_Y14_N6 ; 57 ; Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X38_Y18_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X36_Y12_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
-; execute_stage:exec_st|reg.result[1]~9 ; LC_X32_Y12_N1 ; 12 ; Sync. load ; no ; -- ; -- ;
-; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK3 ;
-; writeback_stage:writeback_st|Mux9~0 ; LC_X37_Y15_N8 ; 7 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X32_Y9_N2 ; 5 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X31_Y8_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X36_Y15_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|reg_we~0 ; LC_X35_Y14_N9 ; 8 ; Write enable ; no ; -- ; -- ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
++-----------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++----------+----------+---------------+---------------+-----------------------+-----+
+; bus_tx ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[0] ; Output ; -- ; -- ; -- ; -- ;
+; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
+; sys_res ; Input ; OFF ; ON ; -- ; -- ;
+; bus_rx ; Input ; ON ; ON ; -- ; -- ;
++----------+----------+---------------+---------------+-----------------------+-----+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+; sys_clk ; ; ;
+; sys_res ; ; ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[17] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[18] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[20] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[28] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[29] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[30] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.sel ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.condition[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
+; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1 ; 1 ; ON ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[8] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[9] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[10] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[12] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[15] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[17] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[16] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[21] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[0] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr_nxt[0]~1 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|tx_rdy_int ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6]~0 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5]~2 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7]~4 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4]~6 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2]~8 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1]~10 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3]~12 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0]~14 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[4] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.wr_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; 1 ; ON ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; bus_rx ; ; ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 1 ; ON ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; decode_stage:decode_st|decoder:decoder_inst|instr_s~10 ; LC_X36_Y12_N6 ; 10 ; Sync. load ; no ; -- ; -- ;
+; decode_stage:decode_st|rtw_rec_nxt.immediate[16]~28 ; LC_X36_Y12_N1 ; 9 ; Sync. clear ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X25_Y16_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X32_Y18_N0 ; 30 ; Clock enable ; no ; -- ; -- ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; LC_X21_Y16_N1 ; 31 ; Sync. clear ; no ; -- ; -- ;
+; sys_clk ; PIN_152 ; 538 ; Clock ; yes ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 504 ; Async. clear, Async. load, Clock enable ; yes ; Global Clock ; GCLK3 ;
+; writeback_stage:writeback_st|dmem_we~0 ; LC_X22_Y14_N4 ; 16 ; Write enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6]~0 ; LC_X21_Y11_N3 ; 28 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4]~33 ; LC_X22_Y18_N2 ; 16 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; LC_X22_Y18_N9 ; 9 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[7]~0 ; LC_X22_Y18_N9 ; 9 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; LC_X21_Y19_N3 ; 51 ; Sync. load ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X29_Y8_N2 ; 6 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0]~0 ; LC_X35_Y13_N0 ; 31 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15]~0 ; LC_X30_Y13_N6 ; 32 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0]~1 ; LC_X35_Y13_N9 ; 32 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|reg_we~11 ; LC_X29_Y17_N6 ; 7 ; Write enable ; no ; -- ; -- ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+------------------------------------------------------------------------+
+---------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+---------+----------+---------+----------------------+------------------+
-; sys_clk ; PIN_152 ; 217 ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 205 ; Global Clock ; GCLK3 ;
+; sys_clk ; PIN_152 ; 538 ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 504 ; Global Clock ; GCLK3 ;
+---------+----------+---------+----------------------+------------------+
-+---------------------------------------------------------------------------------------------+
-; Non-Global High Fan-Out Signals ;
-+-----------------------------------------------------------------------------------+---------+
-; Name ; Fan-Out ;
-+-----------------------------------------------------------------------------------+---------+
-; execute_stage:exec_st|alu:alu_inst|Selector76~0 ; 114 ;
-; execute_stage:exec_st|right_operand[0]~10 ; 90 ;
-; execute_stage:exec_st|right_operand[1]~6 ; 77 ;
-; execute_stage:exec_st|right_operand[2]~4 ; 64 ;
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 57 ;
-; execute_stage:exec_st|alu:alu_inst|Selector48~0 ; 55 ;
-; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 49 ;
-; execute_stage:exec_st|right_operand[3]~8 ; 48 ;
-; decode_stage:decode_st|dec_op_inst.op_detail[2] ; 41 ;
-; execute_stage:exec_st|left_operand[19]~1 ; 41 ;
-; execute_stage:exec_st|right_operand[30]~2 ; 39 ;
-; execute_stage:exec_st|right_operand[30]~1 ; 39 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; 37 ;
-; writeback_stage:writeback_st|wb_reg.dmem_en ; 35 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 35 ;
-; writeback_stage:writeback_st|wb_reg.dmem_write_en ; 34 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|Equal0~10 ; 34 ;
-; execute_stage:exec_st|alu:alu_inst|calc~0 ; 32 ;
-; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
-; execute_stage:exec_st|reg.result[7]~12 ; 30 ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
-; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
-; writeback_stage:writeback_st|jump ; 25 ;
-; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 25 ;
-; execute_stage:exec_st|reg.result[7]~13 ; 24 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; 24 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 23 ;
-; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 20 ;
-; decode_stage:decode_st|decoder:decoder_inst|instr_s~5 ; 15 ;
-; execute_stage:exec_st|reg.result[1]~9 ; 12 ;
-; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 12 ;
-; decode_stage:decode_st|rtw_rec.imm_set ; 12 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 12 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 10 ;
-; execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|tmp_sb~0 ; 9 ;
-; execute_stage:exec_st|alu:alu_inst|Selector76~1 ; 9 ;
-; execute_stage:exec_st|left_operand[30]~46 ; 9 ;
-; execute_stage:exec_st|left_operand[29]~44 ; 9 ;
-; execute_stage:exec_st|left_operand[28]~42 ; 9 ;
-; execute_stage:exec_st|alu:alu_inst|Selector107~0 ; 9 ;
-; execute_stage:exec_st|reg.res_addr[2] ; 9 ;
-; execute_stage:exec_st|reg.result[4]~21 ; 8 ;
-; execute_stage:exec_st|reg.result[25]~14 ; 8 ;
-; execute_stage:exec_st|left_operand[27]~40 ; 8 ;
-; execute_stage:exec_st|left_operand[26]~38 ; 8 ;
-; execute_stage:exec_st|alu:alu_inst|Selector97~0 ; 8 ;
-; execute_stage:exec_st|left_operand[12]~34 ; 8 ;
-; execute_stage:exec_st|left_operand[11]~32 ; 8 ;
-; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 8 ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; 8 ;
-+-----------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter RAM Summary ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
-; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y15 ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y14 ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
++---------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++-----------------------------------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++-----------------------------------------------------------------------------------------+---------+
+; execute_stage:exec_st|right_operand[0]~19 ; 104 ;
+; execute_stage:exec_st|right_operand[1]~15 ; 98 ;
+; writeback_stage:writeback_st|wb_reg.dmem_en ; 91 ;
+; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 89 ;
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 78 ;
+; execute_stage:exec_st|right_operand[2]~13 ; 63 ;
+; execute_stage:exec_st|alu:alu_inst|Selector63~0 ; 60 ;
+; execute_stage:exec_st|left_operand[19]~3 ; 59 ;
+; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 53 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ;
+; writeback_stage:writeback_st|regfile_val[24]~50 ; 48 ;
+; execute_stage:exec_st|right_operand[3]~17 ; 48 ;
+; execute_stage:exec_st|right_operand[5]~3 ; 48 ;
+; execute_stage:exec_st|right_operand[5]~2 ; 48 ;
+; writeback_stage:writeback_st|wb_reg.address[3] ; 45 ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[23] ; 41 ;
+; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 41 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ;
+; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 34 ;
+; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ;
+; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ;
+; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ;
+; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ;
+; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ;
+; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ;
+; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ;
+; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ;
+; writeback_stage:writeback_st|data_addr[6]~4 ; 32 ;
+; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ;
+; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ;
+; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ;
+; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ;
+; execute_stage:exec_st|alu:alu_inst|calc~1 ; 32 ;
+; execute_stage:exec_st|alu:alu_inst|Selector16~2 ; 32 ;
+; execute_stage:exec_st|alu:alu_inst|Selector16~1 ; 32 ;
+; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15]~0 ; 32 ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0]~1 ; 32 ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; 31 ;
+; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0]~0 ; 31 ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
+; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[27] ; 28 ;
+; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6]~0 ; 28 ;
+; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 27 ;
+; writeback_stage:writeback_st|extension_uart:uart|gread~0 ; 27 ;
+; writeback_stage:writeback_st|regfile_val[24]~51 ; 24 ;
+; decode_stage:decode_st|decoder:decoder_inst|instr_spl.bp~0 ; 23 ;
+; decode_stage:decode_st|dec_op_inst.displacement[31] ; 23 ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[26] ; 23 ;
++-----------------------------------------------------------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 16 ; 32 ; 16 ; 32 ; 512 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y17 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 16 ; 32 ; 16 ; 32 ; 512 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y18 ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 2048 ; 32 ; 2048 ; 32 ; yes ; no ; yes ; no ; 65536 ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; 16 ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; M4K_X19_Y19, M4K_X33_Y13, M4K_X33_Y14, M4K_X33_Y16, M4K_X19_Y13, M4K_X19_Y16, M4K_X19_Y18, M4K_X19_Y11, M4K_X19_Y15, M4K_X19_Y14, M4K_X19_Y10, M4K_X33_Y11, M4K_X33_Y12, M4K_X33_Y15, M4K_X19_Y17, M4K_X19_Y12 ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
-+-----------------------------------------------------+
-; Interconnect Usage Summary ;
-+----------------------------+------------------------+
-; Interconnect Resource Type ; Usage ;
-+----------------------------+------------------------+
-; C4s ; 1,302 / 30,600 ( 4 % ) ;
-; Direct links ; 132 / 43,552 ( < 1 % ) ;
-; Global clocks ; 2 / 8 ( 25 % ) ;
-; LAB clocks ; 29 / 312 ( 9 % ) ;
-; LUT chains ; 139 / 10,854 ( 1 % ) ;
-; Local interconnects ; 1,864 / 43,552 ( 4 % ) ;
-; M4K buffers ; 64 / 1,872 ( 3 % ) ;
-; R4s ; 1,504 / 28,560 ( 5 % ) ;
-+----------------------------+------------------------+
++------------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+-------------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+-------------------------+
+; C4s ; 3,149 / 30,600 ( 10 % ) ;
+; Direct links ; 169 / 43,552 ( < 1 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; LAB clocks ; 64 / 312 ( 21 % ) ;
+; LUT chains ; 152 / 10,854 ( 1 % ) ;
+; Local interconnects ; 3,313 / 43,552 ( 8 % ) ;
+; M4K buffers ; 96 / 1,872 ( 5 % ) ;
+; R4s ; 3,533 / 28,560 ( 12 % ) ;
++----------------------------+-------------------------+
+----------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-------------------------------+
-; Number of Logic Elements (Average = 9.53) ; Number of LABs (Total = 111) ;
+; Number of Logic Elements (Average = 9.46) ; Number of LABs (Total = 174) ;
+--------------------------------------------+-------------------------------+
-; 1 ; 3 ;
-; 2 ; 2 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
+; 1 ; 4 ;
+; 2 ; 0 ;
+; 3 ; 2 ;
+; 4 ; 2 ;
+; 5 ; 1 ;
; 6 ; 0 ;
-; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 4 ;
-; 10 ; 100 ;
+; 7 ; 2 ;
+; 8 ; 7 ;
+; 9 ; 7 ;
+; 10 ; 149 ;
+--------------------------------------------+-------------------------------+
+--------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-------------------------------+
-; LAB-wide Signals (Average = 1.49) ; Number of LABs (Total = 111) ;
+; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 174) ;
+------------------------------------+-------------------------------+
-; 1 Async. clear ; 70 ;
-; 1 Async. load ; 2 ;
-; 1 Clock ; 72 ;
-; 1 Clock enable ; 14 ;
-; 1 Sync. clear ; 2 ;
+; 1 Async. clear ; 126 ;
+; 1 Async. load ; 1 ;
+; 1 Clock ; 130 ;
+; 1 Clock enable ; 39 ;
+; 1 Sync. clear ; 4 ;
; 1 Sync. load ; 5 ;
+; 2 Clock enables ; 14 ;
+------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-------------------------------+
-; Number of Signals Sourced (Average = 10.26) ; Number of LABs (Total = 111) ;
+; Number of Signals Sourced (Average = 10.30) ; Number of LABs (Total = 174) ;
+----------------------------------------------+-------------------------------+
; 0 ; 0 ;
-; 1 ; 3 ;
-; 2 ; 2 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
+; 1 ; 4 ;
+; 2 ; 0 ;
+; 3 ; 2 ;
+; 4 ; 2 ;
+; 5 ; 1 ;
; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 5 ;
-; 10 ; 60 ;
-; 11 ; 19 ;
-; 12 ; 13 ;
-; 13 ; 4 ;
+; 7 ; 2 ;
+; 8 ; 5 ;
+; 9 ; 7 ;
+; 10 ; 87 ;
+; 11 ; 30 ;
+; 12 ; 16 ;
+; 13 ; 6 ;
; 14 ; 5 ;
+; 15 ; 3 ;
+; 16 ; 1 ;
+; 17 ; 3 ;
+----------------------------------------------+-------------------------------+
+---------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-------------------------------+
-; Number of Signals Sourced Out (Average = 6.93) ; Number of LABs (Total = 111) ;
+; Number of Signals Sourced Out (Average = 7.25) ; Number of LABs (Total = 174) ;
+-------------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
-; 2 ; 2 ;
-; 3 ; 8 ;
-; 4 ; 5 ;
-; 5 ; 11 ;
-; 6 ; 19 ;
-; 7 ; 13 ;
-; 8 ; 15 ;
-; 9 ; 11 ;
-; 10 ; 19 ;
-; 11 ; 2 ;
+; 2 ; 1 ;
+; 3 ; 5 ;
+; 4 ; 9 ;
+; 5 ; 18 ;
+; 6 ; 26 ;
+; 7 ; 33 ;
+; 8 ; 30 ;
+; 9 ; 19 ;
+; 10 ; 21 ;
+; 11 ; 3 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 1 ;
+; 15 ; 1 ;
+; 16 ; 2 ;
+-------------------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+-------------------------------+
-; Number of Distinct Inputs (Average = 16.28) ; Number of LABs (Total = 111) ;
+; Number of Distinct Inputs (Average = 16.75) ; Number of LABs (Total = 174) ;
+----------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
+; 3 ; 3 ;
+; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 2 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 2 ;
-; 10 ; 4 ;
-; 11 ; 8 ;
-; 12 ; 10 ;
+; 7 ; 6 ;
+; 8 ; 2 ;
+; 9 ; 6 ;
+; 10 ; 6 ;
+; 11 ; 6 ;
+; 12 ; 4 ;
; 13 ; 4 ;
-; 14 ; 4 ;
-; 15 ; 6 ;
+; 14 ; 13 ;
+; 15 ; 10 ;
; 16 ; 5 ;
; 17 ; 4 ;
-; 18 ; 10 ;
-; 19 ; 5 ;
-; 20 ; 19 ;
-; 21 ; 13 ;
-; 22 ; 11 ;
+; 18 ; 9 ;
+; 19 ; 12 ;
+; 20 ; 16 ;
+; 21 ; 35 ;
+; 22 ; 28 ;
+----------------------------------------------+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 12:26:52 2010
+ Info: Processing started: Sun Dec 19 20:36:27 2010
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
Info: Selected device EP1C12Q240C8 for design "dt"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter converted 2 user pins into dedicated programming pins
Info: Pin ~nCSO~ is reserved at location 24
Info: Pin ~ASDO~ is reserved at location 37
+Critical Warning: No exact pin location assignment(s) for 29 pins of 32 total pins
+ Info: Pin sseg0[6] not assigned to an exact location on the device
+ Info: Pin sseg0[5] not assigned to an exact location on the device
+ Info: Pin sseg0[4] not assigned to an exact location on the device
+ Info: Pin sseg0[3] not assigned to an exact location on the device
+ Info: Pin sseg0[2] not assigned to an exact location on the device
+ Info: Pin sseg0[1] not assigned to an exact location on the device
+ Info: Pin sseg0[0] not assigned to an exact location on the device
+ Info: Pin sseg1[6] not assigned to an exact location on the device
+ Info: Pin sseg1[5] not assigned to an exact location on the device
+ Info: Pin sseg1[4] not assigned to an exact location on the device
+ Info: Pin sseg1[3] not assigned to an exact location on the device
+ Info: Pin sseg1[2] not assigned to an exact location on the device
+ Info: Pin sseg1[1] not assigned to an exact location on the device
+ Info: Pin sseg1[0] not assigned to an exact location on the device
+ Info: Pin sseg2[6] not assigned to an exact location on the device
+ Info: Pin sseg2[5] not assigned to an exact location on the device
+ Info: Pin sseg2[4] not assigned to an exact location on the device
+ Info: Pin sseg2[3] not assigned to an exact location on the device
+ Info: Pin sseg2[2] not assigned to an exact location on the device
+ Info: Pin sseg2[1] not assigned to an exact location on the device
+ Info: Pin sseg2[0] not assigned to an exact location on the device
+ Info: Pin sseg3[6] not assigned to an exact location on the device
+ Info: Pin sseg3[5] not assigned to an exact location on the device
+ Info: Pin sseg3[4] not assigned to an exact location on the device
+ Info: Pin sseg3[3] not assigned to an exact location on the device
+ Info: Pin sseg3[2] not assigned to an exact location on the device
+ Info: Pin sseg3[1] not assigned to an exact location on the device
+ Info: Pin sseg3[0] not assigned to an exact location on the device
+ Info: Pin bus_rx not assigned to an exact location on the device
Info: Timing-driven compilation is using the Classic Timing Analyzer
Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "sys_clk" to use Global clock in PIN 152
Info: Automatically promoted some destinations of signal "sys_res" to use Global clock
- Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0" may be non-global or may not use global clock
- Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[6]~3" may be non-global or may not use global clock
+ Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data" may be non-global or may not use global clock
+ Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[0]~1" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6]~0" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5]~2" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7]~4" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4]~6" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2]~8" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1]~10" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3]~12" may be non-global or may not use global clock
+ Info: Limited to 10 non-global destinations
Info: Pin "sys_res" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 29 (unused VREF, 3.3V VCCIO, 1 input, 28 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVCMOS.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used -- 41 pins available
+ Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available
+ Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used -- 43 pins available
+ Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter preparation operations ending: elapsed time is 00:00:02
Info: Fitter placement preparation operations beginning
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
-Info: Estimated most critical path is memory to register delay of 21.050 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y15; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg2'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y15; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a6'
- Info: 3: + IC(1.222 ns) + CELL(0.442 ns) = 5.981 ns; Loc. = LAB_X38_Y16; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[6]~17'
- Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 6.634 ns; Loc. = LAB_X38_Y16; Fanout = 4; COMB Node = 'execute_stage:exec_st|left_operand[6]~18'
- Info: 5: + IC(0.117 ns) + CELL(0.590 ns) = 7.341 ns; Loc. = LAB_X38_Y16; Fanout = 9; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector101~0'
- Info: 6: + IC(1.338 ns) + CELL(0.575 ns) = 9.254 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~37COUT1_200'
- Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.334 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~27COUT1_202'
- Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 9.414 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~17COUT1_204'
- Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 9.494 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~32COUT1_206'
- Info: 10: + IC(0.000 ns) + CELL(0.258 ns) = 9.752 ns; Loc. = LAB_X30_Y16; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~52'
- Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 9.888 ns; Loc. = LAB_X30_Y16; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~87'
- Info: 12: + IC(0.000 ns) + CELL(0.136 ns) = 10.024 ns; Loc. = LAB_X30_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~117'
- Info: 13: + IC(0.000 ns) + CELL(0.679 ns) = 10.703 ns; Loc. = LAB_X30_Y15; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~120'
- Info: 14: + IC(0.771 ns) + CELL(0.432 ns) = 11.906 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[21]~122COUT1_219'
- Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 11.986 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[22]~127COUT1_221'
- Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 12.066 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[23]~132COUT1_223'
- Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 12.146 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[24]~137COUT1_225'
- Info: 18: + IC(0.000 ns) + CELL(0.258 ns) = 12.404 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[25]~142'
- Info: 19: + IC(0.000 ns) + CELL(0.679 ns) = 13.083 ns; Loc. = LAB_X31_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[28]~65'
- Info: 20: + IC(1.640 ns) + CELL(0.114 ns) = 14.837 ns; Loc. = LAB_X36_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~0'
- Info: 21: + IC(1.086 ns) + CELL(0.292 ns) = 16.215 ns; Loc. = LAB_X36_Y16; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~1'
- Info: 22: + IC(0.752 ns) + CELL(0.590 ns) = 17.557 ns; Loc. = LAB_X36_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
- Info: 23: + IC(0.539 ns) + CELL(0.114 ns) = 18.210 ns; Loc. = LAB_X36_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
- Info: 24: + IC(0.063 ns) + CELL(0.590 ns) = 18.863 ns; Loc. = LAB_X36_Y15; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
- Info: 25: + IC(0.211 ns) + CELL(0.442 ns) = 19.516 ns; Loc. = LAB_X36_Y15; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
- Info: 26: + IC(0.667 ns) + CELL(0.867 ns) = 21.050 ns; Loc. = LAB_X37_Y15; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
- Info: Total cell delay = 12.581 ns ( 59.77 % )
- Info: Total interconnect delay = 8.469 ns ( 40.23 % )
+Info: Estimated most critical path is register to register delay of 23.818 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X35_Y17; Fanout = 2; REG Node = 'writeback_stage:writeback_st|wb_reg.address[16]'
+ Info: 2: + IC(0.860 ns) + CELL(0.114 ns) = 0.974 ns; Loc. = LAB_X36_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
+ Info: 3: + IC(1.490 ns) + CELL(0.114 ns) = 2.578 ns; Loc. = LAB_X29_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
+ Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 3.231 ns; Loc. = LAB_X29_Y17; Fanout = 4; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
+ Info: 5: + IC(0.211 ns) + CELL(0.442 ns) = 3.884 ns; Loc. = LAB_X29_Y17; Fanout = 27; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|gread~0'
+ Info: 6: + IC(1.564 ns) + CELL(0.590 ns) = 6.038 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~96'
+ Info: 7: + IC(1.633 ns) + CELL(0.114 ns) = 7.785 ns; Loc. = LAB_X22_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~97'
+ Info: 8: + IC(1.653 ns) + CELL(0.114 ns) = 9.552 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~98'
+ Info: 9: + IC(0.361 ns) + CELL(0.292 ns) = 10.205 ns; Loc. = LAB_X27_Y12; Fanout = 6; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~99'
+ Info: 10: + IC(1.177 ns) + CELL(0.114 ns) = 11.496 ns; Loc. = LAB_X29_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|right_operand[17]~64'
+ Info: 11: + IC(0.361 ns) + CELL(0.292 ns) = 12.149 ns; Loc. = LAB_X29_Y12; Fanout = 5; COMB Node = 'execute_stage:exec_st|right_operand[17]~65'
+ Info: 12: + IC(1.889 ns) + CELL(0.114 ns) = 14.152 ns; Loc. = LAB_X36_Y11; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~176'
+ Info: 13: + IC(1.431 ns) + CELL(0.575 ns) = 16.158 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~78COUT1_259'
+ Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 16.238 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~73COUT1_261'
+ Info: 15: + IC(0.000 ns) + CELL(0.608 ns) = 16.846 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~66'
+ Info: 16: + IC(1.416 ns) + CELL(0.590 ns) = 18.852 ns; Loc. = LAB_X23_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector12~2'
+ Info: 17: + IC(0.063 ns) + CELL(0.590 ns) = 19.505 ns; Loc. = LAB_X23_Y12; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector12~5'
+ Info: 18: + IC(0.752 ns) + CELL(0.590 ns) = 20.847 ns; Loc. = LAB_X23_Y11; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~1'
+ Info: 19: + IC(1.563 ns) + CELL(0.590 ns) = 23.000 ns; Loc. = LAB_X28_Y18; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~2'
+ Info: 20: + IC(0.211 ns) + CELL(0.607 ns) = 23.818 ns; Loc. = LAB_X28_Y18; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
+ Info: Total cell delay = 7.120 ns ( 29.89 % )
+ Info: Total interconnect delay = 16.698 ns ( 70.11 % )
Info: Fitter routing operations beginning
-Info: Router estimated average interconnect usage is 4% of the available device resources
- Info: Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X32_Y14 to location X42_Y27
-Info: Fitter routing operations ending: elapsed time is 00:00:04
+Info: Router estimated average interconnect usage is 9% of the available device resources
+ Info: Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
+Info: Fitter routing operations ending: elapsed time is 00:00:05
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
-Info: Quartus II Fitter was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 269 megabytes
- Info: Processing ended: Fri Dec 17 12:27:11 2010
- Info: Elapsed time: 00:00:19
- Info: Total CPU time (on all processors): 00:00:19
+Info: Quartus II Fitter was successful. 0 errors, 3 warnings
+ Info: Peak virtual memory: 272 megabytes
+ Info: Processing ended: Sun Dec 19 20:36:45 2010
+ Info: Elapsed time: 00:00:18
+ Info: Total CPU time (on all processors): 00:00:16
-Fitter Status : Successful - Fri Dec 17 12:27:10 2010
+Fitter Status : Successful - Sun Dec 19 20:36:44 2010
Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
Revision Name : dt
Top-level Entity Name : core_top
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
-Total logic elements : 1,058 / 12,060 ( 9 % )
-Total pins : 3 / 173 ( 2 % )
+Total logic elements : 1,646 / 12,060 ( 14 % )
+Total pins : 32 / 173 ( 18 % )
Total virtual pins : 0
-Total memory bits : 512 / 239,616 ( < 1 % )
+Total memory bits : 66,560 / 239,616 ( 28 % )
Total PLLs : 0 / 2 ( 0 % )
Flow report for dt
-Fri Dec 17 12:27:19 2010
+Sun Dec 19 20:36:51 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+-----------------------------------------------+
-; Flow Status ; Successful - Fri Dec 17 12:27:18 2010 ;
+; Flow Status ; Successful - Sun Dec 19 20:36:51 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
-; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
-; Total pins ; 3 / 173 ( 2 % ) ;
+; Total logic elements ; 1,646 / 12,060 ( 14 % ) ;
+; Total pins ; 32 / 173 ( 18 % ) ;
; Total virtual pins ; 0 ;
-; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+; Total memory bits ; 66,560 / 239,616 ( 28 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-------------------------+-----------------------------------------------+
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 12/17/2010 12:26:26 ;
+; Start date & time ; 12/19/2010 20:36:12 ;
; Main task ; Compilation ;
; Revision Name ; dt ;
+-------------------+---------------------+
+-------------------------------------+--------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+--------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 91815333562.129258518625184 ; -- ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 99901343620.129278737205529 ; -- ; -- ; -- ;
; MISC_FILE ; /homes/burban/dt/dt.dpf ; -- ; -- ; -- ;
; MISC_FILE ; /homes/c0726283/calu/dt/dt.dpf ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; core_top ; Top ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:23 ; 1.0 ; -- ; 00:00:21 ;
-; Fitter ; 00:00:18 ; 1.0 ; -- ; 00:00:18 ;
-; Assembler ; 00:00:03 ; 1.0 ; -- ; 00:00:02 ;
-; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; -- ; 00:00:01 ;
-; Total ; 00:00:44 ; -- ; -- ; 00:00:42 ;
+; Analysis & Synthesis ; 00:00:13 ; 1.0 ; -- ; 00:00:12 ;
+; Fitter ; 00:00:17 ; 1.0 ; -- ; 00:00:15 ;
+; Assembler ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ;
+; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ;
+; Total ; 00:00:32 ; -- ; -- ; 00:00:29 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-+------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+-------------------------+------------------+---------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+-------------------------+------------------+---------+------------+----------------+
-; Analysis & Synthesis ; ti9 ; Red Hat ; 5 ; x86_64 ;
-; Fitter ; ti9 ; Red Hat ; 5 ; x86_64 ;
-; Assembler ; ti9 ; Red Hat ; 5 ; x86_64 ;
-; Classic Timing Analyzer ; ti9 ; Red Hat ; 5 ; x86_64 ;
-+-------------------------+------------------+---------+------------+----------------+
++-------------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++-------------------------+------------------+----------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++-------------------------+------------------+----------------+------------+----------------+
+; Analysis & Synthesis ; ubuntu ; Ubuntu 10.04.1 ; 10 ; x86_64 ;
+; Fitter ; ubuntu ; Ubuntu 10.04.1 ; 10 ; x86_64 ;
+; Assembler ; ubuntu ; Ubuntu 10.04.1 ; 10 ; x86_64 ;
+; Classic Timing Analyzer ; ubuntu ; Ubuntu 10.04.1 ; 10 ; x86_64 ;
++-------------------------+------------------+----------------+------------+----------------+
------------
Analysis & Synthesis report for dt
-Fri Dec 17 12:26:49 2010
+Sun Dec 19 20:36:26 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
14. Inverted Register Statistics
15. Registers Packed Into Inferred Megafunctions
16. Multiplexer Restructuring Statistics (Restructuring Performed)
- 17. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated
+ 17. Source assignments for writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated
18. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated
- 19. Parameter Settings for User Entity Instance: fetch_stage:fetch_st
- 20. Parameter Settings for User Entity Instance: fetch_stage:fetch_st|r_w_ram:instruction_ram
- 21. Parameter Settings for User Entity Instance: decode_stage:decode_st
- 22. Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram
- 23. Parameter Settings for User Entity Instance: execute_stage:exec_st
- 24. Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst
- 25. Parameter Settings for User Entity Instance: writeback_stage:writeback_st
- 26. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram
- 27. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart
- 28. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst
- 29. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst
- 30. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0
- 31. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
- 32. altsyncram Parameter Settings by Entity Instance
- 33. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst"
- 34. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart"
- 35. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
- 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
- 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
- 38. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
- 39. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
- 40. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
- 41. Port Connectivity Checks: "execute_stage:exec_st"
- 42. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
- 43. Analysis & Synthesis Messages
+ 19. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated
+ 20. Parameter Settings for User Entity Instance: fetch_stage:fetch_st
+ 21. Parameter Settings for User Entity Instance: fetch_stage:fetch_st|rom:instruction_ram
+ 22. Parameter Settings for User Entity Instance: decode_stage:decode_st
+ 23. Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram
+ 24. Parameter Settings for User Entity Instance: execute_stage:exec_st
+ 25. Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst
+ 26. Parameter Settings for User Entity Instance: writeback_stage:writeback_st
+ 27. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram
+ 28. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart
+ 29. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst
+ 30. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst
+ 31. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_7seg:sseg
+ 32. Parameter Settings for Inferred Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0
+ 33. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
+ 34. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2
+ 35. altsyncram Parameter Settings by Entity Instance
+ 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
+ 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
+ 38. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
+ 39. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
+ 40. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
+ 41. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
+ 42. Port Connectivity Checks: "execute_stage:exec_st"
+ 43. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
+ 44. Analysis & Synthesis Messages
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Fri Dec 17 12:26:49 2010 ;
+; Analysis & Synthesis Status ; Successful - Sun Dec 19 20:36:26 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
-; Total logic elements ; 1,143 ;
-; Total pins ; 3 ;
+; Total logic elements ; 1,879 ;
+; Total pins ; 32 ;
; Total virtual pins ; 0 ;
-; Total memory bits ; 512 ;
+; Total memory bits ; 66,560 ;
; Total PLLs ; 0 ;
+-----------------------------+-----------------------------------------------+
+----------------------------+--------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
-+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
-; ../cpu/src/rs232_rx_arc.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_rx_arc.vhd ;
-; ../cpu/src/rs232_rx.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_rx.vhd ;
-; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/writeback_stage_b.vhd ;
-; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/writeback_stage.vhd ;
-; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_tx_arc.vhd ;
-; ../cpu/src/rs232_tx.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_tx.vhd ;
-; ../cpu/src/r_w_ram_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r_w_ram_b.vhd ;
-; ../cpu/src/r_w_ram.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r_w_ram.vhd ;
-; ../cpu/src/r2_w_ram_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r2_w_ram_b.vhd ;
-; ../cpu/src/r2_w_ram.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r2_w_ram.vhd ;
-; ../cpu/src/mem_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/mem_pkg.vhd ;
-; ../cpu/src/fetch_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/fetch_stage_b.vhd ;
-; ../cpu/src/fetch_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/fetch_stage.vhd ;
-; ../cpu/src/extension_uart_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart_pkg.vhd ;
-; ../cpu/src/extension_uart_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart_b.vhd ;
-; ../cpu/src/extension_uart.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart.vhd ;
-; ../cpu/src/extension_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_pkg.vhd ;
-; ../cpu/src/extension_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_b.vhd ;
-; ../cpu/src/extension.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension.vhd ;
-; ../cpu/src/execute_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/execute_stage_b.vhd ;
-; ../cpu/src/execute_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/execute_stage.vhd ;
-; ../cpu/src/exec_op.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op.vhd ;
-; ../cpu/src/decoder_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decoder_b.vhd ;
-; ../cpu/src/decoder.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decoder.vhd ;
-; ../cpu/src/decode_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decode_stage_b.vhd ;
-; ../cpu/src/decode_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decode_stage.vhd ;
-; ../cpu/src/core_top.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/core_top.vhd ;
-; ../cpu/src/core_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/core_pkg.vhd ;
-; ../cpu/src/common_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/common_pkg.vhd ;
-; ../cpu/src/alu_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu_pkg.vhd ;
-; ../cpu/src/alu_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu_b.vhd ;
-; ../cpu/src/alu.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu.vhd ;
-; ../cpu/src/exec_op/xor_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/xor_op_b.vhd ;
-; ../cpu/src/exec_op/shift_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/shift_op_b.vhd ;
-; ../cpu/src/exec_op/or_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/or_op_b.vhd ;
-; ../cpu/src/exec_op/and_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/and_op_b.vhd ;
-; ../cpu/src/exec_op/add_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/add_op_b.vhd ;
-; altsyncram.tdf ; yes ; Megafunction ; /opt/altera/10.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ;
-; db/altsyncram_emk1.tdf ; yes ; Auto-Generated Megafunction ; /homes/c0726283/calu/dt/db/altsyncram_emk1.tdf ;
-; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /homes/c0726283/calu/dt/db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
+; ../cpu/src/rom.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rom.vhd ;
+; ../cpu/src/rom_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rom_b.vhd ;
+; ../cpu/src/extension_7seg_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg_pkg.vhd ;
+; ../cpu/src/extension_7seg_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg_b.vhd ;
+; ../cpu/src/extension_7seg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg.vhd ;
+; ../cpu/src/rs232_rx_arc.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_rx_arc.vhd ;
+; ../cpu/src/rs232_rx.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_rx.vhd ;
+; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/writeback_stage_b.vhd ;
+; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/writeback_stage.vhd ;
+; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_tx_arc.vhd ;
+; ../cpu/src/rs232_tx.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_tx.vhd ;
+; ../cpu/src/r_w_ram_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r_w_ram_b.vhd ;
+; ../cpu/src/r_w_ram.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r_w_ram.vhd ;
+; ../cpu/src/r2_w_ram_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r2_w_ram_b.vhd ;
+; ../cpu/src/r2_w_ram.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r2_w_ram.vhd ;
+; ../cpu/src/mem_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/mem_pkg.vhd ;
+; ../cpu/src/fetch_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd ;
+; ../cpu/src/fetch_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/fetch_stage.vhd ;
+; ../cpu/src/extension_uart_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart_pkg.vhd ;
+; ../cpu/src/extension_uart_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart_b.vhd ;
+; ../cpu/src/extension_uart.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart.vhd ;
+; ../cpu/src/extension_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_pkg.vhd ;
+; ../cpu/src/extension_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_b.vhd ;
+; ../cpu/src/extension.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension.vhd ;
+; ../cpu/src/execute_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/execute_stage_b.vhd ;
+; ../cpu/src/execute_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/execute_stage.vhd ;
+; ../cpu/src/exec_op.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op.vhd ;
+; ../cpu/src/decoder_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decoder_b.vhd ;
+; ../cpu/src/decoder.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decoder.vhd ;
+; ../cpu/src/decode_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decode_stage_b.vhd ;
+; ../cpu/src/decode_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decode_stage.vhd ;
+; ../cpu/src/core_top.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/core_top.vhd ;
+; ../cpu/src/core_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/core_pkg.vhd ;
+; ../cpu/src/common_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/common_pkg.vhd ;
+; ../cpu/src/alu_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu_pkg.vhd ;
+; ../cpu/src/alu_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu_b.vhd ;
+; ../cpu/src/alu.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu.vhd ;
+; ../cpu/src/exec_op/xor_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/xor_op_b.vhd ;
+; ../cpu/src/exec_op/shift_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/shift_op_b.vhd ;
+; ../cpu/src/exec_op/or_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/or_op_b.vhd ;
+; ../cpu/src/exec_op/and_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/and_op_b.vhd ;
+; ../cpu/src/exec_op/add_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/add_op_b.vhd ;
+; altsyncram.tdf ; yes ; Megafunction ; /opt/altera/10.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ;
+; db/altsyncram_grk1.tdf ; yes ; Auto-Generated Megafunction ; /home/stefan/processor/calu/dt/db/altsyncram_grk1.tdf ;
+; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/stefan/processor/calu/dt/db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ;
+; db/altsyncram_emk1.tdf ; yes ; Auto-Generated Megafunction ; /home/stefan/processor/calu/dt/db/altsyncram_emk1.tdf ;
+; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/stefan/processor/calu/dt/db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
++--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
+-------------------------------------------------------+
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
-; Total logic elements ; 1143 ;
-; -- Combinational with no register ; 928 ;
-; -- Register only ; 85 ;
-; -- Combinational with a register ; 130 ;
+; Total logic elements ; 1879 ;
+; -- Combinational with no register ; 1359 ;
+; -- Register only ; 259 ;
+; -- Combinational with a register ; 261 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 473 ;
-; -- 3 input functions ; 443 ;
-; -- 2 input functions ; 123 ;
-; -- 1 input functions ; 18 ;
-; -- 0 input functions ; 1 ;
+; -- 4 input functions ; 827 ;
+; -- 3 input functions ; 474 ;
+; -- 2 input functions ; 292 ;
+; -- 1 input functions ; 27 ;
+; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 937 ;
-; -- arithmetic mode ; 206 ;
+; -- normal mode ; 1703 ;
+; -- arithmetic mode ; 176 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 7 ;
-; -- asynchronous clear/load mode ; 203 ;
+; -- synchronous clear/load mode ; 57 ;
+; -- asynchronous clear/load mode ; 492 ;
; ; ;
-; Total registers ; 215 ;
-; Total logic cells in carry chains ; 214 ;
-; I/O pins ; 3 ;
-; Total memory bits ; 512 ;
+; Total registers ; 520 ;
+; Total logic cells in carry chains ; 184 ;
+; I/O pins ; 32 ;
+; Total memory bits ; 66560 ;
; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 279 ;
-; Total fan-out ; 4464 ;
-; Average fan-out ; 3.69 ;
+; Maximum fan-out ; 616 ;
+; Total fan-out ; 8075 ;
+; Average fan-out ; 4.02 ;
+---------------------------------------------+---------+
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1143 (1) ; 215 ; 512 ; 3 ; 0 ; 928 (1) ; 85 (0) ; 130 (0) ; 214 (0) ; 0 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 106 (99) ; 72 ; 512 ; 0 ; 0 ; 34 (27) ; 51 (51) ; 21 (21) ; 11 (11) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
-; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
-; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
-; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 831 (185) ; 67 ; 0 ; 0 ; 0 ; 764 (149) ; 20 (1) ; 47 (35) ; 171 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 581 (259) ; 0 ; 0 ; 0 ; 0 ; 581 (259) ; 0 (0) ; 0 (0) ; 141 (43) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:or_inst| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
-; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
-; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 34 (34) ; 19 (19) ; 12 (12) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
-; |fetch_stage:fetch_st| ; 39 (30) ; 17 ; 0 ; 0 ; 0 ; 22 (19) ; 11 (11) ; 6 (0) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 166 (49) ; 59 ; 0 ; 0 ; 0 ; 107 (45) ; 3 (1) ; 56 (3) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_uart:uart| ; 108 (14) ; 49 ; 0 ; 0 ; 0 ; 59 (4) ; 2 (2) ; 47 (8) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
-; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
+; |core_top ; 1879 (0) ; 520 ; 66560 ; 32 ; 0 ; 1359 (0) ; 259 (0) ; 261 (0) ; 184 (0) ; 0 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 220 (153) ; 106 ; 1024 ; 0 ; 0 ; 114 (47) ; 54 (54) ; 52 (52) ; 11 (11) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
+; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
+; |altsyncram:ram_rtl_2| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ; ;
+; |execute_stage:exec_st| ; 940 (175) ; 71 ; 0 ; 0 ; 0 ; 869 (136) ; 23 (4) ; 48 (35) ; 108 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 703 (387) ; 0 ; 0 ; 0 ; 0 ; 703 (387) ; 0 (0) ; 0 (0) ; 78 (44) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 34 (34) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |exec_op:shift_inst| ; 249 (249) ; 0 ; 0 ; 0 ; 0 ; 249 (249) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
+; |extension_gpm:gpmp_inst| ; 62 (62) ; 32 ; 0 ; 0 ; 0 ; 30 (30) ; 19 (19) ; 13 (13) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
+; |fetch_stage:fetch_st| ; 55 (34) ; 29 ; 0 ; 0 ; 0 ; 26 (23) ; 11 (11) ; 18 (0) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |rom:instruction_ram| ; 21 (21) ; 18 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 18 (18) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|rom:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 664 (247) ; 314 ; 65536 ; 0 ; 0 ; 350 (183) ; 171 (45) ; 143 (19) ; 65 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_7seg:sseg| ; 48 (48) ; 47 ; 0 ; 0 ; 0 ; 1 (1) ; 18 (18) ; 29 (29) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_7seg:sseg ; ;
+; |extension_uart:uart| ; 369 (145) ; 203 ; 0 ; 0 ; 0 ; 166 (39) ; 108 (98) ; 95 (8) ; 65 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |rs232_rx:rs232_rx_inst| ; 160 (160) ; 73 ; 0 ; 0 ; 0 ; 87 (87) ; 10 (10) ; 63 (63) ; 48 (48) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst ; ;
+; |rs232_tx:rs232_tx_inst| ; 64 (64) ; 24 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 24 (24) ; 17 (17) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
+; |r_w_ram:data_ram| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ; ;
+; |altsyncram_grk1:auto_generated| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ; ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis RAM Summary ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
-; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
+; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
Encoding Type: One-Hot
+--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-; Register name ; Reason for Removal ;
-+------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-; writeback_stage:writeback_st|bus_rx ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; Lost fanout ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0,2,5,8,10..15,17..18,20,22] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0,2,5,8,10..15,17..18,20,22] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.condition[1..3] ; Stuck at VCC due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.op_detail[5] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.displacement[0,2,5,8,10..31] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.saddr1[3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.saddr2[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.daddr[1,3] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|reg.res_addr[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|rtw_rec.immediate[5,7..8,10..11,15] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[23] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[1] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4,6] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[19] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[23] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[1] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[4,6] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[19] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[3] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[7] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ;
-; decode_stage:decode_st|dec_op_inst.daddr[2] ; Lost fanout ;
-; execute_stage:exec_st|reg.res_addr[0] ; Merged with execute_stage:exec_st|reg.res_addr[2] ;
-; decode_stage:decode_st|rtw_rec.immediate[18,21,23..28,30] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
-; decode_stage:decode_st|rtw_rec.immediate[16] ; Merged with decode_stage:decode_st|rtw_rec.immediate[29] ;
-; decode_stage:decode_st|rtw_rec.immediate[20] ; Merged with decode_stage:decode_st|rtw_rec.immediate[22] ;
-; decode_stage:decode_st|rtw_rec.immediate[17] ; Merged with decode_stage:decode_st|rtw_rec.immediate[19] ;
-; decode_stage:decode_st|rtw_rec.immediate[12] ; Merged with decode_stage:decode_st|rtw_rec.immediate[14] ;
-; decode_stage:decode_st|rtw_rec.immediate[1] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
-; decode_stage:decode_st|dec_op_inst.displacement[7] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[9] ;
-; decode_stage:decode_st|dec_op_inst.displacement[4] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[6] ;
-; decode_stage:decode_st|dec_op_inst.saddr1[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr1[2] ;
-; decode_stage:decode_st|dec_op_inst.saddr2[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr2[2] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[1] ; Merged with decode_stage:decode_st|dec_op_inst.op_detail[2] ;
-; decode_stage:decode_st|rtw_rec.immediate[19,22,29] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
-; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0..31] ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0..31] ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP ; Lost fanout ;
-; decode_stage:decode_st|rtw_rec.immediate[31] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.OR_OP ;
-; decode_stage:decode_st|rtw_rec.immediate[9] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ;
-; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
-; Total Number of Removed Registers = 332 ; ;
-+------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Removed Registers Triggering Further Register Optimizations ;
-+-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
-; Register name ; Reason for Removal ; Registers Removed due to This Register ;
-+-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.op_detail[5], ;
-; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.saddr1[3], ;
-; ; ; decode_stage:decode_st|dec_op_inst.saddr2[3], ;
-; ; ; decode_stage:decode_st|dec_op_inst.saddr2[1], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[15], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[11], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[10], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[8], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[7], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[5] ;
-; writeback_stage:writeback_st|bus_rx ; Stuck at VCC ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[31], ;
-; ; due to stuck port data_in ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[30], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[29], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[28], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[27], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[26], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[25], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[24] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[3], ;
-; ; due to stuck port data_in ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo, ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[22] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[3], execute_stage:exec_st|reg.res_addr[3] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[20] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[1], execute_stage:exec_st|reg.res_addr[1] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[30] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[2] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[1] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[14] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[14] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[13] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[13] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[12] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[12] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[11] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[11] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[10] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[10] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[8] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[5] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[5] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[2] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[0] ;
-; ; due to stuck port data_in ; ;
-+-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
+; Register name ; Reason for Removal ;
++------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
+; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[2,8] ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.address[0..1] ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.displacement[2,8] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
+; writeback_stage:writeback_st|wb_reg.byte_en[0..3] ; Merged with writeback_stage:writeback_st|wb_reg.dmem_en ;
+; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[0] ; Merged with writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[1] ;
+; writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[8..30] ; Merged with writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[31] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[9,28..30] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[31] ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[0,10..14,18] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[3] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[4] ;
+; decode_stage:decode_st|rtw_rec.immediate[23..27] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
+; decode_stage:decode_st|rtw_rec.immediate[16] ; Merged with decode_stage:decode_st|rtw_rec.immediate[17] ;
+; decode_stage:decode_st|rtw_rec.immediate[7] ; Merged with decode_stage:decode_st|rtw_rec.immediate[11] ;
+; decode_stage:decode_st|dec_op_inst.condition[1..2] ; Merged with decode_stage:decode_st|dec_op_inst.condition[3] ;
+; decode_stage:decode_st|dec_op_inst.displacement[15..30] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[31] ;
+; decode_stage:decode_st|dec_op_inst.displacement[0,10..13] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[14] ;
+; decode_stage:decode_st|dec_op_inst.displacement[3] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[4] ;
+; writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[31] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.displacement[14] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[31] ;
+; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17..31] ; Lost fanout ;
+; Total Number of Removed Registers = 231 ; ;
++------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations ;
++---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
+; Register name ; Reason for Removal ; Registers Removed due to This Register ;
++---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost Fanouts ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo, ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[8] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[2] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
+; ; due to stuck port data_in ; ;
++---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
+------------------------------------------------------+
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
-; Total registers ; 215 ;
-; Number of registers using Synchronous Clear ; 4 ;
-; Number of registers using Synchronous Load ; 6 ;
-; Number of registers using Asynchronous Clear ; 192 ;
-; Number of registers using Asynchronous Load ; 11 ;
-; Number of registers using Clock Enable ; 43 ;
+; Total registers ; 520 ;
+; Number of registers using Synchronous Clear ; 25 ;
+; Number of registers using Synchronous Load ; 40 ;
+; Number of registers using Asynchronous Clear ; 487 ;
+; Number of registers using Asynchronous Load ; 5 ;
+; Number of registers using Clock Enable ; 177 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
-+------------------------------------------------------------------------------------------------+
-; Inverted Register Statistics ;
-+--------------------------------------------------------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+--------------------------------------------------------------------------------------+---------+
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 1 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 2 ;
-; decode_stage:decode_st|dec_op_inst.condition[0] ; 1 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 4 ;
-; Total number of inverted registers = 24 ; ;
-+--------------------------------------------------------------------------------------+---------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Registers Packed Into Inferred Megafunctions ;
-+------------------------------------------------------------+-----------------------------------------------------+------+
-; Register Name ; Megafunction ; Type ;
-+------------------------------------------------------------+-----------------------------------------------------+------+
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-+------------------------------------------------------------+-----------------------------------------------------+------+
++-----------------------------------------------------------------------------------------------+
+; Inverted Register Statistics ;
++-------------------------------------------------------------------------------------+---------+
+; Inverted Register ; Fan out ;
++-------------------------------------------------------------------------------------+---------+
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 1 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[1] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[4] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[5] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[7] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[8] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 2 ;
+; decode_stage:decode_st|dec_op_inst.condition[0] ; 1 ;
+; decode_stage:decode_st|dec_op_inst.condition[3] ; 1 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[2] ; 13 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 1 ;
+; Total number of inverted registers = 26 ; ;
++-------------------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Registers Packed Into Inferred Megafunctions ;
++------------------------------------------------------------+------------------------------------------------------+------+
+; Register Name ; Megafunction ; Type ;
++------------------------------------------------------------+------------------------------------------------------+------+
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[1] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[5] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[6] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[8] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[10] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[11] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[13] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[14] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[15] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[17] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[19] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[22] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[30] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[31] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
++------------------------------------------------------------+------------------------------------------------------+------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
-; 3:1 ; 21 bits ; 42 LEs ; 21 LEs ; 21 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25] ;
-; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |core_top|decode_stage:decode_st|dec_op_inst.displacement[1] ;
-; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ;
-; 5:1 ; 14 bits ; 42 LEs ; 28 LEs ; 14 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[31] ;
-; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[19] ;
+; 3:1 ; 27 bits ; 54 LEs ; 27 LEs ; 27 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17] ;
+; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |core_top|decode_stage:decode_st|dec_op_inst.displacement[7] ;
+; 4:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|wb_reg.address[19] ;
+; 5:1 ; 21 bits ; 63 LEs ; 42 LEs ; 21 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[30] ;
; 18:1 ; 3 bits ; 36 LEs ; 3 LEs ; 33 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ;
-; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1] ;
-; 9:1 ; 5 bits ; 30 LEs ; 25 LEs ; 5 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[7] ;
-; 9:1 ; 13 bits ; 78 LEs ; 65 LEs ; 13 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[21] ;
-; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[4] ;
-; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[25] ;
-; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[1] ;
-; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[29] ;
-; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ;
+; 5:1 ; 16 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4] ;
+; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ;
+; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|condition[0] ;
+; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.reg_src2_addr[1] ;
+; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_ST_OP ;
+; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[8] ;
; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|left_operand[19] ;
-; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
-; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[10] ;
-; 4:1 ; 26 bits ; 52 LEs ; 52 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[30] ;
-; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector48 ;
-; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[0] ;
-; 5:1 ; 6 bits ; 18 LEs ; 12 LEs ; 6 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[6] ;
-; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector97 ;
-; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|Selector0 ;
-; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|Selector2 ;
+; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[5] ;
+; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector63 ;
+; 5:1 ; 11 bits ; 33 LEs ; 22 LEs ; 11 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[0] ;
+; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector98 ;
+; 32:1 ; 3 bits ; 63 LEs ; 6 LEs ; 57 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.reg_src1_addr[0] ;
+; 6:1 ; 9 bits ; 36 LEs ; 27 LEs ; 9 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
+; 7:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[12] ;
+; 10:1 ; 24 bits ; 144 LEs ; 96 LEs ; 48 LEs ; No ; |core_top|writeback_stage:writeback_st|regfile_val[24] ;
+; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[3] ;
+; 11:1 ; 8 bits ; 56 LEs ; 48 LEs ; 8 LEs ; No ; |core_top|writeback_stage:writeback_st|regfile_val[0] ;
+; 10:1 ; 18 bits ; 108 LEs ; 108 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector16 ;
+; 11:1 ; 4 bits ; 28 LEs ; 24 LEs ; 4 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector3 ;
+; 11:1 ; 4 bits ; 28 LEs ; 24 LEs ; 4 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector28 ;
+; 12:1 ; 2 bits ; 16 LEs ; 14 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector1 ;
+; 12:1 ; 2 bits ; 16 LEs ; 14 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector29 ;
+; 14:1 ; 3 bits ; 27 LEs ; 21 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ;
++---------------------------------+--------------------+------+------------------------------------------------------------+
+; Assignment ; Value ; From ; To ;
++---------------------------------+--------------------+------+------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
++---------------------------------+--------------------+------+------------------------------------------------------------+
+
+
+-------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ;
+; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ;
+; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-+-------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: fetch_stage:fetch_st|r_w_ram:instruction_ram ;
-+----------------+-------+------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+------------------------------------------------------------------+
-; addr_width ; 11 ; Signed Integer ;
-; data_width ; 32 ; Signed Integer ;
-+----------------+-------+------------------------------------------------------------------+
++---------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: fetch_stage:fetch_st|rom:instruction_ram ;
++----------------+-------+--------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------------------------------+
+; addr_width ; 11 ; Signed Integer ;
+; data_width ; 32 ; Signed Integer ;
++----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------------------------------------------------------+
; reset_value ; '0' ; Enumerated ;
+; sync_stages ; 2 ; Signed Integer ;
+----------------+-------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
++-----------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_7seg:sseg ;
++----------------+-------+----------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+----------------------------------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
++----------------+-------+----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ;
++------------------------------------+-------------------------------------+------------------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------------------+-------------------------------------+------------------------------------------+
+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+; WIDTH_BYTEENA ; 1 ; Untyped ;
+; OPERATION_MODE ; DUAL_PORT ; Untyped ;
+; WIDTH_A ; 32 ; Untyped ;
+; WIDTHAD_A ; 11 ; Untyped ;
+; NUMWORDS_A ; 2048 ; Untyped ;
+; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
+; ADDRESS_ACLR_A ; NONE ; Untyped ;
+; OUTDATA_ACLR_A ; NONE ; Untyped ;
+; WRCONTROL_ACLR_A ; NONE ; Untyped ;
+; INDATA_ACLR_A ; NONE ; Untyped ;
+; BYTEENA_ACLR_A ; NONE ; Untyped ;
+; WIDTH_B ; 32 ; Untyped ;
+; WIDTHAD_B ; 11 ; Untyped ;
+; NUMWORDS_B ; 2048 ; Untyped ;
+; INDATA_REG_B ; CLOCK1 ; Untyped ;
+; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
+; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
+; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
+; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
+; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
+; INDATA_ACLR_B ; NONE ; Untyped ;
+; WRCONTROL_ACLR_B ; NONE ; Untyped ;
+; ADDRESS_ACLR_B ; NONE ; Untyped ;
+; OUTDATA_ACLR_B ; NONE ; Untyped ;
+; RDCONTROL_ACLR_B ; NONE ; Untyped ;
+; BYTEENA_ACLR_B ; NONE ; Untyped ;
+; WIDTH_BYTEENA_A ; 1 ; Untyped ;
+; WIDTH_BYTEENA_B ; 1 ; Untyped ;
+; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
+; BYTE_SIZE ; 8 ; Untyped ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; INIT_FILE ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; Untyped ;
+; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
+; MAXIMUM_DEPTH ; 0 ; Untyped ;
+; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
+; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
+; ENABLE_ECC ; FALSE ; Untyped ;
+; DEVICE_FAMILY ; Cyclone ; Untyped ;
+; CBXI_PARAMETER ; altsyncram_grk1 ; Untyped ;
++------------------------------------+-------------------------------------+------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ;
+; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
+------------------------------------+--------------------------------------+----------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------+----------------------------------------+
+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
+; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ;
+------------------------------------+--------------------------------------+----------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-+---------------------------------------------------------------------------------------------------------------+
-; altsyncram Parameter Settings by Entity Instance ;
-+-------------------------------------------+-------------------------------------------------------------------+
-; Name ; Value ;
-+-------------------------------------------+-------------------------------------------------------------------+
-; Number of entity instances ; 2 ;
-; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 32 ;
-; -- NUMWORDS_A ; 16 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 32 ;
-; -- NUMWORDS_B ; 16 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
-; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 32 ;
-; -- NUMWORDS_A ; 16 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 32 ;
-; -- NUMWORDS_B ; 16 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
-+-------------------------------------------+-------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst" ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-; new_rx_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; rx_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart" ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; data_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
++----------------------------------------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance ;
++-------------------------------------------+--------------------------------------------------------------------+
+; Name ; Value ;
++-------------------------------------------+--------------------------------------------------------------------+
+; Number of entity instances ; 3 ;
+; Entity Instance ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ;
+; -- OPERATION_MODE ; DUAL_PORT ;
+; -- WIDTH_A ; 32 ;
+; -- NUMWORDS_A ; 2048 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 32 ;
+; -- NUMWORDS_B ; 2048 ;
+; -- ADDRESS_REG_B ; CLOCK0 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
+; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
+; -- OPERATION_MODE ; DUAL_PORT ;
+; -- WIDTH_A ; 32 ;
+; -- NUMWORDS_A ; 16 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 32 ;
+; -- NUMWORDS_B ; 16 ;
+; -- ADDRESS_REG_B ; CLOCK0 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
+; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ;
+; -- OPERATION_MODE ; DUAL_PORT ;
+; -- WIDTH_A ; 32 ;
+; -- NUMWORDS_A ; 16 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 32 ;
+; -- NUMWORDS_B ; 16 ;
+; -- ADDRESS_REG_B ; CLOCK0 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
++-------------------------------------------+--------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 12:26:25 2010
+ Info: Processing started: Sun Dec 19 20:36:12 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dt -c dt
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rs232_rx_arc.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rom.vhd
+ Info: Found entity 1: rom
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rom_b.vhd
+ Info: Found design unit 1: rom-behaviour
+Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg_pkg.vhd
+ Info: Found design unit 1: extension_7seg_pkg
+ Info: Found design unit 2: extension_7seg_pkg-body
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg_b.vhd
+ Info: Found design unit 1: extension_7seg-behav
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg.vhd
+ Info: Found entity 1: extension_7seg
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_rx_arc.vhd
Info: Found design unit 1: rs232_rx-beh
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rs232_rx.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_rx.vhd
Info: Found entity 1: rs232_rx
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/writeback_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/writeback_stage_b.vhd
Info: Found design unit 1: writeback_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/writeback_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/writeback_stage.vhd
Info: Found entity 1: writeback_stage
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rw_r_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rw_r_ram_b.vhd
Info: Found design unit 1: rw_r_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rw_r_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rw_r_ram.vhd
Info: Found entity 1: rw_r_ram
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rs232_tx_arc.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_tx_arc.vhd
Info: Found design unit 1: rs232_tx-beh
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rs232_tx.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_tx.vhd
Info: Found entity 1: rs232_tx
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/r_w_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/r_w_ram_b.vhd
Info: Found design unit 1: r_w_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/r_w_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/r_w_ram.vhd
Info: Found entity 1: r_w_ram
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/r2_w_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/r2_w_ram_b.vhd
Info: Found design unit 1: r2_w_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/r2_w_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/r2_w_ram.vhd
Info: Found entity 1: r2_w_ram
-Info: Found 3 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/pipeline_tb.vhd
+Info: Found 3 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/pipeline_tb.vhd
Info: Found design unit 1: pipeline_tb-behavior
Info: Found design unit 2: pipeline_conf_beh
Info: Found entity 1: pipeline_tb
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/mem_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/mem_pkg.vhd
Info: Found design unit 1: mem_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/fetch_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
Info: Found design unit 1: fetch_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/fetch_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/fetch_stage.vhd
Info: Found entity 1: fetch_stage
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart_pkg.vhd
Info: Found design unit 1: extension_uart_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart_b.vhd
Info: Found design unit 1: extension_uart-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart.vhd
Info: Found entity 1: extension_uart
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_pkg.vhd
Info: Found design unit 1: extension_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_b.vhd
Info: Found design unit 1: extension_gpm-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/extension.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension.vhd
Info: Found entity 1: extension_gpm
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/execute_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/execute_stage_b.vhd
Info: Found design unit 1: execute_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/execute_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/execute_stage.vhd
Info: Found entity 1: execute_stage
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/exec_op.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op.vhd
Info: Found entity 1: exec_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/decoder_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/decoder_b.vhd
Info: Found design unit 1: decoder-behav_d
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/decoder.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/decoder.vhd
Info: Found entity 1: decoder
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/decode_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/decode_stage_b.vhd
Info: Found design unit 1: decode_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/decode_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/decode_stage.vhd
Info: Found entity 1: decode_stage
-Info: Found 2 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/core_top.vhd
+Info: Found 2 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/core_top.vhd
Info: Found design unit 1: core_top-behav
Info: Found entity 1: core_top
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/core_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/core_pkg.vhd
Info: Found design unit 1: core_pkg
-Info: Found 2 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/common_pkg.vhd
+Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/common_pkg.vhd
Info: Found design unit 1: common_pkg
Info: Found design unit 2: common_pkg-body
-Info: Found 2 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/alu_pkg.vhd
+Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/alu_pkg.vhd
Info: Found design unit 1: alu_pkg
Info: Found design unit 2: alu_pkg-body
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/alu_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/alu_b.vhd
Info: Found design unit 1: alu-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/alu.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/alu.vhd
Info: Found entity 1: alu
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/xor_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/xor_op_b.vhd
Info: Found design unit 1: exec_op-xor_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/shift_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/shift_op_b.vhd
Info: Found design unit 1: exec_op-shift_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/or_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/or_op_b.vhd
Info: Found design unit 1: exec_op-or_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/and_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/and_op_b.vhd
Info: Found design unit 1: exec_op-and_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/add_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/add_op_b.vhd
Info: Found design unit 1: exec_op-add_op
Info: Elaborating entity "core_top" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(25): object "jump_result" assigned a value but never read
-Warning (10541): VHDL Signal Declaration warning at core_top.vhd(53): used implicit default value for signal "gpm_in_pin" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(54): object "gpm_out_pin" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(31): object "jump_result" assigned a value but never read
+Warning (10541): VHDL Signal Declaration warning at core_top.vhd(59): used implicit default value for signal "gpm_in_pin" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(60): object "gpm_out_pin" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(63): object "vers" assigned a value but never read
Info: Elaborating entity "fetch_stage" for hierarchy "fetch_stage:fetch_st"
Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(11): used implicit default value for signal "instr_w_addr" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(14): used implicit default value for signal "instr_we" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(15): used implicit default value for signal "instr_wr_data" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Info: Elaborating entity "r_w_ram" for hierarchy "fetch_stage:fetch_st|r_w_ram:instruction_ram"
-Warning (10036): Verilog HDL or VHDL warning at r_w_ram_b.vhd(15): object "ram" assigned a value but never read
+Info: Elaborating entity "rom" for hierarchy "fetch_stage:fetch_st|rom:instruction_ram"
Info: Elaborating entity "decode_stage" for hierarchy "decode_stage:decode_st"
Info: Elaborating entity "r2_w_ram" for hierarchy "decode_stage:decode_st|r2_w_ram:register_ram"
Info: Elaborating entity "decoder" for hierarchy "decode_stage:decode_st|decoder:decoder_inst"
Info: Elaborating entity "exec_op" using architecture "A:shift_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
Info: Elaborating entity "extension_gpm" for hierarchy "execute_stage:exec_st|extension_gpm:gpmp_inst"
Info: Elaborating entity "writeback_stage" for hierarchy "writeback_stage:writeback_st"
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(14): object "data_ram_read_ext" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(19): object "ext_timer" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(19): object "ext_gpmp" assigned a value but never read
-Warning (10812): VHDL warning at writeback_stage_b.vhd(164): sensitivity list already contains wb_reg_nxt
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(20): object "ext_timer" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(20): object "ext_gpmp" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(25): object "calc_mem_res" assigned a value but never read
+Info: Elaborating entity "r_w_ram" for hierarchy "writeback_stage:writeback_st|r_w_ram:data_ram"
Info: Elaborating entity "extension_uart" for hierarchy "writeback_stage:writeback_st|extension_uart:uart"
-Warning (10036): Verilog HDL or VHDL warning at extension_uart_b.vhd(15): object "new_bus_rx" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at extension_uart_b.vhd(17): object "rx_data" assigned a value but never read
Info: Elaborating entity "rs232_tx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst"
Info: Elaborating entity "rs232_rx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst"
-Info: Inferred 2 megafunctions from design logic
+Info: Elaborating entity "extension_7seg" for hierarchy "writeback_stage:writeback_st|extension_7seg:sseg"
+Info: Inferred 3 megafunctions from design logic
+ Info: Inferred altsyncram megafunction from the following design logic: "writeback_stage:writeback_st|r_w_ram:data_ram|ram~44"
+ Info: Parameter OPERATION_MODE set to DUAL_PORT
+ Info: Parameter WIDTH_A set to 32
+ Info: Parameter WIDTHAD_A set to 11
+ Info: Parameter NUMWORDS_A set to 2048
+ Info: Parameter WIDTH_B set to 32
+ Info: Parameter WIDTHAD_B set to 11
+ Info: Parameter NUMWORDS_B set to 2048
+ Info: Parameter ADDRESS_ACLR_A set to NONE
+ Info: Parameter OUTDATA_REG_B set to UNREGISTERED
+ Info: Parameter ADDRESS_ACLR_B set to NONE
+ Info: Parameter OUTDATA_ACLR_B set to NONE
+ Info: Parameter ADDRESS_REG_B set to CLOCK0
+ Info: Parameter INDATA_ACLR_A set to NONE
+ Info: Parameter WRCONTROL_ACLR_A set to NONE
+ Info: Parameter INIT_FILE set to db/dt.ram0_r_w_ram_1e9198d1.hdl.mif
+ Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info: Inferred altsyncram megafunction from the following design logic: "decode_stage:decode_st|r2_w_ram:register_ram|ram~37"
Info: Parameter OPERATION_MODE set to DUAL_PORT
Info: Parameter WIDTH_A set to 32
Info: Parameter WRCONTROL_ACLR_A set to NONE
Info: Parameter INIT_FILE set to db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif
Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
-Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0"
-Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0" with the following parameter:
+Info: Elaborated megafunction instantiation "writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0"
+Info: Instantiated megafunction "writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0" with the following parameter:
Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
Info: Parameter "WIDTH_A" = "32"
- Info: Parameter "WIDTHAD_A" = "4"
- Info: Parameter "NUMWORDS_A" = "16"
+ Info: Parameter "WIDTHAD_A" = "11"
+ Info: Parameter "NUMWORDS_A" = "2048"
Info: Parameter "WIDTH_B" = "32"
- Info: Parameter "WIDTHAD_B" = "4"
- Info: Parameter "NUMWORDS_B" = "16"
+ Info: Parameter "WIDTHAD_B" = "11"
+ Info: Parameter "NUMWORDS_B" = "2048"
Info: Parameter "ADDRESS_ACLR_A" = "NONE"
Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info: Parameter "ADDRESS_ACLR_B" = "NONE"
Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
Info: Parameter "INDATA_ACLR_A" = "NONE"
Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
- Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
+ Info: Parameter "INIT_FILE" = "db/dt.ram0_r_w_ram_1e9198d1.hdl.mif"
Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_emk1.tdf
- Info: Found entity 1: altsyncram_emk1
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_grk1.tdf
+ Info: Found entity 1: altsyncram_grk1
Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1"
Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1" with the following parameter:
Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_emk1.tdf
+ Info: Found entity 1: altsyncram_emk1
Info: Registers with preset signals will power-up high
-Info: 187 registers lost all their fanouts during netlist optimizations. The first 187 are displayed below.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign" lost all its fanouts during netlist optimizations.
+Info: 130 registers lost all their fanouts during netlist optimizations. The first 130 are displayed below.
+ Info: Register "writeback_stage:writeback_st|wb_reg.address[0]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|wb_reg.address[1]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.daddr[2]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.AND_OP" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[31]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[30]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[29]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[28]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[27]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[26]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[25]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[24]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[23]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[22]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[21]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[20]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[19]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[18]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[17]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[16]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[6]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[5]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[3]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[2]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[28]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[27]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[25]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[11]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[12]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[13]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[29]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[30]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[31]" lost all its fanouts during netlist optimizations.
-Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM"
-Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM"
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[31]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[30]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[29]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[28]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[27]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[26]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[18]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17]" lost all its fanouts during netlist optimizations.
Info: Generating hard_block partition "hard_block:auto_generated_inst"
-Info: Implemented 1210 device resources after synthesis - the final resource count might be different
- Info: Implemented 2 input pins
- Info: Implemented 1 output pins
- Info: Implemented 1143 logic cells
- Info: Implemented 64 RAM segments
-Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
- Info: Peak virtual memory: 268 megabytes
- Info: Processing ended: Fri Dec 17 12:26:49 2010
- Info: Elapsed time: 00:00:24
- Info: Total CPU time (on all processors): 00:00:22
+Info: Implemented 2007 device resources after synthesis - the final resource count might be different
+ Info: Implemented 3 input pins
+ Info: Implemented 29 output pins
+ Info: Implemented 1879 logic cells
+ Info: Implemented 96 RAM segments
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
+ Info: Peak virtual memory: 270 megabytes
+ Info: Processing ended: Sun Dec 19 20:36:26 2010
+ Info: Elapsed time: 00:00:14
+ Info: Total CPU time (on all processors): 00:00:13
-Analysis & Synthesis Status : Successful - Fri Dec 17 12:26:49 2010
+Analysis & Synthesis Status : Successful - Sun Dec 19 20:36:26 2010
Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
Revision Name : dt
Top-level Entity Name : core_top
Family : Cyclone
-Total logic elements : 1,143
-Total pins : 3
+Total logic elements : 1,879
+Total pins : 32
Total virtual pins : 0
-Total memory bits : 512
+Total memory bits : 66,560
Total PLLs : 0
RESERVED_INPUT : 14 : : : : 1 :
RESERVED_INPUT : 15 : : : : 1 :
RESERVED_INPUT : 16 : : : : 1 :
-RESERVED_INPUT : 17 : : : : 1 :
-RESERVED_INPUT : 18 : : : : 1 :
+bus_rx : 17 : input : 3.3-V LVCMOS : : 1 : N
+sseg1[0] : 18 : output : 3.3-V LVCMOS : : 1 : N
RESERVED_INPUT : 19 : : : : 1 :
-RESERVED_INPUT : 20 : : : : 1 :
-RESERVED_INPUT : 21 : : : : 1 :
+sseg2[4] : 20 : output : 3.3-V LVCMOS : : 1 : N
+sseg2[0] : 21 : output : 3.3-V LVCMOS : : 1 : N
VCCIO1 : 22 : power : : 3.3V : 1 :
-RESERVED_INPUT : 23 : : : : 1 :
+sseg3[3] : 23 : output : 3.3-V LVCMOS : : 1 : N
~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 24 : input : 3.3-V LVCMOS : : 1 : N
DATA0 : 25 : input : : : 1 :
nCONFIG : 26 : : : : 1 :
MSEL1 : 35 : : : : 1 :
DCLK : 36 : bidir : : : 1 :
~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 37 : input : 3.3-V LVCMOS : : 1 : N
-RESERVED_INPUT : 38 : : : : 1 :
-RESERVED_INPUT : 39 : : : : 1 :
+sseg3[2] : 38 : output : 3.3-V LVCMOS : : 1 : N
+sseg0[3] : 39 : output : 3.3-V LVCMOS : : 1 : N
GND : 40 : gnd : : : :
RESERVED_INPUT : 41 : : : : 1 :
sys_res : 42 : input : 3.3-V LVCMOS : : 1 : Y
GND : 80 : gnd : : : :
VCCINT : 81 : power : : 1.5V : :
RESERVED_INPUT : 82 : : : : 4 :
-RESERVED_INPUT : 83 : : : : 4 :
-RESERVED_INPUT : 84 : : : : 4 :
-RESERVED_INPUT : 85 : : : : 4 :
-RESERVED_INPUT : 86 : : : : 4 :
-RESERVED_INPUT : 87 : : : : 4 :
-RESERVED_INPUT : 88 : : : : 4 :
+sseg0[0] : 83 : output : 3.3-V LVCMOS : : 4 : N
+sseg3[1] : 84 : output : 3.3-V LVCMOS : : 4 : N
+sseg3[4] : 85 : output : 3.3-V LVCMOS : : 4 : N
+sseg0[1] : 86 : output : 3.3-V LVCMOS : : 4 : N
+sseg3[0] : 87 : output : 3.3-V LVCMOS : : 4 : N
+sseg0[5] : 88 : output : 3.3-V LVCMOS : : 4 : N
GND : 89 : gnd : : : :
VCCINT : 90 : power : : 1.5V : :
GND : 91 : gnd : : : :
VCCIO4 : 92 : power : : 3.3V : 4 :
-RESERVED_INPUT : 93 : : : : 4 :
-RESERVED_INPUT : 94 : : : : 4 :
-RESERVED_INPUT : 95 : : : : 4 :
+sseg1[1] : 93 : output : 3.3-V LVCMOS : : 4 : N
+sseg1[2] : 94 : output : 3.3-V LVCMOS : : 4 : N
+sseg1[6] : 95 : output : 3.3-V LVCMOS : : 4 : N
GND : 96 : gnd : : : :
VCCINT : 97 : power : : 1.5V : :
RESERVED_INPUT : 98 : : : : 4 :
RESERVED_INPUT : 141 : : : : 3 :
GND : 142 : gnd : : : :
RESERVED_INPUT : 143 : : : : 3 :
-RESERVED_INPUT : 144 : : : : 3 :
+sseg0[2] : 144 : output : 3.3-V LVCMOS : : 3 : N
CONF_DONE : 145 : : : : 3 :
nSTATUS : 146 : : : : 3 :
TCK : 147 : input : : : 3 :
VCCIO3 : 157 : power : : 3.3V : 3 :
RESERVED_INPUT : 158 : : : : 3 :
RESERVED_INPUT : 159 : : : : 3 :
-RESERVED_INPUT : 160 : : : : 3 :
-RESERVED_INPUT : 161 : : : : 3 :
-RESERVED_INPUT : 162 : : : : 3 :
+sseg2[6] : 160 : output : 3.3-V LVCMOS : : 3 : N
+sseg2[2] : 161 : output : 3.3-V LVCMOS : : 3 : N
+sseg1[3] : 162 : output : 3.3-V LVCMOS : : 3 : N
RESERVED_INPUT : 163 : : : : 3 :
RESERVED_INPUT : 164 : : : : 3 :
RESERVED_INPUT : 165 : : : : 3 :
RESERVED_INPUT : 197 : : : : 2 :
VCCINT : 198 : power : : 1.5V : :
GND : 199 : gnd : : : :
-RESERVED_INPUT : 200 : : : : 2 :
-RESERVED_INPUT : 201 : : : : 2 :
-RESERVED_INPUT : 202 : : : : 2 :
+sseg2[5] : 200 : output : 3.3-V LVCMOS : : 2 : N
+sseg2[1] : 201 : output : 3.3-V LVCMOS : : 2 : N
+sseg2[3] : 202 : output : 3.3-V LVCMOS : : 2 : N
RESERVED_INPUT : 203 : : : : 2 :
VCCINT : 204 : power : : 1.5V : :
GND : 205 : gnd : : : :
-RESERVED_INPUT : 206 : : : : 2 :
-RESERVED_INPUT : 207 : : : : 2 :
+sseg1[5] : 206 : output : 3.3-V LVCMOS : : 2 : N
+sseg1[4] : 207 : output : 3.3-V LVCMOS : : 2 : N
RESERVED_INPUT : 208 : : : : 2 :
VCCIO2 : 209 : power : : 3.3V : 2 :
GND : 210 : gnd : : : :
VCCINT : 211 : power : : 1.5V : :
GND : 212 : gnd : : : :
-RESERVED_INPUT : 213 : : : : 2 :
-RESERVED_INPUT : 214 : : : : 2 :
-RESERVED_INPUT : 215 : : : : 2 :
-RESERVED_INPUT : 216 : : : : 2 :
+sseg0[4] : 213 : output : 3.3-V LVCMOS : : 2 : N
+sseg0[6] : 214 : output : 3.3-V LVCMOS : : 2 : N
+sseg3[5] : 215 : output : 3.3-V LVCMOS : : 2 : N
+sseg3[6] : 216 : output : 3.3-V LVCMOS : : 2 : N
RESERVED_INPUT : 217 : : : : 2 :
RESERVED_INPUT : 218 : : : : 2 :
RESERVED_INPUT : 219 : : : : 2 :
set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
set_location_assignment PIN_42 -to sys_res
+set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx_arc.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd
Classic Timing Analyzer report for dt
-Fri Dec 17 12:27:19 2010
+Sun Dec 19 20:36:51 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Timing Analyzer Summary ;
-+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
-; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
-+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
-; Worst-case tsu ; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; -- ; sys_clk ; 0 ;
-; Worst-case tco ; N/A ; None ; 10.165 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
-; Worst-case th ; N/A ; None ; -8.849 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; -- ; sys_clk ; 0 ;
-; Clock Setup: 'sys_clk' ; N/A ; None ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
-; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
-+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+--------------+
+; Worst-case tsu ; N/A ; None ; 18.145 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; -- ; sys_clk ; 0 ;
+; Worst-case tco ; N/A ; None ; 10.677 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -5.628 ns ; bus_rx ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; -- ; sys_clk ; 0 ;
+; Clock Setup: 'sys_clk' ; N/A ; None ; 36.95 MHz ( period = 27.067 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------+----------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------+--------+
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clock Setup: 'sys_clk' ;
-+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
-; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
-+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
-; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
-; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
-; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
-; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
-; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
-; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
-; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
-; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
-; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
-; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
-; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
-; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
-; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
-; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
-; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
-; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
-; N/A ; 47.19 MHz ( period = 21.190 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.929 ns ;
-; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
-; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
-; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
-; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
-; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
-; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
-; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
-; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
-; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
-; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
-; N/A ; 47.64 MHz ( period = 20.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.729 ns ;
-; N/A ; 47.81 MHz ( period = 20.918 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.657 ns ;
-; N/A ; 48.27 MHz ( period = 20.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.457 ns ;
-; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
-; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
-; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
-; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
-; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
-; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
-; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
-; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
-; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
-; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
-; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
-; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
-; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
-; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
-; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
-; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
-; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
-; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
-; N/A ; 49.46 MHz ( period = 20.220 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.959 ns ;
-; N/A ; 49.46 MHz ( period = 20.219 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.958 ns ;
-; N/A ; 49.47 MHz ( period = 20.213 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.952 ns ;
-; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
-; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
-; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
-; N/A ; 49.49 MHz ( period = 20.206 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.878 ns ;
-; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
-; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
-; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
-; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
-; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
-; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
-; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
-; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
-; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
-; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
-; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
-; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
-; N/A ; 49.71 MHz ( period = 20.118 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.866 ns ;
-; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
-; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
-; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
-; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
-; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
-; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
-; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
-; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
-; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
-; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
-; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
-; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
-; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
-; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
-; N/A ; 50.14 MHz ( period = 19.943 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.691 ns ;
-; N/A ; 50.17 MHz ( period = 19.931 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.670 ns ;
-; N/A ; 50.21 MHz ( period = 19.918 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.657 ns ;
-; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
-; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
-; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
-; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
-; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
-; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
-; N/A ; 50.28 MHz ( period = 19.888 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.627 ns ;
-; N/A ; 50.28 MHz ( period = 19.887 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.626 ns ;
-; N/A ; 50.30 MHz ( period = 19.881 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.620 ns ;
-; N/A ; 50.32 MHz ( period = 19.874 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.546 ns ;
-; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
-; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
-; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
-; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
-; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
-; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
-; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
-; N/A ; 50.36 MHz ( period = 19.859 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.598 ns ;
-; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
-; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
-; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
-; N/A ; 50.58 MHz ( period = 19.772 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.511 ns ;
-; N/A ; 50.58 MHz ( period = 19.770 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.500 ns ;
-; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
-; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
-; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
-; N/A ; 50.68 MHz ( period = 19.731 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.470 ns ;
-; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 50.72 MHz ( period = 19.718 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.457 ns ;
-; N/A ; 50.72 MHz ( period = 19.717 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.456 ns ;
-; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
-; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
-; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
-; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
-; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
-; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
-; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
-; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
-; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
-; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
-; N/A ; 50.78 MHz ( period = 19.691 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.363 ns ;
-; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
-; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
-; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
-; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
-; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
-; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
-; N/A ; 50.90 MHz ( period = 19.648 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.387 ns ;
-; N/A ; 50.95 MHz ( period = 19.628 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.367 ns ;
-; N/A ; 50.97 MHz ( period = 19.621 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 19.360 ns ;
-; N/A ; 50.99 MHz ( period = 19.613 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.352 ns ;
-; N/A ; 51.05 MHz ( period = 19.587 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.326 ns ;
-; N/A ; 51.10 MHz ( period = 19.570 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.300 ns ;
-; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
-; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
-; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
-; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
-; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
-; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
-; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
-; N/A ; 51.44 MHz ( period = 19.440 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.179 ns ;
-; N/A ; 51.47 MHz ( period = 19.428 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.167 ns ;
-; N/A ; 51.51 MHz ( period = 19.413 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.152 ns ;
-; N/A ; 51.55 MHz ( period = 19.400 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[7] ; sys_clk ; sys_clk ; None ; None ; 18.639 ns ;
-; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
-+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'sys_clk' ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; N/A ; 36.95 MHz ( period = 27.067 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 26.747 ns ;
+; N/A ; 38.35 MHz ( period = 26.075 ns ) ; writeback_stage:writeback_st|wb_reg.address[3] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 25.790 ns ;
+; N/A ; 39.35 MHz ( period = 25.412 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 25.151 ns ;
+; N/A ; 39.69 MHz ( period = 25.193 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 24.873 ns ;
+; N/A ; 39.79 MHz ( period = 25.134 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 24.805 ns ;
+; N/A ; 39.86 MHz ( period = 25.086 ns ) ; writeback_stage:writeback_st|wb_reg.address[2] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.801 ns ;
+; N/A ; 39.87 MHz ( period = 25.079 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 24.759 ns ;
+; N/A ; 39.91 MHz ( period = 25.059 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.798 ns ;
+; N/A ; 40.12 MHz ( period = 24.928 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.667 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.16 MHz ( period = 24.899 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.205 ns ;
+; N/A ; 40.19 MHz ( period = 24.883 ns ) ; writeback_stage:writeback_st|wb_reg.address[17] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.622 ns ;
+; N/A ; 40.19 MHz ( period = 24.882 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.621 ns ;
+; N/A ; 40.19 MHz ( period = 24.881 ns ) ; writeback_stage:writeback_st|wb_reg.address[28] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.620 ns ;
+; N/A ; 40.22 MHz ( period = 24.866 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.605 ns ;
+; N/A ; 40.37 MHz ( period = 24.770 ns ) ; writeback_stage:writeback_st|wb_reg.address[22] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.509 ns ;
+; N/A ; 40.40 MHz ( period = 24.750 ns ) ; writeback_stage:writeback_st|wb_reg.address[16] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.489 ns ;
+; N/A ; 40.46 MHz ( period = 24.718 ns ) ; writeback_stage:writeback_st|wb_reg.address[29] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.457 ns ;
+; N/A ; 40.48 MHz ( period = 24.704 ns ) ; writeback_stage:writeback_st|wb_reg.address[26] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.443 ns ;
+; N/A ; 40.49 MHz ( period = 24.697 ns ) ; writeback_stage:writeback_st|wb_reg.address[15] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.436 ns ;
+; N/A ; 40.53 MHz ( period = 24.674 ns ) ; writeback_stage:writeback_st|wb_reg.address[19] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.413 ns ;
+; N/A ; 40.65 MHz ( period = 24.598 ns ) ; writeback_stage:writeback_st|wb_reg.address[30] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.337 ns ;
+; N/A ; 40.67 MHz ( period = 24.590 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.329 ns ;
+; N/A ; 40.77 MHz ( period = 24.528 ns ) ; writeback_stage:writeback_st|wb_reg.address[27] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.267 ns ;
+; N/A ; 40.80 MHz ( period = 24.509 ns ) ; writeback_stage:writeback_st|wb_reg.address[14] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.248 ns ;
+; N/A ; 40.82 MHz ( period = 24.497 ns ) ; writeback_stage:writeback_st|wb_reg.address[5] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.245 ns ;
+; N/A ; 40.95 MHz ( period = 24.422 ns ) ; writeback_stage:writeback_st|wb_reg.address[25] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.161 ns ;
+; N/A ; 40.96 MHz ( period = 24.417 ns ) ; writeback_stage:writeback_st|wb_reg.address[6] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.156 ns ;
+; N/A ; 40.96 MHz ( period = 24.413 ns ) ; writeback_stage:writeback_st|wb_reg.address[31] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 24.152 ns ;
+; N/A ; 41.26 MHz ( period = 24.235 ns ) ; writeback_stage:writeback_st|wb_reg.address[8] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.974 ns ;
+; N/A ; 41.29 MHz ( period = 24.220 ns ) ; writeback_stage:writeback_st|wb_reg.address[24] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.959 ns ;
+; N/A ; 41.32 MHz ( period = 24.201 ns ) ; writeback_stage:writeback_st|wb_reg.address[3] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 23.916 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.32 MHz ( period = 24.200 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.515 ns ;
+; N/A ; 41.42 MHz ( period = 24.142 ns ) ; writeback_stage:writeback_st|wb_reg.address[3] ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 23.848 ns ;
+; N/A ; 41.52 MHz ( period = 24.087 ns ) ; writeback_stage:writeback_st|wb_reg.address[3] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.802 ns ;
+; N/A ; 41.60 MHz ( period = 24.039 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 23.743 ns ;
+; N/A ; 41.68 MHz ( period = 23.990 ns ) ; writeback_stage:writeback_st|wb_reg.address[4] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.729 ns ;
+; N/A ; 41.69 MHz ( period = 23.987 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.293 ns ;
+; N/A ; 41.69 MHz ( period = 23.987 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.293 ns ;
+; N/A ; 41.69 MHz ( period = 23.987 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.293 ns ;
+; N/A ; 41.69 MHz ( period = 23.987 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.293 ns ;
+; N/A ; 41.78 MHz ( period = 23.935 ns ) ; writeback_stage:writeback_st|wb_reg.address[13] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.674 ns ;
+; N/A ; 41.81 MHz ( period = 23.916 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 23.579 ns ;
+; N/A ; 41.85 MHz ( period = 23.896 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.514 ns ;
+; N/A ; 41.85 MHz ( period = 23.894 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[13] ; sys_clk ; sys_clk ; None ; None ; 23.633 ns ;
+; N/A ; 41.86 MHz ( period = 23.890 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.508 ns ;
+; N/A ; 41.90 MHz ( period = 23.867 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.552 ns ;
+; N/A ; 41.92 MHz ( period = 23.854 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.548 ns ;
+; N/A ; 41.93 MHz ( period = 23.847 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.461 ns ;
+; N/A ; 41.93 MHz ( period = 23.847 ns ) ; writeback_stage:writeback_st|wb_reg.address[10] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.586 ns ;
+; N/A ; 41.94 MHz ( period = 23.841 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.455 ns ;
+; N/A ; 41.95 MHz ( period = 23.839 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 23.510 ns ;
+; N/A ; 41.99 MHz ( period = 23.818 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.499 ns ;
+; N/A ; 42.01 MHz ( period = 23.805 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.495 ns ;
+; N/A ; 42.02 MHz ( period = 23.801 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a9~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.107 ns ;
+; N/A ; 42.02 MHz ( period = 23.801 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a9~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.107 ns ;
+; N/A ; 42.02 MHz ( period = 23.801 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a9~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.107 ns ;
+; N/A ; 42.02 MHz ( period = 23.801 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a9~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.107 ns ;
+; N/A ; 42.06 MHz ( period = 23.773 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.467 ns ;
+; N/A ; 42.07 MHz ( period = 23.771 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[18] ; sys_clk ; sys_clk ; None ; None ; 23.475 ns ;
+; N/A ; 42.07 MHz ( period = 23.771 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.456 ns ;
+; N/A ; 42.10 MHz ( period = 23.755 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.494 ns ;
+; N/A ; 42.11 MHz ( period = 23.748 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 23.487 ns ;
+; N/A ; 42.15 MHz ( period = 23.722 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.403 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.17 MHz ( period = 23.715 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.19 MHz ( period = 23.701 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[11] ; sys_clk ; sys_clk ; None ; None ; 23.372 ns ;
+; N/A ; 42.31 MHz ( period = 23.634 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.373 ns ;
+; N/A ; 42.33 MHz ( period = 23.624 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.363 ns ;
+; N/A ; 42.36 MHz ( period = 23.609 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 23.289 ns ;
+; N/A ; 42.41 MHz ( period = 23.579 ns ) ; writeback_stage:writeback_st|wb_reg.address[17] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.318 ns ;
+; N/A ; 42.41 MHz ( period = 23.578 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.317 ns ;
+; N/A ; 42.41 MHz ( period = 23.577 ns ) ; writeback_stage:writeback_st|wb_reg.address[28] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.316 ns ;
+; N/A ; 42.47 MHz ( period = 23.545 ns ) ; writeback_stage:writeback_st|wb_reg.address[9] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.284 ns ;
+; N/A ; 42.54 MHz ( period = 23.508 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a6~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.261 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.56 MHz ( period = 23.495 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.742 ns ;
+; N/A ; 42.58 MHz ( period = 23.484 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.223 ns ;
+; N/A ; 42.59 MHz ( period = 23.479 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 23.209 ns ;
+; N/A ; 42.61 MHz ( period = 23.466 ns ) ; writeback_stage:writeback_st|wb_reg.address[22] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.205 ns ;
+; N/A ; 42.63 MHz ( period = 23.459 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a6~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.208 ns ;
+; N/A ; 42.64 MHz ( period = 23.451 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a19~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.169 ns ;
+; N/A ; 42.65 MHz ( period = 23.446 ns ) ; writeback_stage:writeback_st|wb_reg.address[16] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.185 ns ;
+; N/A ; 42.67 MHz ( period = 23.434 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 23.114 ns ;
+; N/A ; 42.69 MHz ( period = 23.427 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.117 ns ;
+; N/A ; 42.70 MHz ( period = 23.419 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[16] ; sys_clk ; sys_clk ; None ; None ; 23.099 ns ;
+; N/A ; 42.70 MHz ( period = 23.419 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.172 ns ;
+; N/A ; 42.71 MHz ( period = 23.414 ns ) ; writeback_stage:writeback_st|wb_reg.address[29] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.153 ns ;
+; N/A ; 42.72 MHz ( period = 23.408 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.089 ns ;
+; N/A ; 42.73 MHz ( period = 23.402 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a19~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.116 ns ;
+; N/A ; 42.73 MHz ( period = 23.402 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.087 ns ;
+; N/A ; 42.73 MHz ( period = 23.401 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.086 ns ;
+; N/A ; 42.74 MHz ( period = 23.400 ns ) ; writeback_stage:writeback_st|wb_reg.address[26] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.139 ns ;
+; N/A ; 42.74 MHz ( period = 23.398 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a12~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.151 ns ;
+; N/A ; 42.74 MHz ( period = 23.395 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a10~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.148 ns ;
+; N/A ; 42.75 MHz ( period = 23.394 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.012 ns ;
+; N/A ; 42.75 MHz ( period = 23.393 ns ) ; writeback_stage:writeback_st|wb_reg.address[15] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.132 ns ;
+; N/A ; 42.76 MHz ( period = 23.388 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.006 ns ;
+; N/A ; 42.78 MHz ( period = 23.375 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.060 ns ;
+; N/A ; 42.79 MHz ( period = 23.370 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.119 ns ;
+; N/A ; 42.80 MHz ( period = 23.365 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.050 ns ;
+; N/A ; 42.80 MHz ( period = 23.363 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_we_reg ; sys_clk ; sys_clk ; None ; None ; 22.981 ns ;
+; N/A ; 42.82 MHz ( period = 23.352 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.046 ns ;
+; N/A ; 42.83 MHz ( period = 23.350 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.968 ns ;
+; N/A ; 42.83 MHz ( period = 23.349 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a12~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.098 ns ;
+; N/A ; 42.83 MHz ( period = 23.346 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a10~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.095 ns ;
+; N/A ; 42.84 MHz ( period = 23.345 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.959 ns ;
+; N/A ; 42.84 MHz ( period = 23.344 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.962 ns ;
+; N/A ; 42.85 MHz ( period = 23.339 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.953 ns ;
+; N/A ; 42.85 MHz ( period = 23.335 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 23.015 ns ;
+; N/A ; 42.87 MHz ( period = 23.327 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 23.008 ns ;
+; N/A ; 42.87 MHz ( period = 23.326 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.007 ns ;
+; N/A ; 42.88 MHz ( period = 23.321 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_we_reg ; sys_clk ; sys_clk ; None ; None ; 23.006 ns ;
+; N/A ; 42.88 MHz ( period = 23.321 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.006 ns ;
+; N/A ; 42.89 MHz ( period = 23.317 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[25] ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.89 MHz ( period = 23.316 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.997 ns ;
+; N/A ; 42.90 MHz ( period = 23.308 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 23.002 ns ;
+; N/A ; 42.91 MHz ( period = 23.303 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.993 ns ;
+; N/A ; 42.92 MHz ( period = 23.301 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.915 ns ;
+; N/A ; 42.93 MHz ( period = 23.295 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.909 ns ;
+; N/A ; 42.93 MHz ( period = 23.294 ns ) ; writeback_stage:writeback_st|wb_reg.address[30] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 23.033 ns ;
+; N/A ; 42.97 MHz ( period = 23.272 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.953 ns ;
+; N/A ; 42.97 MHz ( period = 23.271 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 22.965 ns ;
+; N/A ; 42.98 MHz ( period = 23.269 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.954 ns ;
+; N/A ; 42.99 MHz ( period = 23.259 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.949 ns ;
+; N/A ; 43.00 MHz ( period = 23.254 ns ) ; writeback_stage:writeback_st|wb_reg.address[19] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 22.993 ns ;
+; N/A ; 43.00 MHz ( period = 23.254 ns ) ; writeback_stage:writeback_st|wb_reg.address[11] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.993 ns ;
+; N/A ; 43.01 MHz ( period = 23.248 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 22.928 ns ;
+; N/A ; 43.02 MHz ( period = 23.246 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 22.985 ns ;
+; N/A ; 43.05 MHz ( period = 23.227 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg0 ; sys_clk ; sys_clk ; None ; None ; 22.921 ns ;
+; N/A ; 43.06 MHz ( period = 23.225 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.910 ns ;
+; N/A ; 43.06 MHz ( period = 23.224 ns ) ; writeback_stage:writeback_st|wb_reg.address[27] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 22.963 ns ;
+; N/A ; 43.06 MHz ( period = 23.221 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.839 ns ;
+; N/A ; 43.07 MHz ( period = 23.220 ns ) ; writeback_stage:writeback_st|wb_reg.address[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.901 ns ;
+; N/A ; 43.08 MHz ( period = 23.215 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.833 ns ;
+; N/A ; 43.08 MHz ( period = 23.212 ns ) ; writeback_stage:writeback_st|wb_reg.address[2] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 22.927 ns ;
+; N/A ; 43.09 MHz ( period = 23.205 ns ) ; writeback_stage:writeback_st|wb_reg.address[14] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 22.944 ns ;
+; N/A ; 43.10 MHz ( period = 23.202 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; execute_stage:exec_st|reg.result[15] ; sys_clk ; sys_clk ; None ; None ; 22.941 ns ;
+; N/A ; 43.10 MHz ( period = 23.202 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~porta_address_reg4 ; sys_clk ; sys_clk ; None ; None ; 22.879 ns ;
+; N/A ; 43.10 MHz ( period = 23.201 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[7] ; sys_clk ; sys_clk ; None ; None ; 22.881 ns ;
+; N/A ; 43.11 MHz ( period = 23.198 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.816 ns ;
+; N/A ; 43.12 MHz ( period = 23.193 ns ) ; writeback_stage:writeback_st|wb_reg.address[5] ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 22.941 ns ;
+; N/A ; 43.12 MHz ( period = 23.192 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.810 ns ;
+; N/A ; 43.12 MHz ( period = 23.192 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.877 ns ;
+; N/A ; 43.13 MHz ( period = 23.184 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a21~porta_address_reg4 ; sys_clk ; sys_clk ; None ; None ; 22.861 ns ;
+; N/A ; 43.14 MHz ( period = 23.180 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 22.919 ns ;
+; N/A ; 43.14 MHz ( period = 23.179 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.873 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.14 MHz ( period = 23.178 ns ) ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; None ; None ; 22.501 ns ;
+; N/A ; 43.15 MHz ( period = 23.176 ns ) ; writeback_stage:writeback_st|wb_reg.address[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.857 ns ;
+; N/A ; 43.15 MHz ( period = 23.173 ns ) ; writeback_stage:writeback_st|wb_reg.address[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a21~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.850 ns ;
+; N/A ; 43.16 MHz ( period = 23.172 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.786 ns ;
+; N/A ; 43.16 MHz ( period = 23.169 ns ) ; writeback_stage:writeback_st|wb_reg.address[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.854 ns ;
+; N/A ; 43.17 MHz ( period = 23.166 ns ) ; writeback_stage:writeback_st|wb_reg.address[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; sys_clk ; sys_clk ; None ; None ; 22.780 ns ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
-+---------------------------------------------------------------------------------------------------------------------------+
-; tsu ;
-+-------+--------------+------------+---------+------------------------------------------------------------------+----------+
-; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
-+-------+--------------+------------+---------+------------------------------------------------------------------+----------+
-; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
-; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
-; N/A ; None ; 18.960 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
-; N/A ; None ; 18.960 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
-; N/A ; None ; 18.958 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ; sys_clk ;
-; N/A ; None ; 17.463 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
-; N/A ; None ; 16.832 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
-; N/A ; None ; 14.582 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
-; N/A ; None ; 14.522 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
-; N/A ; None ; 14.522 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
-; N/A ; None ; 14.521 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
-; N/A ; None ; 14.516 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
-; N/A ; None ; 14.493 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
-; N/A ; None ; 14.024 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
-; N/A ; None ; 13.946 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
-; N/A ; None ; 13.872 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
-; N/A ; None ; 13.847 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
-; N/A ; None ; 13.783 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
-; N/A ; None ; 13.783 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
-; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
-; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
-; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
-; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
-; N/A ; None ; 13.711 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
-; N/A ; None ; 13.711 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
-; N/A ; None ; 13.661 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
-; N/A ; None ; 13.515 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
-; N/A ; None ; 13.515 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
-; N/A ; None ; 13.480 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
-; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
-; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
-; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
-; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
-; N/A ; None ; 13.410 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
-; N/A ; None ; 13.394 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
-; N/A ; None ; 13.358 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
-; N/A ; None ; 13.319 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
-; N/A ; None ; 13.319 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
-; N/A ; None ; 13.239 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
-; N/A ; None ; 13.166 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
-; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
-; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
-; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
-; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
-; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
-; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
-; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
-; N/A ; None ; 13.121 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
-; N/A ; None ; 13.109 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
-; N/A ; None ; 13.015 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
-; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
-; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
-; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
-; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
-; N/A ; None ; 12.931 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
-; N/A ; None ; 12.853 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
-; N/A ; None ; 12.826 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
-; N/A ; None ; 12.762 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
-; N/A ; None ; 12.742 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
-; N/A ; None ; 12.687 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
-; N/A ; None ; 12.680 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
-; N/A ; None ; 12.550 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
-; N/A ; None ; 12.445 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
-; N/A ; None ; 12.418 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
-; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
-; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
-; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
-; N/A ; None ; 12.184 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
-; N/A ; None ; 12.152 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
-; N/A ; None ; 12.140 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
-; N/A ; None ; 12.139 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
-; N/A ; None ; 12.113 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
-; N/A ; None ; 12.113 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
-; N/A ; None ; 12.108 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
-; N/A ; None ; 11.975 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
-; N/A ; None ; 11.925 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
-; N/A ; None ; 11.648 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
-; N/A ; None ; 11.375 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
-; N/A ; None ; 11.324 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
-; N/A ; None ; 11.324 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
-; N/A ; None ; 11.234 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
-; N/A ; None ; 11.169 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
-; N/A ; None ; 11.158 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
-; N/A ; None ; 11.092 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
-; N/A ; None ; 10.824 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
-; N/A ; None ; 10.819 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
-; N/A ; None ; 10.809 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
-; N/A ; None ; 10.784 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
-; N/A ; None ; 10.648 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
-; N/A ; None ; 9.786 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
-; N/A ; None ; 9.782 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
-; N/A ; None ; 9.296 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
-; N/A ; None ; 9.295 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
-; N/A ; None ; 8.901 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
-+-------+--------------+------------+---------+------------------------------------------------------------------+----------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
+; N/A ; None ; 18.145 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ;
+; N/A ; None ; 18.070 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[1] ; sys_clk ;
+; N/A ; None ; 17.886 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[15] ; sys_clk ;
+; N/A ; None ; 17.811 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[7] ; sys_clk ;
+; N/A ; None ; 17.810 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; sys_clk ;
+; N/A ; None ; 17.809 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[5] ; sys_clk ;
+; N/A ; None ; 17.808 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[31] ; sys_clk ;
+; N/A ; None ; 17.807 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[17] ; sys_clk ;
+; N/A ; None ; 17.805 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[4] ; sys_clk ;
+; N/A ; None ; 17.802 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[16] ; sys_clk ;
+; N/A ; None ; 17.795 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[20] ; sys_clk ;
+; N/A ; None ; 17.790 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[21] ; sys_clk ;
+; N/A ; None ; 17.651 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[26] ; sys_clk ;
+; N/A ; None ; 17.651 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[19] ; sys_clk ;
+; N/A ; None ; 17.605 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[27] ; sys_clk ;
+; N/A ; None ; 17.604 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[23] ; sys_clk ;
+; N/A ; None ; 17.600 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[6] ; sys_clk ;
+; N/A ; None ; 17.598 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[24] ; sys_clk ;
+; N/A ; None ; 17.595 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[25] ; sys_clk ;
+; N/A ; None ; 17.141 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
+; N/A ; None ; 16.690 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_we_reg ; sys_clk ;
+; N/A ; None ; 16.648 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_we_reg ; sys_clk ;
+; N/A ; None ; 16.185 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_we_reg ; sys_clk ;
+; N/A ; None ; 16.144 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_we_reg ; sys_clk ;
+; N/A ; None ; 16.119 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.774 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a6~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.667 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
+; N/A ; None ; 15.650 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.623 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
+; N/A ; None ; 15.511 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.506 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a25~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.491 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a21~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.437 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a8~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.370 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a19~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.343 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a12~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.337 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.243 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a10~porta_we_reg ; sys_clk ;
+; N/A ; None ; 15.224 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
+; N/A ; None ; 15.223 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
+; N/A ; None ; 15.185 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
+; N/A ; None ; 14.915 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
+; N/A ; None ; 14.897 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~porta_we_reg ; sys_clk ;
+; N/A ; None ; 14.795 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
+; N/A ; None ; 14.407 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
+; N/A ; None ; 14.258 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
+; N/A ; None ; 14.258 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
+; N/A ; None ; 14.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
+; N/A ; None ; 14.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
+; N/A ; None ; 14.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
+; N/A ; None ; 14.112 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
+; N/A ; None ; 13.407 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
+; N/A ; None ; 13.406 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
+; N/A ; None ; 13.400 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
+; N/A ; None ; 13.400 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
+; N/A ; None ; 13.400 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
+; N/A ; None ; 13.320 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
+; N/A ; None ; 13.318 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
+; N/A ; None ; 13.316 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
+; N/A ; None ; 13.212 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
+; N/A ; None ; 13.097 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
+; N/A ; None ; 12.997 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
+; N/A ; None ; 12.997 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
+; N/A ; None ; 12.909 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
+; N/A ; None ; 12.909 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
+; N/A ; None ; 12.794 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
+; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
+; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
+; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
+; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
+; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
+; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
+; N/A ; None ; 12.776 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
+; N/A ; None ; 12.705 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
+; N/A ; None ; 12.661 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
+; N/A ; None ; 12.495 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
+; N/A ; None ; 12.360 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
+; N/A ; None ; 12.359 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
+; N/A ; None ; 12.357 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
+; N/A ; None ; 12.335 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
+; N/A ; None ; 12.335 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
+; N/A ; None ; 12.330 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
+; N/A ; None ; 12.330 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
+; N/A ; None ; 12.330 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
+; N/A ; None ; 12.307 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
+; N/A ; None ; 12.215 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
+; N/A ; None ; 12.114 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
+; N/A ; None ; 12.113 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
+; N/A ; None ; 12.112 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
+; N/A ; None ; 12.105 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
+; N/A ; None ; 12.084 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
+; N/A ; None ; 12.084 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
+; N/A ; None ; 12.072 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
+; N/A ; None ; 12.019 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
+; N/A ; None ; 11.981 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
+; N/A ; None ; 11.974 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
+; N/A ; None ; 11.971 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
+; N/A ; None ; 11.937 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
+; N/A ; None ; 11.787 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
+; N/A ; None ; 11.158 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
+; N/A ; None ; 11.054 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
+; N/A ; None ; 10.345 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
+; N/A ; None ; 10.180 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
+; N/A ; None ; 10.094 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
+; N/A ; None ; 10.094 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
+; N/A ; None ; 9.929 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
+; N/A ; None ; 9.926 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
+; N/A ; None ; 9.926 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
+; N/A ; None ; 9.904 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
+; N/A ; None ; 9.903 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
+; N/A ; None ; 9.873 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0] ; sys_clk ;
+; N/A ; None ; 9.605 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6] ; sys_clk ;
+; N/A ; None ; 9.403 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
+; N/A ; None ; 9.340 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
+; N/A ; None ; 9.338 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
+; N/A ; None ; 9.259 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7] ; sys_clk ;
+; N/A ; None ; 9.257 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2] ; sys_clk ;
+; N/A ; None ; 9.012 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
+; N/A ; None ; 8.582 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5] ; sys_clk ;
+; N/A ; None ; 7.904 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; sys_clk ;
+; N/A ; None ; 7.904 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; sys_clk ;
+; N/A ; None ; 6.963 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3] ; sys_clk ;
+; N/A ; None ; 6.869 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1] ; sys_clk ;
+; N/A ; None ; 6.867 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4] ; sys_clk ;
+; N/A ; None ; 5.680 ns ; bus_rx ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; sys_clk ;
++-------+--------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; tco ;
-+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
-; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
-+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
-; N/A ; None ; 10.165 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
-+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; tco ;
++-------+--------------+------------+------------------------------------------------------------------------------------+----------+------------+
+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
++-------+--------------+------------+------------------------------------------------------------------------------------+----------+------------+
+; N/A ; None ; 10.677 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
+; N/A ; None ; 10.627 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[2] ; sseg0[2] ; sys_clk ;
+; N/A ; None ; 9.877 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[1] ; sseg1[1] ; sys_clk ;
+; N/A ; None ; 9.406 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[0] ; sseg2[0] ; sys_clk ;
+; N/A ; None ; 9.395 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[4] ; sseg2[4] ; sys_clk ;
+; N/A ; None ; 9.182 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[6] ; sseg1[6] ; sys_clk ;
+; N/A ; None ; 9.091 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[2] ; sseg1[2] ; sys_clk ;
+; N/A ; None ; 9.079 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[0] ; sseg1[0] ; sys_clk ;
+; N/A ; None ; 8.940 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[3] ; sseg1[3] ; sys_clk ;
+; N/A ; None ; 8.778 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6] ; sseg0[6] ; sys_clk ;
+; N/A ; None ; 8.704 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[2] ; sseg2[2] ; sys_clk ;
+; N/A ; None ; 8.694 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[3] ; sseg3[3] ; sys_clk ;
+; N/A ; None ; 8.693 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[2] ; sseg3[2] ; sys_clk ;
+; N/A ; None ; 8.684 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[6] ; sseg2[6] ; sys_clk ;
+; N/A ; None ; 8.663 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[4] ; sseg0[4] ; sys_clk ;
+; N/A ; None ; 8.607 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[1] ; sseg3[1] ; sys_clk ;
+; N/A ; None ; 8.606 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[5] ; sseg3[5] ; sys_clk ;
+; N/A ; None ; 8.605 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[4] ; sseg3[4] ; sys_clk ;
+; N/A ; None ; 8.592 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[3] ; sseg0[3] ; sys_clk ;
+; N/A ; None ; 8.503 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[6] ; sseg3[6] ; sys_clk ;
+; N/A ; None ; 8.484 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[1] ; sseg0[1] ; sys_clk ;
+; N/A ; None ; 8.475 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[0] ; sseg0[0] ; sys_clk ;
+; N/A ; None ; 8.230 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[5] ; sseg0[5] ; sys_clk ;
+; N/A ; None ; 8.188 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[0] ; sseg3[0] ; sys_clk ;
+; N/A ; None ; 7.759 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[5] ; sseg2[5] ; sys_clk ;
+; N/A ; None ; 7.360 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[3] ; sseg2[3] ; sys_clk ;
+; N/A ; None ; 7.356 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[1] ; sseg2[1] ; sys_clk ;
+; N/A ; None ; 7.295 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[4] ; sseg1[4] ; sys_clk ;
+; N/A ; None ; 7.293 ns ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[5] ; sseg1[5] ; sys_clk ;
++-------+--------------+------------+------------------------------------------------------------------------------------+----------+------------+
-+----------------------------------------------------------------------------------------------------------------------------------+
-; th ;
-+---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
-; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
-+---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
-; N/A ; None ; -8.849 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
-; N/A ; None ; -9.173 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
-; N/A ; None ; -9.243 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
-; N/A ; None ; -9.244 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
-; N/A ; None ; -9.730 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
-; N/A ; None ; -9.734 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
-; N/A ; None ; -10.596 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
-; N/A ; None ; -10.732 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
-; N/A ; None ; -10.757 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
-; N/A ; None ; -10.767 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
-; N/A ; None ; -10.772 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
-; N/A ; None ; -11.019 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
-; N/A ; None ; -11.020 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ; sys_clk ;
-; N/A ; None ; -11.021 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
-; N/A ; None ; -11.021 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
-; N/A ; None ; -11.040 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
-; N/A ; None ; -11.106 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
-; N/A ; None ; -11.117 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
-; N/A ; None ; -11.182 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
-; N/A ; None ; -11.272 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
-; N/A ; None ; -11.272 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
-; N/A ; None ; -11.323 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
-; N/A ; None ; -11.327 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
-; N/A ; None ; -11.596 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
-; N/A ; None ; -11.873 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
-; N/A ; None ; -11.923 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
-; N/A ; None ; -12.056 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
-; N/A ; None ; -12.061 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
-; N/A ; None ; -12.061 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
-; N/A ; None ; -12.087 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
-; N/A ; None ; -12.088 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
-; N/A ; None ; -12.100 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
-; N/A ; None ; -12.132 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
-; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
-; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
-; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
-; N/A ; None ; -12.366 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
-; N/A ; None ; -12.393 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
-; N/A ; None ; -12.498 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
-; N/A ; None ; -12.628 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
-; N/A ; None ; -12.635 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
-; N/A ; None ; -12.690 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
-; N/A ; None ; -12.710 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
-; N/A ; None ; -12.730 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
-; N/A ; None ; -12.774 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
-; N/A ; None ; -12.801 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
-; N/A ; None ; -12.879 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
-; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
-; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
-; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
-; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
-; N/A ; None ; -12.963 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
-; N/A ; None ; -13.057 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
-; N/A ; None ; -13.069 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
-; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
-; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
-; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
-; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
-; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
-; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
-; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
-; N/A ; None ; -13.114 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
-; N/A ; None ; -13.187 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
-; N/A ; None ; -13.267 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
-; N/A ; None ; -13.267 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
-; N/A ; None ; -13.306 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
-; N/A ; None ; -13.342 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
-; N/A ; None ; -13.358 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
-; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
-; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
-; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
-; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
-; N/A ; None ; -13.428 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
-; N/A ; None ; -13.463 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
-; N/A ; None ; -13.463 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
-; N/A ; None ; -13.609 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
-; N/A ; None ; -13.659 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
-; N/A ; None ; -13.659 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
-; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
-; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
-; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
-; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
-; N/A ; None ; -13.731 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
-; N/A ; None ; -13.731 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
-; N/A ; None ; -13.795 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
-; N/A ; None ; -13.820 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
-; N/A ; None ; -13.894 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
-; N/A ; None ; -14.441 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
-; N/A ; None ; -14.464 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
-; N/A ; None ; -14.469 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
-; N/A ; None ; -14.470 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
-; N/A ; None ; -14.470 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
-; N/A ; None ; -14.530 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
-; N/A ; None ; -15.539 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
-+---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
+; N/A ; None ; -5.628 ns ; bus_rx ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; sys_clk ;
+; N/A ; None ; -6.815 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4] ; sys_clk ;
+; N/A ; None ; -6.817 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1] ; sys_clk ;
+; N/A ; None ; -6.911 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3] ; sys_clk ;
+; N/A ; None ; -7.852 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; sys_clk ;
+; N/A ; None ; -7.852 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; sys_clk ;
+; N/A ; None ; -8.530 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5] ; sys_clk ;
+; N/A ; None ; -8.960 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
+; N/A ; None ; -9.205 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2] ; sys_clk ;
+; N/A ; None ; -9.207 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7] ; sys_clk ;
+; N/A ; None ; -9.286 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
+; N/A ; None ; -9.288 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
+; N/A ; None ; -9.351 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
+; N/A ; None ; -9.553 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6] ; sys_clk ;
+; N/A ; None ; -9.821 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0] ; sys_clk ;
+; N/A ; None ; -9.851 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
+; N/A ; None ; -9.852 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
+; N/A ; None ; -9.874 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
+; N/A ; None ; -9.874 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
+; N/A ; None ; -9.877 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
+; N/A ; None ; -10.042 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
+; N/A ; None ; -10.042 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
+; N/A ; None ; -10.128 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
+; N/A ; None ; -10.293 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
+; N/A ; None ; -11.002 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
+; N/A ; None ; -11.106 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
+; N/A ; None ; -11.409 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[23] ; sys_clk ;
+; N/A ; None ; -11.410 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[25] ; sys_clk ;
+; N/A ; None ; -11.410 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[27] ; sys_clk ;
+; N/A ; None ; -11.412 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[24] ; sys_clk ;
+; N/A ; None ; -11.413 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[6] ; sys_clk ;
+; N/A ; None ; -11.494 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[15] ; sys_clk ;
+; N/A ; None ; -11.528 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; sys_clk ;
+; N/A ; None ; -11.529 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[7] ; sys_clk ;
+; N/A ; None ; -11.532 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[5] ; sys_clk ;
+; N/A ; None ; -11.536 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[31] ; sys_clk ;
+; N/A ; None ; -11.539 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[17] ; sys_clk ;
+; N/A ; None ; -11.541 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[4] ; sys_clk ;
+; N/A ; None ; -11.542 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[16] ; sys_clk ;
+; N/A ; None ; -11.544 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[20] ; sys_clk ;
+; N/A ; None ; -11.545 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[21] ; sys_clk ;
+; N/A ; None ; -11.583 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[19] ; sys_clk ;
+; N/A ; None ; -11.585 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[26] ; sys_clk ;
+; N/A ; None ; -11.735 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
+; N/A ; None ; -11.885 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
+; N/A ; None ; -11.919 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
+; N/A ; None ; -11.922 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
+; N/A ; None ; -11.929 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
+; N/A ; None ; -11.967 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
+; N/A ; None ; -12.020 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
+; N/A ; None ; -12.032 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
+; N/A ; None ; -12.032 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
+; N/A ; None ; -12.053 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
+; N/A ; None ; -12.060 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
+; N/A ; None ; -12.061 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
+; N/A ; None ; -12.062 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
+; N/A ; None ; -12.163 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
+; N/A ; None ; -12.255 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
+; N/A ; None ; -12.278 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
+; N/A ; None ; -12.278 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
+; N/A ; None ; -12.278 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
+; N/A ; None ; -12.283 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
+; N/A ; None ; -12.283 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
+; N/A ; None ; -12.305 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
+; N/A ; None ; -12.307 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
+; N/A ; None ; -12.308 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
+; N/A ; None ; -12.443 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
+; N/A ; None ; -12.609 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
+; N/A ; None ; -12.653 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
+; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
+; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
+; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
+; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
+; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
+; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
+; N/A ; None ; -12.724 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
+; N/A ; None ; -12.742 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
+; N/A ; None ; -12.857 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
+; N/A ; None ; -12.857 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
+; N/A ; None ; -12.945 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
+; N/A ; None ; -12.945 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
+; N/A ; None ; -13.045 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
+; N/A ; None ; -13.160 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
+; N/A ; None ; -13.264 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
+; N/A ; None ; -13.266 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
+; N/A ; None ; -13.268 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
+; N/A ; None ; -13.348 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
+; N/A ; None ; -13.348 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
+; N/A ; None ; -13.348 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
+; N/A ; None ; -13.354 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
+; N/A ; None ; -13.355 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
+; N/A ; None ; -13.682 ns ; sys_res ; fetch_stage:fetch_st|rom:instruction_ram|data_out[1] ; sys_clk ;
+; N/A ; None ; -14.060 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
+; N/A ; None ; -14.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
+; N/A ; None ; -14.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
+; N/A ; None ; -14.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
+; N/A ; None ; -14.206 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
+; N/A ; None ; -14.206 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
+; N/A ; None ; -14.355 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
+; N/A ; None ; -14.743 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
+; N/A ; None ; -14.749 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a20~porta_we_reg ; sys_clk ;
+; N/A ; None ; -14.863 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
+; N/A ; None ; -15.095 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a10~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.133 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
+; N/A ; None ; -15.171 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
+; N/A ; None ; -15.172 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
+; N/A ; None ; -15.189 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a30~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.195 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a12~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.222 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a19~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.289 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a8~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.343 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a21~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.358 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a25~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.363 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a14~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.502 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a2~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.571 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
+; N/A ; None ; -15.615 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
+; N/A ; None ; -15.626 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a6~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.971 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a3~porta_we_reg ; sys_clk ;
+; N/A ; None ; -15.996 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a29~porta_we_reg ; sys_clk ;
+; N/A ; None ; -16.037 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a24~porta_we_reg ; sys_clk ;
+; N/A ; None ; -16.500 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a7~porta_we_reg ; sys_clk ;
+; N/A ; None ; -16.542 ns ; sys_res ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ram_block1a16~porta_we_reg ; sys_clk ;
+; N/A ; None ; -17.089 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
+; N/A ; None ; -18.093 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ;
++---------------+-------------+------------+---------+------------------------------------------------------------------------------------------------------------------------------+----------+
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 12:27:18 2010
+ Info: Processing started: Sun Dec 19 20:36:50 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "sys_clk" is an undefined clock
-Info: Clock "sys_clk" has Internal fmax of 46.34 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]" (period= 21.578 ns)
- Info: + Longest memory to register delay is 20.884 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y14; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a7'
- Info: 3: + IC(1.221 ns) + CELL(0.114 ns) = 5.652 ns; Loc. = LC_X35_Y16_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|right_operand[7]~17'
- Info: 4: + IC(1.274 ns) + CELL(0.114 ns) = 7.040 ns; Loc. = LC_X36_Y15_N7; Fanout = 4; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~COMBOUT'
- Info: 5: + IC(1.641 ns) + CELL(0.423 ns) = 9.104 ns; Loc. = LC_X32_Y16_N1; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~29'
- Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 9.182 ns; Loc. = LC_X32_Y16_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~19'
- Info: 7: + IC(0.000 ns) + CELL(0.078 ns) = 9.260 ns; Loc. = LC_X32_Y16_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~34'
- Info: 8: + IC(0.000 ns) + CELL(0.178 ns) = 9.438 ns; Loc. = LC_X32_Y16_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~54'
- Info: 9: + IC(0.000 ns) + CELL(0.208 ns) = 9.646 ns; Loc. = LC_X32_Y16_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~89'
- Info: 10: + IC(0.000 ns) + CELL(0.679 ns) = 10.325 ns; Loc. = LC_X32_Y15_N0; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~102'
- Info: 11: + IC(1.125 ns) + CELL(0.564 ns) = 12.014 ns; Loc. = LC_X31_Y15_N0; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[16]~102'
- Info: 12: + IC(0.000 ns) + CELL(0.078 ns) = 12.092 ns; Loc. = LC_X31_Y15_N1; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[17]~107'
- Info: 13: + IC(0.000 ns) + CELL(0.078 ns) = 12.170 ns; Loc. = LC_X31_Y15_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[18]~112'
- Info: 14: + IC(0.000 ns) + CELL(0.078 ns) = 12.248 ns; Loc. = LC_X31_Y15_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[19]~92'
- Info: 15: + IC(0.000 ns) + CELL(0.178 ns) = 12.426 ns; Loc. = LC_X31_Y15_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[20]~117'
- Info: 16: + IC(0.000 ns) + CELL(0.208 ns) = 12.634 ns; Loc. = LC_X31_Y15_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[25]~142'
- Info: 17: + IC(0.000 ns) + CELL(0.679 ns) = 13.313 ns; Loc. = LC_X31_Y14_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[28]~65'
- Info: 18: + IC(1.677 ns) + CELL(0.442 ns) = 15.432 ns; Loc. = LC_X36_Y12_N1; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~0'
- Info: 19: + IC(1.252 ns) + CELL(0.114 ns) = 16.798 ns; Loc. = LC_X36_Y16_N7; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~1'
- Info: 20: + IC(1.221 ns) + CELL(0.114 ns) = 18.133 ns; Loc. = LC_X36_Y15_N5; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
- Info: 21: + IC(0.418 ns) + CELL(0.114 ns) = 18.665 ns; Loc. = LC_X36_Y15_N0; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
- Info: 22: + IC(0.182 ns) + CELL(0.114 ns) = 18.961 ns; Loc. = LC_X36_Y15_N1; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
- Info: 23: + IC(0.182 ns) + CELL(0.114 ns) = 19.257 ns; Loc. = LC_X36_Y15_N2; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
- Info: 24: + IC(0.760 ns) + CELL(0.867 ns) = 20.884 ns; Loc. = LC_X37_Y15_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
- Info: Total cell delay = 9.931 ns ( 47.55 % )
- Info: Total interconnect delay = 10.953 ns ( 52.45 % )
- Info: - Smallest clock skew is -0.007 ns
- Info: + Shortest clock path from clock "sys_clk" to destination register is 3.178 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X37_Y15_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
- Info: Total cell delay = 2.180 ns ( 68.60 % )
- Info: Total interconnect delay = 0.998 ns ( 31.40 % )
- Info: - Longest clock path from clock "sys_clk" to source memory is 3.185 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(0.998 ns) + CELL(0.718 ns) = 3.185 ns; Loc. = M4K_X33_Y14; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
- Info: Total cell delay = 2.187 ns ( 68.67 % )
- Info: Total interconnect delay = 0.998 ns ( 31.33 % )
- Info: + Micro clock to output delay of source is 0.650 ns
+Info: Clock "sys_clk" has Internal fmax of 36.95 MHz between source register "writeback_stage:writeback_st|wb_reg.dmem_en" and destination register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero" (period= 27.067 ns)
+ Info: + Longest register to register delay is 26.747 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y17_N9; Fanout = 91; REG Node = 'writeback_stage:writeback_st|wb_reg.dmem_en'
+ Info: 2: + IC(1.734 ns) + CELL(0.590 ns) = 2.324 ns; Loc. = LC_X24_Y13_N7; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|regfile_val[0]~3'
+ Info: 3: + IC(3.282 ns) + CELL(0.590 ns) = 6.196 ns; Loc. = LC_X24_Y9_N9; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[0]~48'
+ Info: 4: + IC(2.117 ns) + CELL(0.442 ns) = 8.755 ns; Loc. = LC_X29_Y17_N8; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|regfile_val[0]~49'
+ Info: 5: + IC(1.568 ns) + CELL(0.114 ns) = 10.437 ns; Loc. = LC_X31_Y15_N1; Fanout = 1; COMB Node = 'execute_stage:exec_st|right_operand[0]~18'
+ Info: 6: + IC(0.182 ns) + CELL(0.114 ns) = 10.733 ns; Loc. = LC_X31_Y15_N2; Fanout = 105; COMB Node = 'execute_stage:exec_st|right_operand[0]~19'
+ Info: 7: + IC(1.760 ns) + CELL(0.114 ns) = 12.607 ns; Loc. = LC_X28_Y14_N8; Fanout = 13; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|ShiftLeft0~14'
+ Info: 8: + IC(2.460 ns) + CELL(0.114 ns) = 15.181 ns; Loc. = LC_X29_Y14_N0; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|ShiftRight0~15'
+ Info: 9: + IC(0.400 ns) + CELL(0.442 ns) = 16.023 ns; Loc. = LC_X29_Y14_N6; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|ShiftLeft0~31'
+ Info: 10: + IC(3.419 ns) + CELL(0.114 ns) = 19.556 ns; Loc. = LC_X27_Y11_N7; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|ShiftLeft0~60'
+ Info: 11: + IC(0.459 ns) + CELL(0.292 ns) = 20.307 ns; Loc. = LC_X27_Y11_N0; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector11~0'
+ Info: 12: + IC(0.423 ns) + CELL(0.114 ns) = 20.844 ns; Loc. = LC_X27_Y11_N6; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector11~1'
+ Info: 13: + IC(1.211 ns) + CELL(0.292 ns) = 22.347 ns; Loc. = LC_X23_Y11_N1; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector11~2'
+ Info: 14: + IC(0.182 ns) + CELL(0.114 ns) = 22.643 ns; Loc. = LC_X23_Y11_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector11~5'
+ Info: 15: + IC(0.456 ns) + CELL(0.292 ns) = 23.391 ns; Loc. = LC_X23_Y11_N4; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~1'
+ Info: 16: + IC(2.074 ns) + CELL(0.114 ns) = 25.579 ns; Loc. = LC_X28_Y18_N2; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~2'
+ Info: 17: + IC(0.430 ns) + CELL(0.738 ns) = 26.747 ns; Loc. = LC_X28_Y18_N6; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
+ Info: Total cell delay = 4.590 ns ( 17.16 % )
+ Info: Total interconnect delay = 22.157 ns ( 82.84 % )
+ Info: - Smallest clock skew is -0.059 ns
+ Info: + Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X28_Y18_N6; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
+ Info: Total cell delay = 2.180 ns ( 68.40 % )
+ Info: Total interconnect delay = 1.007 ns ( 31.60 % )
+ Info: - Longest clock path from clock "sys_clk" to source register is 3.246 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X25_Y17_N9; Fanout = 91; REG Node = 'writeback_stage:writeback_st|wb_reg.dmem_en'
+ Info: Total cell delay = 2.180 ns ( 67.16 % )
+ Info: Total interconnect delay = 1.066 ns ( 32.84 % )
+ Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
-Info: tsu for register "fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]" (data pin = "sys_res", clock pin = "sys_clk") is 18.965 ns
- Info: + Longest pin to register delay is 22.115 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
- Info: 2: + IC(9.029 ns) + CELL(0.114 ns) = 10.612 ns; Loc. = LC_X38_Y14_N6; Fanout = 10; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[6]~3'
- Info: 3: + IC(0.479 ns) + CELL(0.114 ns) = 11.205 ns; Loc. = LC_X38_Y14_N3; Fanout = 8; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[0]~20'
- Info: 4: + IC(3.612 ns) + CELL(0.442 ns) = 15.259 ns; Loc. = LC_X29_Y17_N2; Fanout = 2; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[2]~11'
- Info: 5: + IC(1.961 ns) + CELL(0.442 ns) = 17.662 ns; Loc. = LC_X35_Y16_N6; Fanout = 1; COMB Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|Equal0~1'
- Info: 6: + IC(1.703 ns) + CELL(0.292 ns) = 19.657 ns; Loc. = LC_X38_Y14_N4; Fanout = 6; COMB Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|Equal0~2'
- Info: 7: + IC(2.149 ns) + CELL(0.309 ns) = 22.115 ns; Loc. = LC_X35_Y19_N2; Fanout = 25; REG Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]'
- Info: Total cell delay = 3.182 ns ( 14.39 % )
- Info: Total interconnect delay = 18.933 ns ( 85.61 % )
+Info: tsu for register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero" (data pin = "sys_res", clock pin = "sys_clk") is 18.145 ns
+ Info: + Longest pin to register delay is 21.295 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 504; PIN Node = 'sys_res'
+ Info: 2: + IC(9.198 ns) + CELL(0.442 ns) = 11.109 ns; Loc. = LC_X28_Y20_N7; Fanout = 7; COMB Node = 'execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1'
+ Info: 3: + IC(5.851 ns) + CELL(0.590 ns) = 17.550 ns; Loc. = LC_X25_Y16_N7; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|calc~0'
+ Info: 4: + IC(2.878 ns) + CELL(0.867 ns) = 21.295 ns; Loc. = LC_X28_Y18_N6; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
+ Info: Total cell delay = 3.368 ns ( 15.82 % )
+ Info: Total interconnect delay = 17.927 ns ( 84.18 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X35_Y19_N2; Fanout = 25; REG Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]'
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X28_Y18_N6; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
Info: Total cell delay = 2.180 ns ( 68.40 % )
Info: Total interconnect delay = 1.007 ns ( 31.60 % )
-Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 10.165 ns
+Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 10.677 ns
Info: + Longest clock path from clock "sys_clk" to source register is 3.111 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X32_Y9_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
+ Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X27_Y8_N4; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
Info: Total cell delay = 2.180 ns ( 70.07 % )
Info: Total interconnect delay = 0.931 ns ( 29.93 % )
Info: + Micro clock to output delay of source is 0.224 ns
- Info: + Longest register to pin delay is 6.830 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y9_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
- Info: 2: + IC(4.706 ns) + CELL(2.124 ns) = 6.830 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
- Info: Total cell delay = 2.124 ns ( 31.10 % )
- Info: Total interconnect delay = 4.706 ns ( 68.90 % )
-Info: th for register "fetch_stage:fetch_st|instr_r_addr[4]" (data pin = "sys_res", clock pin = "sys_clk") is -8.849 ns
- Info: + Longest clock path from clock "sys_clk" to destination register is 3.178 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X39_Y14_N4; Fanout = 3; REG Node = 'fetch_stage:fetch_st|instr_r_addr[4]'
- Info: Total cell delay = 2.180 ns ( 68.60 % )
- Info: Total interconnect delay = 0.998 ns ( 31.40 % )
+ Info: + Longest register to pin delay is 7.342 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y8_N4; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
+ Info: 2: + IC(5.218 ns) + CELL(2.124 ns) = 7.342 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
+ Info: Total cell delay = 2.124 ns ( 28.93 % )
+ Info: Total interconnect delay = 5.218 ns ( 71.07 % )
+Info: th for register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1]" (data pin = "bus_rx", clock pin = "sys_clk") is -5.628 ns
+ Info: + Longest clock path from clock "sys_clk" to destination register is 3.246 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 1098; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X22_Y18_N3; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1]'
+ Info: Total cell delay = 2.180 ns ( 67.16 % )
+ Info: Total interconnect delay = 1.066 ns ( 32.84 % )
Info: + Micro hold delay of destination is 0.015 ns
- Info: - Shortest pin to register delay is 12.042 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
- Info: 2: + IC(9.029 ns) + CELL(0.114 ns) = 10.612 ns; Loc. = LC_X38_Y14_N6; Fanout = 10; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[6]~3'
- Info: 3: + IC(0.482 ns) + CELL(0.114 ns) = 11.208 ns; Loc. = LC_X38_Y14_N0; Fanout = 2; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[4]~14'
- Info: 4: + IC(0.719 ns) + CELL(0.115 ns) = 12.042 ns; Loc. = LC_X39_Y14_N4; Fanout = 3; REG Node = 'fetch_stage:fetch_st|instr_r_addr[4]'
- Info: Total cell delay = 1.812 ns ( 15.05 % )
- Info: Total interconnect delay = 10.230 ns ( 84.95 % )
+ Info: - Shortest pin to register delay is 8.889 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 1; PIN Node = 'bus_rx'
+ Info: 2: + IC(7.111 ns) + CELL(0.309 ns) = 8.889 ns; Loc. = LC_X22_Y18_N3; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1]'
+ Info: Total cell delay = 1.778 ns ( 20.00 % )
+ Info: Total interconnect delay = 7.111 ns ( 80.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 189 megabytes
- Info: Processing ended: Fri Dec 17 12:27:19 2010
+ Info: Peak virtual memory: 192 megabytes
+ Info: Processing ended: Sun Dec 19 20:36:51 2010
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Type : Worst-case tsu
Slack : N/A
Required Time : None
-Actual Time : 18.965 ns
+Actual Time : 18.145 ns
From : sys_res
-To : fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27]
+To : execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero
From Clock : --
To Clock : sys_clk
Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
-Actual Time : 10.165 ns
+Actual Time : 10.677 ns
From : writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int
To : bus_tx
From Clock : sys_clk
Type : Worst-case th
Slack : N/A
Required Time : None
-Actual Time : -8.849 ns
-From : sys_res
-To : fetch_stage:fetch_st|instr_r_addr[4]
+Actual Time : -5.628 ns
+From : bus_rx
+To : writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1]
From Clock : --
To Clock : sys_clk
Failed Paths : 0
Type : Clock Setup: 'sys_clk'
Slack : N/A
Required Time : None
-Actual Time : 46.34 MHz ( period = 21.578 ns )
-From : decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2
-To : writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4]
+Actual Time : 36.95 MHz ( period = 27.067 ns )
+From : writeback_stage:writeback_st|wb_reg.dmem_en
+To : execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero
From Clock : sys_clk
To Clock : sys_clk
Failed Paths : 0
projects / calu.git / commitdiff