wb extension

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 5eb1f949faa7c2a78d752cc825a3eb3afbe84a22..7cf1548ff4c59000d9b0a12c864fabbbad7570ec 100644 (file)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -12,6 +12,7 @@ use work.extension_uart_pkg.all;
 architecture behav of writeback_stage is
 
 signal data_ram_read, data_ram_read_ext : word_t;
+signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
@@ -32,8 +33,8 @@ begin
                
                port map (
                        clk,
-                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
-                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
                        wb_reg_nxt.dmem_write_en,
                        ram_data,
                        data_ram_read
@@ -141,11 +142,17 @@ end process;
 
 
 
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt)
 
 begin  
        reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
        reg_addr <= result_addr;
+
+       data_addr <= (others => '0');
+       
+       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) = '1') then
+               data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
+       end if;
 end process;