vcom -work work ../src/common_pkg.vhd
vcom -work work ../src/extension_pkg.vhd
vcom -work work ../src/extension_uart_pkg.vhd
+vcom -work work ../src/extension_uart.vhd
+vcom -work work ../src/extension_uart_b.vhd
+vcom -work work ../src/rs232_tx.vhd
+vcom -work work ../src/rs232_tx_arc.vhd
+vcom -work work ../src/rs232_rx.vhd
+vcom -work work ../src/rs232_rx_arc.vhd
+
vcom -work work ../src/core_pkg.vhd
vcom -work work ../src/decoder.vhd
vcom -work work ../src/decoder_b.vhd
add wave -radix hexadecimal /pipeline_tb/data_pin
add wave -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
add wave -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
+add wave -radix hexadecimal /pipeline_tb/writeback_st/dmem_we
+add wave -radix hexadecimal /pipeline_tb/writeback_st/data_addr
add wave -radix decimal /pipeline_tb/cycle_cnt
run 10000 ns
add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
-
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ram_data
add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_uart
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg_nxt
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/wb_reg
add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg
add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt
add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config
constant EXT_TIMER_ADDR: ext_addrid_t := x"FFFFFFC";
constant EXT_AC97_ADDR: ext_addrid_t := x"FFFFFFD";
-- constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE";
-constant EXT_UART_ADDR: ext_addrid_t := x"0000100";
+constant EXT_UART_ADDR: ext_addrid_t := x"0000200";
constant EXT_GPMP_ADDR: ext_addrid_t := x"FFFFFFF";
component extension_gpm is
architecture behav of extension_uart is
signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
-signal new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
+signal new_bus_rx,new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
signal bd_rate : baud_rate_l;
-
+signal rx_data : std_logic_vector(7 downto 0);
begin
bus_rx,
--From/to sendlogic
- w1_st_co(17),
- w4_uart_receive(byte_t'range)
-
+ new_bus_rx,
+ rx_data
);
w2_uart_config <= (others=>'0');
w3_uart_send <= (others=>'0');
w4_uart_receive <= (others=>'0');
-
+ tx_rdy_int <= '0';
+ new_tx_data <= '0';
elsif rising_edge(clk) then
w1_st_co <= w1_st_co_nxt;
-- r0 = 0, r1 = 1, r2 = 3, r3 = A
signal ram : RAM_TYPE := (
--- 0 => x"ed2802d0", -- ldi r5, 0x5a;;
--- 1 => x"ed008058", -- ldi r0, 0x100b;;
--- 2 => x"e7a80000", -- stw r5, 0(r0);;
--- 3 => "11101011000000000000000000000010",
+ -- 0 => x"ed2802d0", -- ldi r5, 0x5a;;
+ -- 1 => x"ed010058", -- ldi r0, 0x200b;;
+ -- 2 => x"e7a80000", -- stw r5, 0(r0);;
+ -- 3 => x"e7828000", -- stw r0, 0(r5);;
+ -- 4 => "11101011000000000000000000000010",
--8 => "11100111100010000000000000000000", --stw
-- 0 => "11101101000000000000000000000000", --ldi
process(clk)
begin
if rising_edge(clk) then
- --data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ -- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
case rd_addr is
when "00000000000" => data_out <= x"ed2802d0"; -- ldi r5, 0x5a;;
- when "00000000001" => data_out <= x"ed008058"; -- ldi r0, 0x100b;;
+ when "00000000001" => data_out <= x"ed010058"; -- ldi r0, 0x200b;;
when "00000000010" => data_out <= x"e7a80000"; -- stw r5, 0(r0);;
when others => data_out <= "11101011000000000000000000000010";
end case;
signal ext_uart,ext_timer,ext_gpmp : extmod_rec;
-signal sel_nxt :std_logic;
+signal sel_nxt, dmem_we, bus_rx :std_logic;
clk,
data_addr(DATA_ADDR_WIDTH+1 downto 2),
data_addr(DATA_ADDR_WIDTH+1 downto 2),
- wb_reg_nxt.dmem_write_en,
+ dmem_we,
ram_data,
data_ram_read
);
reset,
ext_uart,
data_ram_read_ext,
+ bus_rx,
bus_tx
);
wb_reg.dmem_write_en <= '0';
wb_reg.hword <= '0';
wb_reg.byte_s <= '0';
+ bus_rx <= '1';
elsif rising_edge(clk) then
wb_reg <= wb_reg_nxt;
+ bus_rx <= '1';
end if;
end process;
reg_addr <= result_addr;
data_addr <= (others => '0');
+ dmem_we <= '0';
- if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) = '1') then
+ if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
+ dmem_we <= wb_reg_nxt.dmem_write_en;
end if;
end process;
addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en)
begin
- ext_uart.sel <='0';
+ ext_uart.sel <='0';
ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
ext_uart.byte_en <= (others => '0');
ext_uart.data <= (others => '0');
ext_gpmp.byte_en <= (others => '0');
ext_gpmp.data <= (others => '0');
ext_gpmp.addr <= (others => '0');
- -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
- case wb_reg_nxt.address(wb_reg_nxt.address'high downto 4) is
+ -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
+ case wb_reg_nxt.address(31 downto 4) is
when EXT_UART_ADDR =>
ext_uart.sel <='1';
ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
ext_uart.data <= ram_data;
- ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
+ ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
case wb_reg.address(1 downto 0) is
when "00" => ext_uart.byte_en <= "0001";
when "01" => ext_uart.byte_en <= "0010";
when "11" => ext_uart.byte_en <= "1111";
when others => null;
end case;
+
+
when EXT_TIMER_ADDR =>
ext_timer.sel <='1';
ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
Assembler report for dt
-Fri Dec 17 10:10:39 2010
+Fri Dec 17 12:27:16 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Fri Dec 17 10:10:39 2010 ;
+; Assembler Status ; Successful - Fri Dec 17 12:27:16 2010 ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
+----------------+-----------------+
; Device ; EP1C12Q240C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x001F1EC3 ;
+; Checksum ; 0x001EAC07 ;
+----------------+-----------------+
+--------------------+-------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x03ACAE9A ;
+; Checksum ; 0x03AFD4AC ;
; Compression Ratio ; 1 ;
+--------------------+-------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 10:10:37 2010
+ Info: Processing started: Fri Dec 17 12:27:13 2010
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dt -c dt
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 230 megabytes
- Info: Processing ended: Fri Dec 17 10:10:39 2010
- Info: Elapsed time: 00:00:02
+ Info: Processing ended: Fri Dec 17 12:27:16 2010
+ Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02
-Fri Dec 17 10:10:43 2010
+Fri Dec 17 12:27:19 2010
Fitter report for dt
-Fri Dec 17 10:10:33 2010
+Fri Dec 17 12:27:10 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
-; Fitter Status ; Successful - Fri Dec 17 10:10:33 2010 ;
+; Fitter Status ; Successful - Fri Dec 17 12:27:10 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
-; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
+; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
; Total pins ; 3 / 173 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
; Type ; Value ;
+---------------------+------------------------+
; Placement (by node) ; ;
-; -- Requested ; 0 / 1125 ( 0.00 % ) ;
-; -- Achieved ; 0 / 1125 ( 0.00 % ) ;
+; -- Requested ; 0 / 1127 ( 0.00 % ) ;
+; -- Achieved ; 0 / 1127 ( 0.00 % ) ;
; ; ;
; Routing (by net) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
-; Top ; 1123 ; 0 ; N/A ; Source File ;
+; Top ; 1125 ; 0 ; N/A ; Source File ;
; hard_block:auto_generated_inst ; 2 ; 0 ; N/A ; Source File ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
+---------------------------------------------+-------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------------------------------------+
-; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
-; -- Combinational with no register ; 841 ;
+; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
+; -- Combinational with no register ; 843 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 215 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 467 ;
-; -- 3 input functions ; 447 ;
+; -- 4 input functions ; 473 ;
+; -- 3 input functions ; 443 ;
; -- 2 input functions ; 123 ;
; -- 1 input functions ; 18 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 850 ;
+; -- normal mode ; 852 ;
; -- arithmetic mode ; 206 ;
-; -- qfbk mode ; 77 ;
+; -- qfbk mode ; 76 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 84 ;
-; -- asynchronous clear/load mode ; 202 ;
+; -- synchronous clear/load mode ; 83 ;
+; -- asynchronous clear/load mode ; 203 ;
; ; ;
; Total registers ; 215 / 12,567 ( 2 % ) ;
-; Total LABs ; 114 / 1,206 ( 9 % ) ;
+; Total LABs ; 111 / 1,206 ( 9 % ) ;
; Logic elements in carry chains ; 214 ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; ASMI Blocks ; 0 / 1 ( 0 % ) ;
; CRC blocks ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 5% / 5% / 5% ;
-; Peak interconnect usage (total/H/V) ; 31% / 32% / 30% ;
+; Average interconnect usage (total/H/V) ; 5% / 5% / 4% ;
+; Peak interconnect usage (total/H/V) ; 17% / 19% / 14% ;
; Maximum fan-out node ; sys_clk ;
; Maximum fan-out ; 217 ;
; Highest non-global fan-out signal ; execute_stage:exec_st|alu:alu_inst|Selector76~0 ;
-; Highest non-global fan-out ; 115 ;
-; Total fan-out ; 4170 ;
-; Average fan-out ; 3.92 ;
+; Highest non-global fan-out ; 114 ;
+; Total fan-out ; 4182 ;
+; Average fan-out ; 3.93 ;
+---------------------------------------------+-------------------------------------------------+
+---------------------------------------------+--------------------+--------------------------------+
; Difficulty Clustering Region ; Low ; Low ;
; ; ; ;
-; Total logic elements ; 1056 ; 0 ;
-; -- Combinational with no register ; 841 ; 0 ;
+; Total logic elements ; 1058 ; 0 ;
+; -- Combinational with no register ; 843 ; 0 ;
; -- Register only ; 0 ; 0 ;
; -- Combinational with a register ; 215 ; 0 ;
; ; ; ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
-; -- Total Connections ; 4343 ; 0 ;
-; -- Registered Connections ; 813 ; 0 ;
+; -- Total Connections ; 4355 ; 0 ;
+; -- Registered Connections ; 809 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 0 ; 0 ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1056 (1) ; 215 ; 512 ; 2 ; 3 ; 0 ; 841 (1) ; 0 (0) ; 215 (0) ; 214 (0) ; 77 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 103 (96) ; 72 ; 512 ; 2 ; 0 ; 0 ; 31 (24) ; 0 (0) ; 72 (72) ; 11 (11) ; 5 (5) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |core_top ; 1058 (1) ; 215 ; 512 ; 2 ; 3 ; 0 ; 843 (1) ; 0 (0) ; 215 (0) ; 214 (0) ; 76 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 100 (94) ; 72 ; 512 ; 2 ; 0 ; 0 ; 28 (22) ; 0 (0) ; 72 (72) ; 11 (11) ; 5 (5) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 755 (145) ; 67 ; 0 ; 0 ; 0 ; 0 ; 688 (109) ; 0 (0) ; 67 (36) ; 171 (0) ; 71 (40) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 545 (224) ; 0 ; 0 ; 0 ; 0 ; 0 ; 545 (224) ; 0 (0) ; 0 (0) ; 141 (43) ; 31 (31) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |execute_stage:exec_st| ; 761 (146) ; 67 ; 0 ; 0 ; 0 ; 0 ; 694 (110) ; 0 (0) ; 67 (36) ; 171 (0) ; 70 (39) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 550 (228) ; 0 ; 0 ; 0 ; 0 ; 0 ; 550 (228) ; 0 (0) ; 0 (0) ; 141 (43) ; 31 (31) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:or_inst| ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
+; |exec_op:or_inst| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 31 (31) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
; |fetch_stage:fetch_st| ; 33 (24) ; 17 ; 0 ; 0 ; 0 ; 0 ; 16 (13) ; 0 (0) ; 17 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 164 (52) ; 59 ; 0 ; 0 ; 0 ; 0 ; 105 (48) ; 0 (0) ; 59 (4) ; 32 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st ; ;
+; |writeback_stage:writeback_st| ; 163 (48) ; 59 ; 0 ; 0 ; 0 ; 0 ; 104 (44) ; 0 (0) ; 59 (4) ; 32 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st ; ;
; |extension_uart:uart| ; 106 (12) ; 49 ; 0 ; 0 ; 0 ; 0 ; 57 (2) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+; |r_w_ram:data_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0 ; 1 ; ON ;
; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.displacement[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr_nxt[3]~3 ; 1 ; ON ;
+; - fetch_stage:fetch_st|instr_r_addr_nxt[6]~3 ; 1 ; ON ;
; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
+---------------------------------------------------------------------------------------------+-------------------+---------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X27_Y17_N9 ; 58 ; Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X36_Y17_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X29_Y15_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
-; execute_stage:exec_st|reg.result[1]~9 ; LC_X27_Y16_N4 ; 12 ; Sync. load ; no ; -- ; -- ;
-; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load, Clock enable ; yes ; Global Clock ; GCLK3 ;
-; writeback_stage:writeback_st|Mux9~0 ; LC_X26_Y19_N7 ; 7 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X40_Y20_N6 ; 5 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X40_Y19_N5 ; 35 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X27_Y19_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|reg_we~0 ; LC_X31_Y18_N0 ; 8 ; Write enable ; no ; -- ; -- ;
-+--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X39_Y14_N6 ; 57 ; Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X38_Y18_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X36_Y12_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
+; execute_stage:exec_st|reg.result[1]~9 ; LC_X32_Y12_N1 ; 12 ; Sync. load ; no ; -- ; -- ;
+; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK3 ;
+; writeback_stage:writeback_st|Mux9~0 ; LC_X37_Y15_N8 ; 7 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X32_Y9_N2 ; 5 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X31_Y8_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X36_Y15_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|reg_we~0 ; LC_X35_Y14_N9 ; 8 ; Write enable ; no ; -- ; -- ;
++--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+-----------------------------------------------------------------------------------+---------+
-; execute_stage:exec_st|alu:alu_inst|Selector76~0 ; 115 ;
-; execute_stage:exec_st|right_operand[0]~10 ; 89 ;
+; execute_stage:exec_st|alu:alu_inst|Selector76~0 ; 114 ;
+; execute_stage:exec_st|right_operand[0]~10 ; 90 ;
; execute_stage:exec_st|right_operand[1]~6 ; 77 ;
-; execute_stage:exec_st|right_operand[2]~4 ; 63 ;
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 58 ;
-; execute_stage:exec_st|alu:alu_inst|Selector53~0 ; 53 ;
+; execute_stage:exec_st|right_operand[2]~4 ; 64 ;
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 57 ;
+; execute_stage:exec_st|alu:alu_inst|Selector48~0 ; 55 ;
; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 49 ;
; execute_stage:exec_st|right_operand[3]~8 ; 48 ;
; decode_stage:decode_st|dec_op_inst.op_detail[2] ; 41 ;
-; execute_stage:exec_st|left_operand[13]~1 ; 40 ;
-; execute_stage:exec_st|right_operand[14]~1 ; 38 ;
+; execute_stage:exec_st|left_operand[19]~1 ; 41 ;
+; execute_stage:exec_st|right_operand[30]~2 ; 39 ;
+; execute_stage:exec_st|right_operand[30]~1 ; 39 ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; 37 ;
-; execute_stage:exec_st|right_operand[14]~2 ; 37 ;
; writeback_stage:writeback_st|wb_reg.dmem_en ; 35 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 35 ;
; writeback_stage:writeback_st|wb_reg.dmem_write_en ; 34 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|Equal0~10 ; 34 ;
; execute_stage:exec_st|alu:alu_inst|calc~0 ; 32 ;
; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
+; execute_stage:exec_st|reg.result[7]~12 ; 30 ;
; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
-; execute_stage:exec_st|reg.result[11]~12 ; 29 ;
; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
; writeback_stage:writeback_st|jump ; 25 ;
; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 25 ;
+; execute_stage:exec_st|reg.result[7]~13 ; 24 ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; 24 ;
-; execute_stage:exec_st|reg.result[11]~13 ; 23 ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 23 ;
-; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 21 ;
+; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 20 ;
; decode_stage:decode_st|decoder:decoder_inst|instr_s~5 ; 15 ;
-; decode_stage:decode_st|rtw_rec.imm_set ; 15 ;
-; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 13 ;
; execute_stage:exec_st|reg.result[1]~9 ; 12 ;
+; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 12 ;
+; decode_stage:decode_st|rtw_rec.imm_set ; 12 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 12 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 10 ;
; execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|tmp_sb~0 ; 9 ;
-; execute_stage:exec_st|left_operand[30]~56 ; 9 ;
-; execute_stage:exec_st|left_operand[29]~54 ; 9 ;
-; execute_stage:exec_st|left_operand[28]~52 ; 9 ;
+; execute_stage:exec_st|alu:alu_inst|Selector76~1 ; 9 ;
+; execute_stage:exec_st|left_operand[30]~46 ; 9 ;
+; execute_stage:exec_st|left_operand[29]~44 ; 9 ;
+; execute_stage:exec_st|left_operand[28]~42 ; 9 ;
+; execute_stage:exec_st|alu:alu_inst|Selector107~0 ; 9 ;
; execute_stage:exec_st|reg.res_addr[2] ; 9 ;
-; execute_stage:exec_st|reg.result[6]~21 ; 8 ;
+; execute_stage:exec_st|reg.result[4]~21 ; 8 ;
; execute_stage:exec_st|reg.result[25]~14 ; 8 ;
-; execute_stage:exec_st|alu:alu_inst|Selector76~1 ; 8 ;
-; execute_stage:exec_st|left_operand[27]~50 ; 8 ;
-; execute_stage:exec_st|left_operand[26]~48 ; 8 ;
+; execute_stage:exec_st|left_operand[27]~40 ; 8 ;
+; execute_stage:exec_st|left_operand[26]~38 ; 8 ;
; execute_stage:exec_st|alu:alu_inst|Selector97~0 ; 8 ;
; execute_stage:exec_st|left_operand[12]~34 ; 8 ;
; execute_stage:exec_st|left_operand[11]~32 ; 8 ;
; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 8 ;
-; execute_stage:exec_st|alu:alu_inst|Selector107~0 ; 8 ;
-; execute_stage:exec_st|right_operand[14]~13 ; 8 ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; 8 ;
+-----------------------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y18 ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y19 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y15 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y14 ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+----------------------------+------------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------------+
-; C4s ; 1,397 / 30,600 ( 5 % ) ;
-; Direct links ; 137 / 43,552 ( < 1 % ) ;
+; C4s ; 1,302 / 30,600 ( 4 % ) ;
+; Direct links ; 132 / 43,552 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
-; LAB clocks ; 32 / 312 ( 10 % ) ;
-; LUT chains ; 146 / 10,854 ( 1 % ) ;
-; Local interconnects ; 1,899 / 43,552 ( 4 % ) ;
+; LAB clocks ; 29 / 312 ( 9 % ) ;
+; LUT chains ; 139 / 10,854 ( 1 % ) ;
+; Local interconnects ; 1,864 / 43,552 ( 4 % ) ;
; M4K buffers ; 64 / 1,872 ( 3 % ) ;
-; R4s ; 1,532 / 28,560 ( 5 % ) ;
+; R4s ; 1,504 / 28,560 ( 5 % ) ;
+----------------------------+------------------------+
+----------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-------------------------------+
-; Number of Logic Elements (Average = 9.26) ; Number of LABs (Total = 114) ;
+; Number of Logic Elements (Average = 9.53) ; Number of LABs (Total = 111) ;
+--------------------------------------------+-------------------------------+
-; 1 ; 6 ;
-; 2 ; 1 ;
-; 3 ; 1 ;
+; 1 ; 3 ;
+; 2 ; 2 ;
+; 3 ; 0 ;
; 4 ; 0 ;
-; 5 ; 2 ;
+; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
-; 8 ; 0 ;
-; 9 ; 2 ;
-; 10 ; 101 ;
+; 8 ; 1 ;
+; 9 ; 4 ;
+; 10 ; 100 ;
+--------------------------------------------+-------------------------------+
+--------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-------------------------------+
-; LAB-wide Signals (Average = 1.44) ; Number of LABs (Total = 114) ;
+; LAB-wide Signals (Average = 1.49) ; Number of LABs (Total = 111) ;
+------------------------------------+-------------------------------+
-; 1 Async. clear ; 69 ;
+; 1 Async. clear ; 70 ;
; 1 Async. load ; 2 ;
; 1 Clock ; 72 ;
-; 1 Clock enable ; 13 ;
-; 1 Sync. clear ; 3 ;
+; 1 Clock enable ; 14 ;
+; 1 Sync. clear ; 2 ;
; 1 Sync. load ; 5 ;
+------------------------------------+-------------------------------+
-+-----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-------------------------------+
-; Number of Signals Sourced (Average = 9.97) ; Number of LABs (Total = 114) ;
-+---------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 6 ;
-; 2 ; 1 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 2 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 2 ;
-; 10 ; 60 ;
-; 11 ; 21 ;
-; 12 ; 7 ;
-; 13 ; 7 ;
-; 14 ; 6 ;
-+---------------------------------------------+-------------------------------+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced (Average = 10.26) ; Number of LABs (Total = 111) ;
++----------------------------------------------+-------------------------------+
+; 0 ; 0 ;
+; 1 ; 3 ;
+; 2 ; 2 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 5 ;
+; 10 ; 60 ;
+; 11 ; 19 ;
+; 12 ; 13 ;
+; 13 ; 4 ;
+; 14 ; 5 ;
++----------------------------------------------+-------------------------------+
+---------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-------------------------------+
-; Number of Signals Sourced Out (Average = 6.84) ; Number of LABs (Total = 114) ;
+; Number of Signals Sourced Out (Average = 6.93) ; Number of LABs (Total = 111) ;
+-------------------------------------------------+-------------------------------+
; 0 ; 0 ;
-; 1 ; 6 ;
-; 2 ; 1 ;
-; 3 ; 7 ;
-; 4 ; 7 ;
-; 5 ; 14 ;
-; 6 ; 15 ;
-; 7 ; 14 ;
-; 8 ; 17 ;
-; 9 ; 10 ;
-; 10 ; 18 ;
+; 1 ; 4 ;
+; 2 ; 2 ;
+; 3 ; 8 ;
+; 4 ; 5 ;
+; 5 ; 11 ;
+; 6 ; 19 ;
+; 7 ; 13 ;
+; 8 ; 15 ;
+; 9 ; 11 ;
+; 10 ; 19 ;
; 11 ; 2 ;
-; 12 ; 2 ;
-; 13 ; 1 ;
+; 12 ; 1 ;
+; 13 ; 0 ;
+; 14 ; 1 ;
+-------------------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+-------------------------------+
-; Number of Distinct Inputs (Average = 16.04) ; Number of LABs (Total = 114) ;
+; Number of Distinct Inputs (Average = 16.28) ; Number of LABs (Total = 111) ;
+----------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
-; 3 ; 3 ;
-; 4 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
; 5 ; 2 ;
-; 6 ; 1 ;
+; 6 ; 2 ;
; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 0 ;
-; 10 ; 5 ;
+; 8 ; 0 ;
+; 9 ; 2 ;
+; 10 ; 4 ;
; 11 ; 8 ;
-; 12 ; 7 ;
-; 13 ; 3 ;
-; 14 ; 9 ;
-; 15 ; 5 ;
+; 12 ; 10 ;
+; 13 ; 4 ;
+; 14 ; 4 ;
+; 15 ; 6 ;
; 16 ; 5 ;
-; 17 ; 6 ;
-; 18 ; 7 ;
-; 19 ; 4 ;
-; 20 ; 18 ;
-; 21 ; 16 ;
+; 17 ; 4 ;
+; 18 ; 10 ;
+; 19 ; 5 ;
+; 20 ; 19 ;
+; 21 ; 13 ;
; 22 ; 11 ;
+----------------------------------------------+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 10:10:15 2010
+ Info: Processing started: Fri Dec 17 12:26:52 2010
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
Info: Selected device EP1C12Q240C8 for design "dt"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Automatically promoted signal "sys_clk" to use Global clock in PIN 152
Info: Automatically promoted some destinations of signal "sys_res" to use Global clock
Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|new_tx_data" may be non-global or may not use global clock
- Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[3]~3" may be non-global or may not use global clock
+ Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[6]~3" may be non-global or may not use global clock
Info: Pin "sys_res" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
-Info: Estimated most critical path is memory to register delay of 20.863 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3~portb_address_reg2'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3'
- Info: 3: + IC(1.586 ns) + CELL(0.442 ns) = 6.345 ns; Loc. = LAB_X28_Y22; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[3]~19'
- Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 6.998 ns; Loc. = LAB_X28_Y22; Fanout = 4; COMB Node = 'execute_stage:exec_st|left_operand[3]~20'
- Info: 5: + IC(0.117 ns) + CELL(0.590 ns) = 7.705 ns; Loc. = LAB_X28_Y22; Fanout = 8; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector104~0'
- Info: 6: + IC(0.995 ns) + CELL(0.575 ns) = 9.275 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~2COUT1_196'
- Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.355 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~12COUT1_198'
- Info: 8: + IC(0.000 ns) + CELL(0.258 ns) = 9.613 ns; Loc. = LAB_X31_Y22; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~17'
- Info: 9: + IC(0.000 ns) + CELL(0.679 ns) = 10.292 ns; Loc. = LAB_X31_Y21; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~20'
- Info: 10: + IC(0.771 ns) + CELL(0.432 ns) = 11.495 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[6]~22COUT1_195'
- Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 11.575 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[7]~27COUT1_197'
- Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 11.655 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[8]~32COUT1_199'
- Info: 13: + IC(0.000 ns) + CELL(0.608 ns) = 12.263 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[9]~5'
- Info: 14: + IC(1.264 ns) + CELL(0.114 ns) = 13.641 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector65~0'
- Info: 15: + IC(0.361 ns) + CELL(0.292 ns) = 14.294 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector65~1'
- Info: 16: + IC(0.063 ns) + CELL(0.590 ns) = 14.947 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~0'
- Info: 17: + IC(0.303 ns) + CELL(0.590 ns) = 15.840 ns; Loc. = LAB_X30_Y17; Fanout = 7; COMB Node = 'writeback_stage:writeback_st|Equal0~5'
- Info: 18: + IC(1.093 ns) + CELL(0.590 ns) = 17.523 ns; Loc. = LAB_X27_Y19; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
- Info: 19: + IC(0.063 ns) + CELL(0.590 ns) = 18.176 ns; Loc. = LAB_X27_Y19; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~12'
- Info: 20: + IC(0.211 ns) + CELL(0.442 ns) = 18.829 ns; Loc. = LAB_X27_Y19; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
- Info: 21: + IC(1.167 ns) + CELL(0.867 ns) = 20.863 ns; Loc. = LAB_X28_Y21; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
- Info: Total cell delay = 12.806 ns ( 61.38 % )
- Info: Total interconnect delay = 8.057 ns ( 38.62 % )
+Info: Estimated most critical path is memory to register delay of 21.050 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y15; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg2'
+ Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y15; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a6'
+ Info: 3: + IC(1.222 ns) + CELL(0.442 ns) = 5.981 ns; Loc. = LAB_X38_Y16; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[6]~17'
+ Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 6.634 ns; Loc. = LAB_X38_Y16; Fanout = 4; COMB Node = 'execute_stage:exec_st|left_operand[6]~18'
+ Info: 5: + IC(0.117 ns) + CELL(0.590 ns) = 7.341 ns; Loc. = LAB_X38_Y16; Fanout = 9; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector101~0'
+ Info: 6: + IC(1.338 ns) + CELL(0.575 ns) = 9.254 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~37COUT1_200'
+ Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.334 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~27COUT1_202'
+ Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 9.414 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~17COUT1_204'
+ Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 9.494 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~32COUT1_206'
+ Info: 10: + IC(0.000 ns) + CELL(0.258 ns) = 9.752 ns; Loc. = LAB_X30_Y16; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~52'
+ Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 9.888 ns; Loc. = LAB_X30_Y16; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~87'
+ Info: 12: + IC(0.000 ns) + CELL(0.136 ns) = 10.024 ns; Loc. = LAB_X30_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~117'
+ Info: 13: + IC(0.000 ns) + CELL(0.679 ns) = 10.703 ns; Loc. = LAB_X30_Y15; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~120'
+ Info: 14: + IC(0.771 ns) + CELL(0.432 ns) = 11.906 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[21]~122COUT1_219'
+ Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 11.986 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[22]~127COUT1_221'
+ Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 12.066 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[23]~132COUT1_223'
+ Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 12.146 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[24]~137COUT1_225'
+ Info: 18: + IC(0.000 ns) + CELL(0.258 ns) = 12.404 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[25]~142'
+ Info: 19: + IC(0.000 ns) + CELL(0.679 ns) = 13.083 ns; Loc. = LAB_X31_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[28]~65'
+ Info: 20: + IC(1.640 ns) + CELL(0.114 ns) = 14.837 ns; Loc. = LAB_X36_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~0'
+ Info: 21: + IC(1.086 ns) + CELL(0.292 ns) = 16.215 ns; Loc. = LAB_X36_Y16; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~1'
+ Info: 22: + IC(0.752 ns) + CELL(0.590 ns) = 17.557 ns; Loc. = LAB_X36_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
+ Info: 23: + IC(0.539 ns) + CELL(0.114 ns) = 18.210 ns; Loc. = LAB_X36_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
+ Info: 24: + IC(0.063 ns) + CELL(0.590 ns) = 18.863 ns; Loc. = LAB_X36_Y15; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
+ Info: 25: + IC(0.211 ns) + CELL(0.442 ns) = 19.516 ns; Loc. = LAB_X36_Y15; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
+ Info: 26: + IC(0.667 ns) + CELL(0.867 ns) = 21.050 ns; Loc. = LAB_X37_Y15; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
+ Info: Total cell delay = 12.581 ns ( 59.77 % )
+ Info: Total interconnect delay = 8.469 ns ( 40.23 % )
Info: Fitter routing operations beginning
Info: Router estimated average interconnect usage is 4% of the available device resources
- Info: Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
+ Info: Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X32_Y14 to location X42_Y27
Info: Fitter routing operations ending: elapsed time is 00:00:04
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 269 megabytes
- Info: Processing ended: Fri Dec 17 10:10:34 2010
+ Info: Processing ended: Fri Dec 17 12:27:11 2010
Info: Elapsed time: 00:00:19
Info: Total CPU time (on all processors): 00:00:19
-Fitter Status : Successful - Fri Dec 17 10:10:33 2010
+Fitter Status : Successful - Fri Dec 17 12:27:10 2010
Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
Revision Name : dt
Top-level Entity Name : core_top
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
-Total logic elements : 1,056 / 12,060 ( 9 % )
+Total logic elements : 1,058 / 12,060 ( 9 % )
Total pins : 3 / 173 ( 2 % )
Total virtual pins : 0
Total memory bits : 512 / 239,616 ( < 1 % )
Flow report for dt
-Fri Dec 17 10:10:42 2010
+Fri Dec 17 12:27:19 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+-----------------------------------------------+
-; Flow Status ; Successful - Fri Dec 17 10:10:42 2010 ;
+; Flow Status ; Successful - Fri Dec 17 12:27:18 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
-; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
+; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
; Total pins ; 3 / 173 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 12/17/2010 10:09:48 ;
+; Start date & time ; 12/17/2010 12:26:26 ;
; Main task ; Compilation ;
; Revision Name ; dt ;
+-------------------+---------------------+
+-------------------------------------+--------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+--------------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 91815333562.129257698817483 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 91815333562.129258518625184 ; -- ; -- ; -- ;
; MISC_FILE ; /homes/burban/dt/dt.dpf ; -- ; -- ; -- ;
; MISC_FILE ; /homes/c0726283/calu/dt/dt.dpf ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; core_top ; Top ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:24 ; 1.0 ; -- ; 00:00:20 ;
+; Analysis & Synthesis ; 00:00:23 ; 1.0 ; -- ; 00:00:21 ;
; Fitter ; 00:00:18 ; 1.0 ; -- ; 00:00:18 ;
-; Assembler ; 00:00:02 ; 1.0 ; -- ; 00:00:02 ;
-; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ;
-; Total ; 00:00:45 ; -- ; -- ; 00:00:41 ;
+; Assembler ; 00:00:03 ; 1.0 ; -- ; 00:00:02 ;
+; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; -- ; 00:00:01 ;
+; Total ; 00:00:44 ; -- ; -- ; 00:00:42 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
Analysis & Synthesis report for dt
-Fri Dec 17 10:10:12 2010
+Fri Dec 17 12:26:49 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
- 9. State Machine - |core_top|decode_stage:decode_st|dec_op_inst.op_group
- 10. Registers Removed During Synthesis
- 11. Removed Registers Triggering Further Register Optimizations
- 12. General Register Statistics
- 13. Inverted Register Statistics
- 14. Registers Packed Into Inferred Megafunctions
- 15. Multiplexer Restructuring Statistics (Restructuring Performed)
- 16. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated
- 17. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated
- 18. Parameter Settings for User Entity Instance: fetch_stage:fetch_st
- 19. Parameter Settings for User Entity Instance: fetch_stage:fetch_st|r_w_ram:instruction_ram
- 20. Parameter Settings for User Entity Instance: decode_stage:decode_st
- 21. Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram
- 22. Parameter Settings for User Entity Instance: execute_stage:exec_st
- 23. Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst
- 24. Parameter Settings for User Entity Instance: writeback_stage:writeback_st
- 25. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram
- 26. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart
- 27. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst
- 28. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0
- 29. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
- 30. altsyncram Parameter Settings by Entity Instance
- 31. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart"
- 32. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
- 33. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
- 34. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
- 35. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
- 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
- 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
- 38. Port Connectivity Checks: "execute_stage:exec_st"
- 39. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
- 40. Analysis & Synthesis Messages
+ 9. State Machine - |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state
+ 10. State Machine - |core_top|decode_stage:decode_st|dec_op_inst.op_group
+ 11. Registers Removed During Synthesis
+ 12. Removed Registers Triggering Further Register Optimizations
+ 13. General Register Statistics
+ 14. Inverted Register Statistics
+ 15. Registers Packed Into Inferred Megafunctions
+ 16. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 17. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated
+ 18. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated
+ 19. Parameter Settings for User Entity Instance: fetch_stage:fetch_st
+ 20. Parameter Settings for User Entity Instance: fetch_stage:fetch_st|r_w_ram:instruction_ram
+ 21. Parameter Settings for User Entity Instance: decode_stage:decode_st
+ 22. Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram
+ 23. Parameter Settings for User Entity Instance: execute_stage:exec_st
+ 24. Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst
+ 25. Parameter Settings for User Entity Instance: writeback_stage:writeback_st
+ 26. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram
+ 27. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart
+ 28. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst
+ 29. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst
+ 30. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0
+ 31. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
+ 32. altsyncram Parameter Settings by Entity Instance
+ 33. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst"
+ 34. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart"
+ 35. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
+ 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
+ 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
+ 38. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
+ 39. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
+ 40. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
+ 41. Port Connectivity Checks: "execute_stage:exec_st"
+ 42. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
+ 43. Analysis & Synthesis Messages
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Fri Dec 17 10:10:12 2010 ;
+; Analysis & Synthesis Status ; Successful - Fri Dec 17 12:26:49 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
-; Total logic elements ; 1,142 ;
+; Total logic elements ; 1,143 ;
; Total pins ; 3 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 ;
+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
+; ../cpu/src/rs232_rx_arc.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_rx_arc.vhd ;
+; ../cpu/src/rs232_rx.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_rx.vhd ;
; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/writeback_stage_b.vhd ;
; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/writeback_stage.vhd ;
; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_tx_arc.vhd ;
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
-; Total logic elements ; 1142 ;
-; -- Combinational with no register ; 927 ;
-; -- Register only ; 86 ;
-; -- Combinational with a register ; 129 ;
+; Total logic elements ; 1143 ;
+; -- Combinational with no register ; 928 ;
+; -- Register only ; 85 ;
+; -- Combinational with a register ; 130 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 467 ;
-; -- 3 input functions ; 447 ;
+; -- 4 input functions ; 473 ;
+; -- 3 input functions ; 443 ;
; -- 2 input functions ; 123 ;
; -- 1 input functions ; 18 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 936 ;
+; -- normal mode ; 937 ;
; -- arithmetic mode ; 206 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 7 ;
-; -- asynchronous clear/load mode ; 202 ;
+; -- asynchronous clear/load mode ; 203 ;
; ; ;
; Total registers ; 215 ;
; Total logic cells in carry chains ; 214 ;
; Total memory bits ; 512 ;
; Maximum fan-out node ; sys_clk ;
; Maximum fan-out ; 279 ;
-; Total fan-out ; 4453 ;
-; Average fan-out ; 3.68 ;
+; Total fan-out ; 4464 ;
+; Average fan-out ; 3.69 ;
+---------------------------------------------+---------+
+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1142 (1) ; 215 ; 512 ; 3 ; 0 ; 927 (1) ; 86 (0) ; 129 (0) ; 214 (0) ; 0 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 109 (101) ; 72 ; 512 ; 0 ; 0 ; 37 (29) ; 52 (52) ; 20 (20) ; 11 (11) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |core_top ; 1143 (1) ; 215 ; 512 ; 3 ; 0 ; 928 (1) ; 85 (0) ; 130 (0) ; 214 (0) ; 0 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 106 (99) ; 72 ; 512 ; 0 ; 0 ; 34 (27) ; 51 (51) ; 21 (21) ; 11 (11) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 826 (185) ; 67 ; 0 ; 0 ; 0 ; 759 (149) ; 20 (1) ; 47 (35) ; 171 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 576 (255) ; 0 ; 0 ; 0 ; 0 ; 576 (255) ; 0 (0) ; 0 (0) ; 141 (43) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |execute_stage:exec_st| ; 831 (185) ; 67 ; 0 ; 0 ; 0 ; 764 (149) ; 20 (1) ; 47 (35) ; 171 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 581 (259) ; 0 ; 0 ; 0 ; 0 ; 581 (259) ; 0 (0) ; 0 (0) ; 141 (43) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:or_inst| ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
+; |exec_op:or_inst| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 34 (34) ; 19 (19) ; 12 (12) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
; |fetch_stage:fetch_st| ; 39 (30) ; 17 ; 0 ; 0 ; 0 ; 22 (19) ; 11 (11) ; 6 (0) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 167 (53) ; 59 ; 0 ; 0 ; 0 ; 108 (49) ; 3 (1) ; 56 (3) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
+; |writeback_stage:writeback_st| ; 166 (49) ; 59 ; 0 ; 0 ; 0 ; 107 (45) ; 3 (1) ; 56 (3) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
; |extension_uart:uart| ; 108 (14) ; 49 ; 0 ; 0 ; 0 ; 59 (4) ; 2 (2) ; 47 (8) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+; |r_w_ram:data_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
+Encoding Type: One-Hot
++---------------------------------------------------------------------------------------------------------+
+; State Machine - |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state ;
++------------------+-----------------+-----------------+----------------+------------------+--------------+
+; Name ; state.POST_STOP ; state.READ_STOP ; state.READ_BIT ; state.READ_START ; state.IDLE ;
++------------------+-----------------+-----------------+----------------+------------------+--------------+
+; state.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; state.READ_START ; 0 ; 0 ; 0 ; 1 ; 1 ;
+; state.READ_BIT ; 0 ; 0 ; 1 ; 0 ; 1 ;
+; state.READ_STOP ; 0 ; 1 ; 0 ; 0 ; 1 ;
+; state.POST_STOP ; 1 ; 0 ; 0 ; 0 ; 1 ;
++------------------+-----------------+-----------------+----------------+------------------+--------------+
+
+
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |core_top|decode_stage:decode_st|dec_op_inst.op_group ;
+--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+-------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-; Register name ; Reason for Removal ;
-+-------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0,2,5,8,10..14,16..18,20,22] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0,2,5,8,10..14,16..18,20,22] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.condition[1..3] ; Stuck at VCC due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.op_detail[5] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.displacement[0,2,5,8,10..31] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.saddr1[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.saddr2[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.daddr[1,3] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|reg.res_addr[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|rtw_rec.immediate[5,7,9..11,13,15] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[23] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[1] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4,6] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[19] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[15] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[23] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[1] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[4,6] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[19] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[3] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[15] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[7] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ;
-; decode_stage:decode_st|dec_op_inst.daddr[2] ; Lost fanout ;
-; execute_stage:exec_st|reg.res_addr[0] ; Merged with execute_stage:exec_st|reg.res_addr[2] ;
-; decode_stage:decode_st|rtw_rec.immediate[18,21,23..27,29..30] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
-; decode_stage:decode_st|rtw_rec.immediate[16] ; Merged with decode_stage:decode_st|rtw_rec.immediate[28] ;
-; decode_stage:decode_st|rtw_rec.immediate[20] ; Merged with decode_stage:decode_st|rtw_rec.immediate[22] ;
-; decode_stage:decode_st|rtw_rec.immediate[17] ; Merged with decode_stage:decode_st|rtw_rec.immediate[19] ;
-; decode_stage:decode_st|rtw_rec.immediate[1] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
-; decode_stage:decode_st|dec_op_inst.displacement[7] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[9] ;
-; decode_stage:decode_st|dec_op_inst.displacement[4] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[6] ;
-; decode_stage:decode_st|dec_op_inst.saddr2[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr2[2] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[1] ; Merged with decode_stage:decode_st|dec_op_inst.op_detail[2] ;
-; decode_stage:decode_st|rtw_rec.immediate[19,22,28] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
-; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; Lost fanout ;
-; decode_stage:decode_st|rtw_rec.immediate[31] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.OR_OP ;
-; decode_stage:decode_st|rtw_rec.immediate[8] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ;
-; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
-; Total Number of Removed Registers = 261 ; ;
-+-------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Removed Registers Triggering Further Register Optimizations ;
-+-----------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------+
-; Register name ; Reason for Removal ; Registers Removed due to This Register ;
-+-----------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------+
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.op_detail[5], ;
-; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.saddr1[3], ;
-; ; ; decode_stage:decode_st|dec_op_inst.saddr1[1], ;
-; ; ; decode_stage:decode_st|dec_op_inst.saddr2[3], ;
-; ; ; decode_stage:decode_st|dec_op_inst.saddr2[1], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[15], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[13], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[11], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[10], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[9], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[7], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[5] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[3], ;
-; ; due to stuck port data_in ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo, ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[22] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[3], execute_stage:exec_st|reg.res_addr[3] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[20] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[1], execute_stage:exec_st|reg.res_addr[1] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[30] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[2] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[1] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[14] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[14] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[13] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[13] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[12] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[12] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[11] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[11] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[10] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[10] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[8] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[5] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[5] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[2] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[0] ;
-; ; due to stuck port data_in ; ;
-+-----------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+; Register name ; Reason for Removal ;
++------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+; writeback_stage:writeback_st|bus_rx ; Stuck at VCC due to stuck port data_in ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; Lost fanout ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0,2,5,8,10..15,17..18,20,22] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0,2,5,8,10..15,17..18,20,22] ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.condition[1..3] ; Stuck at VCC due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.op_detail[5] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.displacement[0,2,5,8,10..31] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.saddr1[3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.saddr2[1,3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.daddr[1,3] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|reg.res_addr[1,3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|rtw_rec.immediate[5,7..8,10..11,15] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[23] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[1] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4,6] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[19] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[23] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[1] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[4,6] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[19] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[3] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[7] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ;
+; decode_stage:decode_st|dec_op_inst.daddr[2] ; Lost fanout ;
+; execute_stage:exec_st|reg.res_addr[0] ; Merged with execute_stage:exec_st|reg.res_addr[2] ;
+; decode_stage:decode_st|rtw_rec.immediate[18,21,23..28,30] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
+; decode_stage:decode_st|rtw_rec.immediate[16] ; Merged with decode_stage:decode_st|rtw_rec.immediate[29] ;
+; decode_stage:decode_st|rtw_rec.immediate[20] ; Merged with decode_stage:decode_st|rtw_rec.immediate[22] ;
+; decode_stage:decode_st|rtw_rec.immediate[17] ; Merged with decode_stage:decode_st|rtw_rec.immediate[19] ;
+; decode_stage:decode_st|rtw_rec.immediate[12] ; Merged with decode_stage:decode_st|rtw_rec.immediate[14] ;
+; decode_stage:decode_st|rtw_rec.immediate[1] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
+; decode_stage:decode_st|dec_op_inst.displacement[7] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[9] ;
+; decode_stage:decode_st|dec_op_inst.displacement[4] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[6] ;
+; decode_stage:decode_st|dec_op_inst.saddr1[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr1[2] ;
+; decode_stage:decode_st|dec_op_inst.saddr2[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr2[2] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[1] ; Merged with decode_stage:decode_st|dec_op_inst.op_detail[2] ;
+; decode_stage:decode_st|rtw_rec.immediate[19,22,29] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
+; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0..31] ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0..31] ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP ; Lost fanout ;
+; decode_stage:decode_st|rtw_rec.immediate[31] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.OR_OP ;
+; decode_stage:decode_st|rtw_rec.immediate[9] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ;
+; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
+; Total Number of Removed Registers = 332 ; ;
++------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations ;
++-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
+; Register name ; Reason for Removal ; Registers Removed due to This Register ;
++-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.op_detail[5], ;
+; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.saddr1[3], ;
+; ; ; decode_stage:decode_st|dec_op_inst.saddr2[3], ;
+; ; ; decode_stage:decode_st|dec_op_inst.saddr2[1], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[15], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[11], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[10], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[8], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[7], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[5] ;
+; writeback_stage:writeback_st|bus_rx ; Stuck at VCC ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[31], ;
+; ; due to stuck port data_in ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[30], ;
+; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[29], ;
+; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[28], ;
+; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[27], ;
+; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[26], ;
+; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[25], ;
+; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[24] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[3], ;
+; ; due to stuck port data_in ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo, ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[22] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[3], execute_stage:exec_st|reg.res_addr[3] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[20] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[1], execute_stage:exec_st|reg.res_addr[1] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[30] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[2] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[1] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[14] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[14] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[13] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[13] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[12] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[12] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[11] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[11] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[10] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[10] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[8] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[5] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[5] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[2] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[0] ;
+; ; due to stuck port data_in ; ;
++-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
+------------------------------------------------------+
; Total registers ; 215 ;
; Number of registers using Synchronous Clear ; 4 ;
; Number of registers using Synchronous Load ; 6 ;
-; Number of registers using Asynchronous Clear ; 191 ;
+; Number of registers using Asynchronous Clear ; 192 ;
; Number of registers using Asynchronous Load ; 11 ;
-; Number of registers using Clock Enable ; 44 ;
+; Number of registers using Clock Enable ; 43 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 2 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 2 ;
; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 2 ;
; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 2 ;
; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 2 ;
; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 2 ;
; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 2 ;
; decode_stage:decode_st|dec_op_inst.condition[0] ; 1 ;
; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 4 ;
; Total number of inverted registers = 24 ; ;
+------------------------------------------------------------+-----------------------------------------------------+------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
-; 3:1 ; 21 bits ; 42 LEs ; 21 LEs ; 21 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ;
-; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |core_top|decode_stage:decode_st|dec_op_inst.displacement[1] ;
-; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ;
-; 5:1 ; 14 bits ; 42 LEs ; 28 LEs ; 14 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[30] ;
-; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[21] ;
-; 18:1 ; 3 bits ; 36 LEs ; 3 LEs ; 33 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ;
-; 9:1 ; 5 bits ; 30 LEs ; 25 LEs ; 5 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[11] ;
-; 9:1 ; 13 bits ; 78 LEs ; 65 LEs ; 13 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[17] ;
-; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[6] ;
-; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[25] ;
-; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[1] ;
-; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[29] ;
-; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ;
-; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|left_operand[13] ;
-; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
-; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[7] ;
-; 4:1 ; 25 bits ; 50 LEs ; 50 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[14] ;
-; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector53 ;
-; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[2] ;
-; 5:1 ; 6 bits ; 18 LEs ; 12 LEs ; 6 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[3] ;
-; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector107 ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
+; 3:1 ; 21 bits ; 42 LEs ; 21 LEs ; 21 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25] ;
+; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |core_top|decode_stage:decode_st|dec_op_inst.displacement[1] ;
+; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ;
+; 5:1 ; 14 bits ; 42 LEs ; 28 LEs ; 14 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[31] ;
+; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[19] ;
+; 18:1 ; 3 bits ; 36 LEs ; 3 LEs ; 33 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ;
+; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1] ;
+; 9:1 ; 5 bits ; 30 LEs ; 25 LEs ; 5 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[7] ;
+; 9:1 ; 13 bits ; 78 LEs ; 65 LEs ; 13 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[21] ;
+; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[4] ;
+; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[25] ;
+; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[1] ;
+; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[29] ;
+; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ;
+; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|left_operand[19] ;
+; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
+; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[10] ;
+; 4:1 ; 26 bits ; 52 LEs ; 52 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[30] ;
+; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector48 ;
+; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[0] ;
+; 5:1 ; 6 bits ; 18 LEs ; 12 LEs ; 6 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[6] ;
+; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector97 ;
+; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|Selector0 ;
+; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|Selector2 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
++----------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst ;
++----------------+-------+---------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+---------------------------------------------------------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
++----------------+-------+---------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ;
+------------------------------------+--------------------------------------+----------------------------------------+
+-------------------------------------------+-------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst" ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+; new_rx_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; rx_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
+--------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart" ;
+----------+--------+----------+-------------------------------------------------------------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 10:09:47 2010
+ Info: Processing started: Fri Dec 17 12:26:25 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dt -c dt
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rs232_rx_arc.vhd
+ Info: Found design unit 1: rs232_rx-beh
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rs232_rx.vhd
+ Info: Found entity 1: rs232_rx
Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/writeback_stage_b.vhd
Info: Found design unit 1: writeback_stage-behav
Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/writeback_stage.vhd
Info: Elaborating entity "extension_gpm" for hierarchy "execute_stage:exec_st|extension_gpm:gpmp_inst"
Info: Elaborating entity "writeback_stage" for hierarchy "writeback_stage:writeback_st"
Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(14): object "data_ram_read_ext" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(18): object "ext_timer" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(18): object "ext_gpmp" assigned a value but never read
-Warning (10812): VHDL warning at writeback_stage_b.vhd(152): sensitivity list already contains wb_reg_nxt
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(19): object "ext_timer" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(19): object "ext_gpmp" assigned a value but never read
+Warning (10812): VHDL warning at writeback_stage_b.vhd(164): sensitivity list already contains wb_reg_nxt
Info: Elaborating entity "extension_uart" for hierarchy "writeback_stage:writeback_st|extension_uart:uart"
+Warning (10036): Verilog HDL or VHDL warning at extension_uart_b.vhd(15): object "new_bus_rx" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at extension_uart_b.vhd(17): object "rx_data" assigned a value but never read
Info: Elaborating entity "rs232_tx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst"
+Info: Elaborating entity "rs232_rx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst"
Info: Inferred 2 megafunctions from design logic
Info: Inferred altsyncram megafunction from the following design logic: "decode_stage:decode_st|r2_w_ram:register_ram|ram~37"
Info: Parameter OPERATION_MODE set to DUAL_PORT
Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_emk1.tdf
Info: Found entity 1: altsyncram_emk1
+Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1"
+Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1" with the following parameter:
+ Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
+ Info: Parameter "WIDTH_A" = "32"
+ Info: Parameter "WIDTHAD_A" = "4"
+ Info: Parameter "NUMWORDS_A" = "16"
+ Info: Parameter "WIDTH_B" = "32"
+ Info: Parameter "WIDTHAD_B" = "4"
+ Info: Parameter "NUMWORDS_B" = "16"
+ Info: Parameter "ADDRESS_ACLR_A" = "NONE"
+ Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
+ Info: Parameter "ADDRESS_ACLR_B" = "NONE"
+ Info: Parameter "OUTDATA_ACLR_B" = "NONE"
+ Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
+ Info: Parameter "INDATA_ACLR_A" = "NONE"
+ Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
+ Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
+ Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info: Registers with preset signals will power-up high
-Info: 117 registers lost all their fanouts during netlist optimizations. The first 117 are displayed below.
+Info: 187 registers lost all their fanouts during netlist optimizations. The first 187 are displayed below.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign" lost all its fanouts during netlist optimizations.
Info: Register "decode_stage:decode_st|dec_op_inst.daddr[2]" lost all its fanouts during netlist optimizations.
Info: Register "decode_stage:decode_st|dec_op_inst.op_group.AND_OP" lost all its fanouts during netlist optimizations.
Info: Register "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[31]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[30]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[29]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[28]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[27]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[26]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[25]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[24]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[23]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[22]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[21]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[20]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[19]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[18]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[17]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[16]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[6]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[5]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[3]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[2]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[28]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[27]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[25]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[11]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[12]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[13]" lost all its fanouts during netlist optimizations.
Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM"
Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM"
Info: Generating hard_block partition "hard_block:auto_generated_inst"
-Info: Implemented 1209 device resources after synthesis - the final resource count might be different
+Info: Implemented 1210 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 1 output pins
- Info: Implemented 1142 logic cells
+ Info: Implemented 1143 logic cells
Info: Implemented 64 RAM segments
-Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
- Info: Peak virtual memory: 267 megabytes
- Info: Processing ended: Fri Dec 17 10:10:12 2010
- Info: Elapsed time: 00:00:25
- Info: Total CPU time (on all processors): 00:00:21
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
+ Info: Peak virtual memory: 268 megabytes
+ Info: Processing ended: Fri Dec 17 12:26:49 2010
+ Info: Elapsed time: 00:00:24
+ Info: Total CPU time (on all processors): 00:00:22
-Analysis & Synthesis Status : Successful - Fri Dec 17 10:10:12 2010
+Analysis & Synthesis Status : Successful - Fri Dec 17 12:26:49 2010
Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
Revision Name : dt
Top-level Entity Name : core_top
Family : Cyclone
-Total logic elements : 1,142
+Total logic elements : 1,143
Total pins : 3
Total virtual pins : 0
Total memory bits : 512
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
+set_location_assignment PIN_166 -to bus_tx
+set_location_assignment PIN_152 -to sys_clk
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
+set_location_assignment PIN_42 -to sys_res
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx_arc.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
-set_location_assignment PIN_166 -to bus_tx
-set_location_assignment PIN_152 -to sys_clk
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-
-set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
-set_location_assignment PIN_42 -to sys_res
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Classic Timing Analyzer report for dt
-Fri Dec 17 10:10:42 2010
+Fri Dec 17 12:27:19 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
-; Worst-case tsu ; N/A ; None ; 16.692 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; -- ; sys_clk ; 0 ;
-; Worst-case tco ; N/A ; None ; 8.362 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
-; Worst-case th ; N/A ; None ; -8.416 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; -- ; sys_clk ; 0 ;
-; Clock Setup: 'sys_clk' ; N/A ; None ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
+; Worst-case tsu ; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; -- ; sys_clk ; 0 ;
+; Worst-case tco ; N/A ; None ; 10.165 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -8.849 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; -- ; sys_clk ; 0 ;
+; Clock Setup: 'sys_clk' ; N/A ; None ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
-; Minimum Core Junction Temperature ; 0 ; ; ; ;
-; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
-; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
-; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
-; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
-; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
-; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
-; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
-; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
-; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
-; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
-; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
-; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
-; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
-; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
-; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
-; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
-; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
-; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
-; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
-; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
-; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
-; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
-; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
-; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
-; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
-; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
-; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
-; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
-; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
-; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
-; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
-; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
-; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
-; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
-; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
-; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
-; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
-; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
-; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
-; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
-; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
-; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
-; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
-; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
-; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
-; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
-; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
-; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
-; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
-; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
-; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
-; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
-; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
-; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
-; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
-; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
-; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
-; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
-; N/A ; 49.82 MHz ( period = 20.073 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.812 ns ;
-; N/A ; 49.82 MHz ( period = 20.073 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.812 ns ;
-; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
-; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
-; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
-; N/A ; 49.97 MHz ( period = 20.012 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.819 ns ;
-; N/A ; 49.97 MHz ( period = 20.012 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.819 ns ;
-; N/A ; 49.98 MHz ( period = 20.008 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.688 ns ;
-; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
-; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
-; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
-; N/A ; 50.16 MHz ( period = 19.938 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.736 ns ;
-; N/A ; 50.16 MHz ( period = 19.938 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.736 ns ;
-; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
-; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
-; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
-; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
-; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
-; N/A ; 50.55 MHz ( period = 19.781 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.461 ns ;
-; N/A ; 50.66 MHz ( period = 19.739 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.537 ns ;
-; N/A ; 50.66 MHz ( period = 19.739 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.537 ns ;
-; N/A ; 50.71 MHz ( period = 19.720 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
-; N/A ; 50.72 MHz ( period = 19.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.516 ns ;
-; N/A ; 50.72 MHz ( period = 19.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.516 ns ;
-; N/A ; 50.74 MHz ( period = 19.709 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.457 ns ;
-; N/A ; 50.89 MHz ( period = 19.649 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
-; N/A ; 50.90 MHz ( period = 19.646 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.385 ns ;
-; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
-; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
-; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
-; N/A ; 51.03 MHz ( period = 19.597 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 19.277 ns ;
-; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
-; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
-; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
-; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
-; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
-; N/A ; 51.05 MHz ( period = 19.588 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.395 ns ;
-; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
-; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
-; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
-; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
-; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
-; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
-; N/A ; 51.14 MHz ( period = 19.553 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.351 ns ;
-; N/A ; 51.14 MHz ( period = 19.553 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.351 ns ;
-; N/A ; 51.15 MHz ( period = 19.550 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 19.230 ns ;
-; N/A ; 51.25 MHz ( period = 19.514 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.312 ns ;
-; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
-; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
-; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
-; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
-; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
-; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
-; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
-; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
-; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
-; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
-; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
-; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
-; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
-; N/A ; 51.37 MHz ( period = 19.465 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.145 ns ;
-; N/A ; 51.42 MHz ( period = 19.447 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.186 ns ;
-; N/A ; 51.45 MHz ( period = 19.436 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.175 ns ;
-; N/A ; 51.48 MHz ( period = 19.426 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.165 ns ;
-; N/A ; 51.51 MHz ( period = 19.415 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.154 ns ;
-; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
-; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
-; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
-; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
-; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
-; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
-; N/A ; 51.77 MHz ( period = 19.315 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.113 ns ;
-; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
-; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
-; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
-; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
-; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
-; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
-; N/A ; 51.82 MHz ( period = 19.298 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 19.046 ns ;
-; N/A ; 51.83 MHz ( period = 19.294 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.092 ns ;
-; N/A ; 51.92 MHz ( period = 19.261 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.000 ns ;
-; N/A ; 51.95 MHz ( period = 19.251 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.999 ns ;
-; N/A ; 51.95 MHz ( period = 19.250 ns ) ; execute_stage:exec_st|reg.alu_jump ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 18.989 ns ;
-; N/A ; 51.98 MHz ( period = 19.239 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.037 ns ;
-; N/A ; 51.98 MHz ( period = 19.239 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.037 ns ;
-; N/A ; 52.18 MHz ( period = 19.166 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.914 ns ;
-; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
-; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
-; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
-; N/A ; 52.28 MHz ( period = 19.129 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 18.927 ns ;
-; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
-; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
-; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
-; N/A ; 52.36 MHz ( period = 19.098 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.837 ns ;
-; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
-; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
-; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
-; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
-; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
-; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
-; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
-; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
-; N/A ; 52.52 MHz ( period = 19.042 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.849 ns ;
-; N/A ; 52.52 MHz ( period = 19.042 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.849 ns ;
-; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
-; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
-; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
-; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
-; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
-; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
-; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.764 ns ;
-; N/A ; 52.62 MHz ( period = 19.004 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.743 ns ;
-; N/A ; 52.62 MHz ( period = 19.003 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 18.309 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.34 MHz ( period = 21.578 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.884 ns ;
+; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
+; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
+; N/A ; 46.56 MHz ( period = 21.477 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.783 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.89 MHz ( period = 21.327 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.633 ns ;
+; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
+; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
+; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
+; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
+; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
+; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
+; N/A ; 46.97 MHz ( period = 21.291 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 21.030 ns ;
+; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
+; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
+; N/A ; 47.00 MHz ( period = 21.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.583 ns ;
+; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
+; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
+; N/A ; 47.11 MHz ( period = 21.226 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.532 ns ;
+; N/A ; 47.19 MHz ( period = 21.190 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.929 ns ;
+; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
+; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
+; N/A ; 47.56 MHz ( period = 21.026 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.332 ns ;
+; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
+; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
+; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
+; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
+; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
+; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
+; N/A ; 47.58 MHz ( period = 21.019 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.758 ns ;
+; N/A ; 47.64 MHz ( period = 20.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.729 ns ;
+; N/A ; 47.81 MHz ( period = 20.918 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 20.657 ns ;
+; N/A ; 48.27 MHz ( period = 20.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.457 ns ;
+; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
+; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
+; N/A ; 48.45 MHz ( period = 20.640 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.955 ns ;
+; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
+; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
+; N/A ; 49.32 MHz ( period = 20.277 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.583 ns ;
+; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
+; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
+; N/A ; 49.37 MHz ( period = 20.256 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.562 ns ;
+; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
+; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
+; N/A ; 49.37 MHz ( period = 20.255 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.561 ns ;
+; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
+; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
+; N/A ; 49.39 MHz ( period = 20.249 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.555 ns ;
+; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
+; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
+; N/A ; 49.40 MHz ( period = 20.242 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.481 ns ;
+; N/A ; 49.46 MHz ( period = 20.220 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.959 ns ;
+; N/A ; 49.46 MHz ( period = 20.219 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.958 ns ;
+; N/A ; 49.47 MHz ( period = 20.213 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.952 ns ;
+; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
+; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
+; N/A ; 49.48 MHz ( period = 20.211 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.526 ns ;
+; N/A ; 49.49 MHz ( period = 20.206 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.878 ns ;
+; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
+; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
+; N/A ; 49.60 MHz ( period = 20.163 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.469 ns ;
+; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 49.60 MHz ( period = 20.162 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
+; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
+; N/A ; 49.61 MHz ( period = 20.156 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.462 ns ;
+; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
+; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
+; N/A ; 49.63 MHz ( period = 20.149 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
+; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
+; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
+; N/A ; 49.64 MHz ( period = 20.146 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.452 ns ;
+; N/A ; 49.71 MHz ( period = 20.118 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.866 ns ;
+; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
+; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
+; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
+; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
+; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
+; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
+; N/A ; 49.92 MHz ( period = 20.032 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.771 ns ;
+; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
+; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
+; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
+; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
+; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
+; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
+; N/A ; 49.95 MHz ( period = 20.019 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.758 ns ;
+; N/A ; 50.14 MHz ( period = 19.943 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[17] ; sys_clk ; sys_clk ; None ; None ; 19.691 ns ;
+; N/A ; 50.17 MHz ( period = 19.931 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.670 ns ;
+; N/A ; 50.21 MHz ( period = 19.918 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.657 ns ;
+; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
+; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
+; N/A ; 50.22 MHz ( period = 19.911 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.150 ns ;
+; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
+; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
+; N/A ; 50.26 MHz ( period = 19.895 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.201 ns ;
+; N/A ; 50.28 MHz ( period = 19.888 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; sys_clk ; sys_clk ; None ; None ; 19.627 ns ;
+; N/A ; 50.28 MHz ( period = 19.887 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; sys_clk ; sys_clk ; None ; None ; 19.626 ns ;
+; N/A ; 50.30 MHz ( period = 19.881 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; sys_clk ; sys_clk ; None ; None ; 19.620 ns ;
+; N/A ; 50.32 MHz ( period = 19.874 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; sys_clk ; sys_clk ; None ; None ; 19.546 ns ;
+; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
+; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
+; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
+; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
+; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
+; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
+; N/A ; 50.32 MHz ( period = 19.871 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.601 ns ;
+; N/A ; 50.36 MHz ( period = 19.859 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.598 ns ;
+; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
+; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
+; N/A ; 50.48 MHz ( period = 19.808 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.114 ns ;
+; N/A ; 50.58 MHz ( period = 19.772 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.511 ns ;
+; N/A ; 50.58 MHz ( period = 19.770 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.500 ns ;
+; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
+; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
+; N/A ; 50.63 MHz ( period = 19.753 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.059 ns ;
+; N/A ; 50.68 MHz ( period = 19.731 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.470 ns ;
+; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 50.69 MHz ( period = 19.729 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 50.72 MHz ( period = 19.718 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.457 ns ;
+; N/A ; 50.72 MHz ( period = 19.717 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 19.456 ns ;
+; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
+; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
+; N/A ; 50.72 MHz ( period = 19.715 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.021 ns ;
+; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
+; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
+; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
+; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
+; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
+; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
+; N/A ; 50.73 MHz ( period = 19.714 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.453 ns ;
+; N/A ; 50.78 MHz ( period = 19.691 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[12] ; sys_clk ; sys_clk ; None ; None ; 19.363 ns ;
+; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
+; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
+; N/A ; 50.86 MHz ( period = 19.660 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; sys_clk ; sys_clk ; None ; None ; 18.966 ns ;
+; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
+; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
+; N/A ; 50.87 MHz ( period = 19.658 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 18.964 ns ;
+; N/A ; 50.90 MHz ( period = 19.648 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[19] ; sys_clk ; sys_clk ; None ; None ; 19.387 ns ;
+; N/A ; 50.95 MHz ( period = 19.628 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.367 ns ;
+; N/A ; 50.97 MHz ( period = 19.621 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[10] ; sys_clk ; sys_clk ; None ; None ; 19.360 ns ;
+; N/A ; 50.99 MHz ( period = 19.613 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.352 ns ;
+; N/A ; 51.05 MHz ( period = 19.587 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 19.326 ns ;
+; N/A ; 51.10 MHz ( period = 19.570 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.300 ns ;
+; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
+; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
+; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
+; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
+; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
+; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
+; N/A ; 51.39 MHz ( period = 19.460 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.199 ns ;
+; N/A ; 51.44 MHz ( period = 19.440 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 19.179 ns ;
+; N/A ; 51.47 MHz ( period = 19.428 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.167 ns ;
+; N/A ; 51.51 MHz ( period = 19.413 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.152 ns ;
+; N/A ; 51.55 MHz ( period = 19.400 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[7] ; sys_clk ; sys_clk ; None ; None ; 18.639 ns ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------+--------------+------------+---------+------------------------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+---------+------------------------------------------------------------------+----------+
-; N/A ; None ; 16.692 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
-; N/A ; None ; 16.689 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
-; N/A ; None ; 16.688 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
-; N/A ; None ; 16.686 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[15] ; sys_clk ;
-; N/A ; None ; 16.684 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
-; N/A ; None ; 16.683 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
-; N/A ; None ; 16.681 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
-; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
-; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
-; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
-; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
-; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
-; N/A ; None ; 14.759 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
-; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
-; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
-; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
-; N/A ; None ; 14.673 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
-; N/A ; None ; 14.673 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
-; N/A ; None ; 14.394 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
-; N/A ; None ; 14.381 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
-; N/A ; None ; 14.248 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
-; N/A ; None ; 13.957 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
-; N/A ; None ; 13.957 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
-; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
-; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
-; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
-; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
-; N/A ; None ; 13.742 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
-; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
-; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
-; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
-; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
-; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
-; N/A ; None ; 13.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
-; N/A ; None ; 13.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
-; N/A ; None ; 13.375 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
-; N/A ; None ; 13.265 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
-; N/A ; None ; 13.205 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
-; N/A ; None ; 13.126 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
-; N/A ; None ; 13.126 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
-; N/A ; None ; 12.974 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
-; N/A ; None ; 12.974 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
-; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
-; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
-; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
-; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
-; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
-; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
-; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
-; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
-; N/A ; None ; 12.849 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
-; N/A ; None ; 12.769 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
-; N/A ; None ; 12.542 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
-; N/A ; None ; 12.384 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
-; N/A ; None ; 12.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
-; N/A ; None ; 12.255 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
-; N/A ; None ; 12.236 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
-; N/A ; None ; 12.158 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
-; N/A ; None ; 12.154 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
-; N/A ; None ; 12.149 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
-; N/A ; None ; 12.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
-; N/A ; None ; 12.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
-; N/A ; None ; 12.033 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
-; N/A ; None ; 12.027 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
-; N/A ; None ; 11.977 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
-; N/A ; None ; 11.927 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
-; N/A ; None ; 11.914 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
-; N/A ; None ; 11.890 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
-; N/A ; None ; 11.889 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
-; N/A ; None ; 11.881 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
-; N/A ; None ; 11.764 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
-; N/A ; None ; 11.700 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
-; N/A ; None ; 11.660 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
-; N/A ; None ; 11.555 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
-; N/A ; None ; 11.555 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
-; N/A ; None ; 11.537 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
-; N/A ; None ; 11.535 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
-; N/A ; None ; 11.318 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
-; N/A ; None ; 11.315 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
-; N/A ; None ; 11.255 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
-; N/A ; None ; 11.184 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
-; N/A ; None ; 11.144 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
-; N/A ; None ; 11.127 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
-; N/A ; None ; 11.007 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
-; N/A ; None ; 10.999 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
-; N/A ; None ; 10.955 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
-; N/A ; None ; 10.830 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
-; N/A ; None ; 10.734 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
-; N/A ; None ; 10.714 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
-; N/A ; None ; 10.601 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
-; N/A ; None ; 10.573 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
-; N/A ; None ; 10.408 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
-; N/A ; None ; 10.117 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
-; N/A ; None ; 9.756 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
+; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
+; N/A ; None ; 18.965 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
+; N/A ; None ; 18.960 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
+; N/A ; None ; 18.960 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
+; N/A ; None ; 18.958 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ; sys_clk ;
+; N/A ; None ; 17.463 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
+; N/A ; None ; 16.832 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
+; N/A ; None ; 14.582 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
+; N/A ; None ; 14.522 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
+; N/A ; None ; 14.522 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
+; N/A ; None ; 14.521 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
+; N/A ; None ; 14.516 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
+; N/A ; None ; 14.493 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
+; N/A ; None ; 14.024 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
+; N/A ; None ; 13.946 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
+; N/A ; None ; 13.872 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
+; N/A ; None ; 13.847 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
+; N/A ; None ; 13.783 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
+; N/A ; None ; 13.783 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
+; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
+; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
+; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
+; N/A ; None ; 13.761 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
+; N/A ; None ; 13.711 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
+; N/A ; None ; 13.711 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
+; N/A ; None ; 13.661 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
+; N/A ; None ; 13.515 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
+; N/A ; None ; 13.515 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
+; N/A ; None ; 13.480 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
+; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
+; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
+; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
+; N/A ; None ; 13.442 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
+; N/A ; None ; 13.410 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
+; N/A ; None ; 13.394 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
+; N/A ; None ; 13.358 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
+; N/A ; None ; 13.319 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
+; N/A ; None ; 13.319 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
+; N/A ; None ; 13.239 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
+; N/A ; None ; 13.166 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
+; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
+; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
+; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
+; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
+; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
+; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
+; N/A ; None ; 13.127 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
+; N/A ; None ; 13.121 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
+; N/A ; None ; 13.109 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
+; N/A ; None ; 13.015 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
+; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
+; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
+; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
+; N/A ; None ; 12.971 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
+; N/A ; None ; 12.931 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
+; N/A ; None ; 12.853 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
+; N/A ; None ; 12.826 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
+; N/A ; None ; 12.762 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
+; N/A ; None ; 12.742 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
+; N/A ; None ; 12.687 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
+; N/A ; None ; 12.680 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
+; N/A ; None ; 12.550 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
+; N/A ; None ; 12.445 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
+; N/A ; None ; 12.418 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
+; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
+; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
+; N/A ; None ; 12.396 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
+; N/A ; None ; 12.184 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
+; N/A ; None ; 12.152 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
+; N/A ; None ; 12.140 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
+; N/A ; None ; 12.139 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
+; N/A ; None ; 12.113 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
+; N/A ; None ; 12.113 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
+; N/A ; None ; 12.108 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
+; N/A ; None ; 11.975 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
+; N/A ; None ; 11.925 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
+; N/A ; None ; 11.648 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
+; N/A ; None ; 11.375 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
+; N/A ; None ; 11.324 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
+; N/A ; None ; 11.324 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
+; N/A ; None ; 11.234 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
+; N/A ; None ; 11.169 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
+; N/A ; None ; 11.158 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
+; N/A ; None ; 11.092 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
+; N/A ; None ; 10.824 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
+; N/A ; None ; 10.819 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
+; N/A ; None ; 10.809 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
+; N/A ; None ; 10.784 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
+; N/A ; None ; 10.648 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
+; N/A ; None ; 9.786 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
+; N/A ; None ; 9.782 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
+; N/A ; None ; 9.296 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
+; N/A ; None ; 9.295 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
+; N/A ; None ; 8.901 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
+-------+--------------+------------+---------+------------------------------------------------------------------+----------+
+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
-; N/A ; None ; 8.362 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
+; N/A ; None ; 10.165 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
+---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
-; N/A ; None ; -8.416 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
-; N/A ; None ; -9.704 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
-; N/A ; None ; -10.065 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
-; N/A ; None ; -10.356 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
-; N/A ; None ; -10.521 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
-; N/A ; None ; -10.549 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
-; N/A ; None ; -10.662 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
-; N/A ; None ; -10.682 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
-; N/A ; None ; -10.778 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
-; N/A ; None ; -10.903 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
-; N/A ; None ; -10.947 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
-; N/A ; None ; -10.955 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
-; N/A ; None ; -11.075 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
-; N/A ; None ; -11.092 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
-; N/A ; None ; -11.132 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
-; N/A ; None ; -11.203 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
-; N/A ; None ; -11.263 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
-; N/A ; None ; -11.266 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
-; N/A ; None ; -11.483 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
-; N/A ; None ; -11.485 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
-; N/A ; None ; -11.503 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
-; N/A ; None ; -11.503 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
-; N/A ; None ; -11.608 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
-; N/A ; None ; -11.648 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
-; N/A ; None ; -11.662 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
-; N/A ; None ; -11.662 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[15] ; sys_clk ;
-; N/A ; None ; -11.663 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
-; N/A ; None ; -11.664 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
-; N/A ; None ; -11.665 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
-; N/A ; None ; -11.712 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
-; N/A ; None ; -11.829 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
-; N/A ; None ; -11.837 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
-; N/A ; None ; -11.838 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
-; N/A ; None ; -11.862 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
-; N/A ; None ; -11.875 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
-; N/A ; None ; -11.925 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
-; N/A ; None ; -11.975 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
-; N/A ; None ; -11.981 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
-; N/A ; None ; -12.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
-; N/A ; None ; -12.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
-; N/A ; None ; -12.097 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
-; N/A ; None ; -12.102 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
-; N/A ; None ; -12.106 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
-; N/A ; None ; -12.184 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
-; N/A ; None ; -12.203 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
-; N/A ; None ; -12.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
-; N/A ; None ; -12.332 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
-; N/A ; None ; -12.490 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
-; N/A ; None ; -12.717 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
-; N/A ; None ; -12.797 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
-; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
-; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
-; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
-; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
-; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
-; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
-; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
-; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
-; N/A ; None ; -12.922 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
-; N/A ; None ; -12.922 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
-; N/A ; None ; -12.945 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
-; N/A ; None ; -13.074 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
-; N/A ; None ; -13.074 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
-; N/A ; None ; -13.213 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
-; N/A ; None ; -13.323 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
-; N/A ; None ; -13.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
-; N/A ; None ; -13.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
-; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
-; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
-; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
-; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
-; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
-; N/A ; None ; -13.690 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
-; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
-; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
-; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
-; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
-; N/A ; None ; -13.905 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
-; N/A ; None ; -13.905 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
-; N/A ; None ; -14.196 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
-; N/A ; None ; -14.329 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
-; N/A ; None ; -14.342 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
-; N/A ; None ; -14.363 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
-; N/A ; None ; -14.621 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
-; N/A ; None ; -14.621 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
-; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
-; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
-; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
-; N/A ; None ; -15.078 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
-; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
-; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
-; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
-; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
-; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
+; N/A ; None ; -8.849 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
+; N/A ; None ; -9.173 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
+; N/A ; None ; -9.243 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
+; N/A ; None ; -9.244 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
+; N/A ; None ; -9.730 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
+; N/A ; None ; -9.734 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
+; N/A ; None ; -10.596 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
+; N/A ; None ; -10.732 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
+; N/A ; None ; -10.757 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
+; N/A ; None ; -10.767 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
+; N/A ; None ; -10.772 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
+; N/A ; None ; -11.019 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
+; N/A ; None ; -11.020 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ; sys_clk ;
+; N/A ; None ; -11.021 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
+; N/A ; None ; -11.021 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
+; N/A ; None ; -11.040 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
+; N/A ; None ; -11.106 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
+; N/A ; None ; -11.117 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
+; N/A ; None ; -11.182 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
+; N/A ; None ; -11.272 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
+; N/A ; None ; -11.272 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
+; N/A ; None ; -11.323 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
+; N/A ; None ; -11.327 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
+; N/A ; None ; -11.596 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
+; N/A ; None ; -11.873 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
+; N/A ; None ; -11.923 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
+; N/A ; None ; -12.056 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
+; N/A ; None ; -12.061 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
+; N/A ; None ; -12.061 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
+; N/A ; None ; -12.087 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
+; N/A ; None ; -12.088 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
+; N/A ; None ; -12.100 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
+; N/A ; None ; -12.132 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
+; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
+; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
+; N/A ; None ; -12.344 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
+; N/A ; None ; -12.366 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
+; N/A ; None ; -12.393 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
+; N/A ; None ; -12.498 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
+; N/A ; None ; -12.628 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
+; N/A ; None ; -12.635 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
+; N/A ; None ; -12.690 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
+; N/A ; None ; -12.710 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
+; N/A ; None ; -12.730 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
+; N/A ; None ; -12.774 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
+; N/A ; None ; -12.801 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
+; N/A ; None ; -12.879 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
+; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
+; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
+; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
+; N/A ; None ; -12.919 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
+; N/A ; None ; -12.963 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
+; N/A ; None ; -13.057 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
+; N/A ; None ; -13.069 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
+; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
+; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
+; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
+; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
+; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
+; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
+; N/A ; None ; -13.075 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
+; N/A ; None ; -13.114 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
+; N/A ; None ; -13.187 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
+; N/A ; None ; -13.267 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
+; N/A ; None ; -13.267 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
+; N/A ; None ; -13.306 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
+; N/A ; None ; -13.342 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
+; N/A ; None ; -13.358 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
+; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
+; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
+; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
+; N/A ; None ; -13.390 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
+; N/A ; None ; -13.428 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
+; N/A ; None ; -13.463 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
+; N/A ; None ; -13.463 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
+; N/A ; None ; -13.609 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
+; N/A ; None ; -13.659 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
+; N/A ; None ; -13.659 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
+; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
+; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
+; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
+; N/A ; None ; -13.709 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
+; N/A ; None ; -13.731 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
+; N/A ; None ; -13.731 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
+; N/A ; None ; -13.795 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
+; N/A ; None ; -13.820 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
+; N/A ; None ; -13.894 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
+; N/A ; None ; -14.441 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
+; N/A ; None ; -14.464 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
+; N/A ; None ; -14.469 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
+; N/A ; None ; -14.470 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
+; N/A ; None ; -14.470 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
+; N/A ; None ; -14.530 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
+; N/A ; None ; -15.539 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
+---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 10:10:41 2010
+ Info: Processing started: Fri Dec 17 12:27:18 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "sys_clk" is an undefined clock
-Info: Clock "sys_clk" has Internal fmax of 46.92 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]" (period= 21.311 ns)
- Info: + Longest memory to register delay is 20.617 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a1'
- Info: 3: + IC(1.103 ns) + CELL(0.114 ns) = 5.534 ns; Loc. = LC_X31_Y18_N3; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[1]~3'
- Info: 4: + IC(0.437 ns) + CELL(0.114 ns) = 6.085 ns; Loc. = LC_X31_Y18_N2; Fanout = 5; COMB Node = 'execute_stage:exec_st|left_operand[1]~4'
- Info: 5: + IC(1.249 ns) + CELL(0.114 ns) = 7.448 ns; Loc. = LC_X31_Y22_N0; Fanout = 9; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector106~0'
- Info: 6: + IC(0.410 ns) + CELL(0.432 ns) = 8.290 ns; Loc. = LC_X31_Y22_N5; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~152COUT1_192'
- Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 8.370 ns; Loc. = LC_X31_Y22_N6; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~147COUT1_194'
- Info: 8: + IC(0.000 ns) + CELL(0.608 ns) = 8.978 ns; Loc. = LC_X31_Y22_N7; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~0'
- Info: 9: + IC(0.728 ns) + CELL(0.575 ns) = 10.281 ns; Loc. = LC_X30_Y22_N7; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[3]~2COUT1_191'
- Info: 10: + IC(0.000 ns) + CELL(0.608 ns) = 10.889 ns; Loc. = LC_X30_Y22_N8; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[4]~10'
- Info: 11: + IC(1.603 ns) + CELL(0.114 ns) = 12.606 ns; Loc. = LC_X32_Y21_N2; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector70~0'
- Info: 12: + IC(1.282 ns) + CELL(0.292 ns) = 14.180 ns; Loc. = LC_X31_Y17_N0; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector70~1'
- Info: 13: + IC(0.418 ns) + CELL(0.114 ns) = 14.712 ns; Loc. = LC_X31_Y17_N5; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~0'
- Info: 14: + IC(0.727 ns) + CELL(0.292 ns) = 15.731 ns; Loc. = LC_X30_Y17_N6; Fanout = 7; COMB Node = 'writeback_stage:writeback_st|Equal0~5'
- Info: 15: + IC(1.590 ns) + CELL(0.292 ns) = 17.613 ns; Loc. = LC_X27_Y19_N2; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
- Info: 16: + IC(0.182 ns) + CELL(0.114 ns) = 17.909 ns; Loc. = LC_X27_Y19_N3; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~12'
- Info: 17: + IC(0.431 ns) + CELL(0.114 ns) = 18.454 ns; Loc. = LC_X27_Y19_N6; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
- Info: 18: + IC(1.296 ns) + CELL(0.867 ns) = 20.617 ns; Loc. = LC_X28_Y21_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
- Info: Total cell delay = 9.161 ns ( 44.43 % )
- Info: Total interconnect delay = 11.456 ns ( 55.57 % )
+Info: Clock "sys_clk" has Internal fmax of 46.34 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]" (period= 21.578 ns)
+ Info: + Longest memory to register delay is 20.884 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y14; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
+ Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y14; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a7'
+ Info: 3: + IC(1.221 ns) + CELL(0.114 ns) = 5.652 ns; Loc. = LC_X35_Y16_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|right_operand[7]~17'
+ Info: 4: + IC(1.274 ns) + CELL(0.114 ns) = 7.040 ns; Loc. = LC_X36_Y15_N7; Fanout = 4; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~COMBOUT'
+ Info: 5: + IC(1.641 ns) + CELL(0.423 ns) = 9.104 ns; Loc. = LC_X32_Y16_N1; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~29'
+ Info: 6: + IC(0.000 ns) + CELL(0.078 ns) = 9.182 ns; Loc. = LC_X32_Y16_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~19'
+ Info: 7: + IC(0.000 ns) + CELL(0.078 ns) = 9.260 ns; Loc. = LC_X32_Y16_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~34'
+ Info: 8: + IC(0.000 ns) + CELL(0.178 ns) = 9.438 ns; Loc. = LC_X32_Y16_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~54'
+ Info: 9: + IC(0.000 ns) + CELL(0.208 ns) = 9.646 ns; Loc. = LC_X32_Y16_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~89'
+ Info: 10: + IC(0.000 ns) + CELL(0.679 ns) = 10.325 ns; Loc. = LC_X32_Y15_N0; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~102'
+ Info: 11: + IC(1.125 ns) + CELL(0.564 ns) = 12.014 ns; Loc. = LC_X31_Y15_N0; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[16]~102'
+ Info: 12: + IC(0.000 ns) + CELL(0.078 ns) = 12.092 ns; Loc. = LC_X31_Y15_N1; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[17]~107'
+ Info: 13: + IC(0.000 ns) + CELL(0.078 ns) = 12.170 ns; Loc. = LC_X31_Y15_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[18]~112'
+ Info: 14: + IC(0.000 ns) + CELL(0.078 ns) = 12.248 ns; Loc. = LC_X31_Y15_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[19]~92'
+ Info: 15: + IC(0.000 ns) + CELL(0.178 ns) = 12.426 ns; Loc. = LC_X31_Y15_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[20]~117'
+ Info: 16: + IC(0.000 ns) + CELL(0.208 ns) = 12.634 ns; Loc. = LC_X31_Y15_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[25]~142'
+ Info: 17: + IC(0.000 ns) + CELL(0.679 ns) = 13.313 ns; Loc. = LC_X31_Y14_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[28]~65'
+ Info: 18: + IC(1.677 ns) + CELL(0.442 ns) = 15.432 ns; Loc. = LC_X36_Y12_N1; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~0'
+ Info: 19: + IC(1.252 ns) + CELL(0.114 ns) = 16.798 ns; Loc. = LC_X36_Y16_N7; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~1'
+ Info: 20: + IC(1.221 ns) + CELL(0.114 ns) = 18.133 ns; Loc. = LC_X36_Y15_N5; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
+ Info: 21: + IC(0.418 ns) + CELL(0.114 ns) = 18.665 ns; Loc. = LC_X36_Y15_N0; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
+ Info: 22: + IC(0.182 ns) + CELL(0.114 ns) = 18.961 ns; Loc. = LC_X36_Y15_N1; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
+ Info: 23: + IC(0.182 ns) + CELL(0.114 ns) = 19.257 ns; Loc. = LC_X36_Y15_N2; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
+ Info: 24: + IC(0.760 ns) + CELL(0.867 ns) = 20.884 ns; Loc. = LC_X37_Y15_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
+ Info: Total cell delay = 9.931 ns ( 47.55 % )
+ Info: Total interconnect delay = 10.953 ns ( 52.45 % )
Info: - Smallest clock skew is -0.007 ns
- Info: + Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
+ Info: + Shortest clock path from clock "sys_clk" to destination register is 3.178 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X28_Y21_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
- Info: Total cell delay = 2.180 ns ( 68.40 % )
- Info: Total interconnect delay = 1.007 ns ( 31.60 % )
- Info: - Longest clock path from clock "sys_clk" to source memory is 3.194 ns
+ Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X37_Y15_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
+ Info: Total cell delay = 2.180 ns ( 68.60 % )
+ Info: Total interconnect delay = 0.998 ns ( 31.40 % )
+ Info: - Longest clock path from clock "sys_clk" to source memory is 3.185 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.718 ns) = 3.194 ns; Loc. = M4K_X33_Y18; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0'
- Info: Total cell delay = 2.187 ns ( 68.47 % )
- Info: Total interconnect delay = 1.007 ns ( 31.53 % )
+ Info: 2: + IC(0.998 ns) + CELL(0.718 ns) = 3.185 ns; Loc. = M4K_X33_Y14; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
+ Info: Total cell delay = 2.187 ns ( 68.67 % )
+ Info: Total interconnect delay = 0.998 ns ( 31.33 % )
Info: + Micro clock to output delay of source is 0.650 ns
Info: + Micro setup delay of destination is 0.037 ns
-Info: tsu for register "execute_stage:exec_st|reg.result[2]" (data pin = "sys_res", clock pin = "sys_clk") is 16.692 ns
- Info: + Longest pin to register delay is 19.842 ns
+Info: tsu for register "fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]" (data pin = "sys_res", clock pin = "sys_clk") is 18.965 ns
+ Info: + Longest pin to register delay is 22.115 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
- Info: 2: + IC(9.460 ns) + CELL(0.292 ns) = 11.221 ns; Loc. = LC_X37_Y17_N4; Fanout = 7; COMB Node = 'execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0'
- Info: 3: + IC(0.771 ns) + CELL(0.114 ns) = 12.106 ns; Loc. = LC_X36_Y17_N6; Fanout = 32; COMB Node = 'execute_stage:exec_st|alu:alu_inst|calc~0'
- Info: 4: + IC(2.560 ns) + CELL(0.114 ns) = 14.780 ns; Loc. = LC_X27_Y16_N7; Fanout = 3; COMB Node = 'execute_stage:exec_st|reg.result[1]~19'
- Info: 5: + IC(2.407 ns) + CELL(0.442 ns) = 17.629 ns; Loc. = LC_X27_Y22_N4; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|alu_result.result[2]~8'
- Info: 6: + IC(1.606 ns) + CELL(0.607 ns) = 19.842 ns; Loc. = LC_X32_Y22_N2; Fanout = 2; REG Node = 'execute_stage:exec_st|reg.result[2]'
- Info: Total cell delay = 3.038 ns ( 15.31 % )
- Info: Total interconnect delay = 16.804 ns ( 84.69 % )
+ Info: 2: + IC(9.029 ns) + CELL(0.114 ns) = 10.612 ns; Loc. = LC_X38_Y14_N6; Fanout = 10; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[6]~3'
+ Info: 3: + IC(0.479 ns) + CELL(0.114 ns) = 11.205 ns; Loc. = LC_X38_Y14_N3; Fanout = 8; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[0]~20'
+ Info: 4: + IC(3.612 ns) + CELL(0.442 ns) = 15.259 ns; Loc. = LC_X29_Y17_N2; Fanout = 2; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[2]~11'
+ Info: 5: + IC(1.961 ns) + CELL(0.442 ns) = 17.662 ns; Loc. = LC_X35_Y16_N6; Fanout = 1; COMB Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|Equal0~1'
+ Info: 6: + IC(1.703 ns) + CELL(0.292 ns) = 19.657 ns; Loc. = LC_X38_Y14_N4; Fanout = 6; COMB Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|Equal0~2'
+ Info: 7: + IC(2.149 ns) + CELL(0.309 ns) = 22.115 ns; Loc. = LC_X35_Y19_N2; Fanout = 25; REG Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]'
+ Info: Total cell delay = 3.182 ns ( 14.39 % )
+ Info: Total interconnect delay = 18.933 ns ( 85.61 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X32_Y22_N2; Fanout = 2; REG Node = 'execute_stage:exec_st|reg.result[2]'
+ Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X35_Y19_N2; Fanout = 25; REG Node = 'fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25]'
Info: Total cell delay = 2.180 ns ( 68.40 % )
Info: Total interconnect delay = 1.007 ns ( 31.60 % )
-Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 8.362 ns
- Info: + Longest clock path from clock "sys_clk" to source register is 3.187 ns
+Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 10.165 ns
+ Info: + Longest clock path from clock "sys_clk" to source register is 3.111 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X40_Y20_N8; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
- Info: Total cell delay = 2.180 ns ( 68.40 % )
- Info: Total interconnect delay = 1.007 ns ( 31.60 % )
+ Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X32_Y9_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
+ Info: Total cell delay = 2.180 ns ( 70.07 % )
+ Info: Total interconnect delay = 0.931 ns ( 29.93 % )
Info: + Micro clock to output delay of source is 0.224 ns
- Info: + Longest register to pin delay is 4.951 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y20_N8; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
- Info: 2: + IC(2.827 ns) + CELL(2.124 ns) = 4.951 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
- Info: Total cell delay = 2.124 ns ( 42.90 % )
- Info: Total interconnect delay = 2.827 ns ( 57.10 % )
-Info: th for register "writeback_stage:writeback_st|extension_uart:uart|new_tx_data" (data pin = "sys_res", clock pin = "sys_clk") is -8.416 ns
- Info: + Longest clock path from clock "sys_clk" to destination register is 3.187 ns
+ Info: + Longest register to pin delay is 6.830 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y9_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
+ Info: 2: + IC(4.706 ns) + CELL(2.124 ns) = 6.830 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
+ Info: Total cell delay = 2.124 ns ( 31.10 % )
+ Info: Total interconnect delay = 4.706 ns ( 68.90 % )
+Info: th for register "fetch_stage:fetch_st|instr_r_addr[4]" (data pin = "sys_res", clock pin = "sys_clk") is -8.849 ns
+ Info: + Longest clock path from clock "sys_clk" to destination register is 3.178 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X27_Y19_N6; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|new_tx_data'
- Info: Total cell delay = 2.180 ns ( 68.40 % )
- Info: Total interconnect delay = 1.007 ns ( 31.60 % )
+ Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X39_Y14_N4; Fanout = 3; REG Node = 'fetch_stage:fetch_st|instr_r_addr[4]'
+ Info: Total cell delay = 2.180 ns ( 68.60 % )
+ Info: Total interconnect delay = 0.998 ns ( 31.40 % )
Info: + Micro hold delay of destination is 0.015 ns
- Info: - Shortest pin to register delay is 11.618 ns
+ Info: - Shortest pin to register delay is 12.042 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
- Info: 2: + IC(9.282 ns) + CELL(0.867 ns) = 11.618 ns; Loc. = LC_X27_Y19_N6; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|new_tx_data'
- Info: Total cell delay = 2.336 ns ( 20.11 % )
- Info: Total interconnect delay = 9.282 ns ( 79.89 % )
+ Info: 2: + IC(9.029 ns) + CELL(0.114 ns) = 10.612 ns; Loc. = LC_X38_Y14_N6; Fanout = 10; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[6]~3'
+ Info: 3: + IC(0.482 ns) + CELL(0.114 ns) = 11.208 ns; Loc. = LC_X38_Y14_N0; Fanout = 2; COMB Node = 'fetch_stage:fetch_st|instr_r_addr_nxt[4]~14'
+ Info: 4: + IC(0.719 ns) + CELL(0.115 ns) = 12.042 ns; Loc. = LC_X39_Y14_N4; Fanout = 3; REG Node = 'fetch_stage:fetch_st|instr_r_addr[4]'
+ Info: Total cell delay = 1.812 ns ( 15.05 % )
+ Info: Total interconnect delay = 10.230 ns ( 84.95 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 189 megabytes
- Info: Processing ended: Fri Dec 17 10:10:42 2010
+ Info: Processing ended: Fri Dec 17 12:27:19 2010
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Type : Worst-case tsu
Slack : N/A
Required Time : None
-Actual Time : 16.692 ns
+Actual Time : 18.965 ns
From : sys_res
-To : execute_stage:exec_st|reg.result[2]
+To : fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27]
From Clock : --
To Clock : sys_clk
Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
-Actual Time : 8.362 ns
+Actual Time : 10.165 ns
From : writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int
To : bus_tx
From Clock : sys_clk
Type : Worst-case th
Slack : N/A
Required Time : None
-Actual Time : -8.416 ns
+Actual Time : -8.849 ns
From : sys_res
-To : writeback_stage:writeback_st|extension_uart:uart|new_tx_data
+To : fetch_stage:fetch_st|instr_r_addr[4]
From Clock : --
To Clock : sys_clk
Failed Paths : 0
Type : Clock Setup: 'sys_clk'
Slack : N/A
Required Time : None
-Actual Time : 46.92 MHz ( period = 21.311 ns )
-From : decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2
+Actual Time : 46.34 MHz ( period = 21.578 ns )
+From : decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2
To : writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4]
From Clock : sys_clk
To Clock : sys_clk
projects / calu.git / commitdiff