call/return

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index 41ea3647871a9ba41da317a8c02257a0034544c6..c77feb02ae23ce5ba6890fdcfc37aec093d2a390 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -68,4 +68,8 @@ add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_we
 
 add wave  -radix hexadecimal /pipeline_tb/exec_st/gpmp_inst/psw
 
+add wave  -radix hexadecimal /pipeline_tb/addr_pin
+add wave  -radix hexadecimal /pipeline_tb/data_pin
+add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
+
 run 5000 ns

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 0dbf3d4e5466aa7b897727e91215db82995711f3..14cc3bede1dc39a6da050615e729b77c522ba235 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -12,7 +12,7 @@ architecture behaviour of r_w_ram is
        
                                                                        -- r0 = 0, r1 = 1, r2 = 3, r3 = A
 
-       signal ram : RAM_TYPE := (  0 => "11101011000000000000000000010111", -- call +1
+       signal ram : RAM_TYPE := (  0 => "11101011000000000000000010000101", -- call +1
 
                                    1 => "11101101000010000000000000111000", -- r1 = 7
                                    2 => "11101101000100000000000000101000", -- r2 = 5