vcom -work work ../src/r2_w_ram_b.vhd
vcom -work work ../src/common_pkg.vhd
vcom -work work ../src/extension_pkg.vhd
+vcom -work work ../src/extension_uart_pkg.vhd
vcom -work work ../src/core_pkg.vhd
vcom -work work ../src/decoder.vhd
vcom -work work ../src/decoder_b.vhd
port(
--System input pins
+ sys_res : in std_logic;
sys_clk : in std_logic;
-- result : out gp_register_t;
-- reg_wr_data : out gp_register_t
architecture behav of core_top is
signal jump_result : instruction_addr_t;
- signal sys_res : std_logic;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal branch_prediction_bit_pin : std_logic;
nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
jump_result <= prog_cnt_pin; --jump_result_pin;
- sys_res <= '1';
+-- sys_res <= '1';
-- reg_wr_data <= reg_wr_data_pin;
end behav;
-- r0 = 0, r1 = 1, r2 = 3, r3 = A
signal ram : RAM_TYPE := (
+-- 0 => x"ed2802d0", -- ldi r5, 0x5a;;
+-- 1 => x"ed008058", -- ldi r0, 0x100b;;
+-- 2 => x"e7a80000", -- stw r5, 0(r0);;
+-- 3 => "11101011000000000000000000000010",
+
--8 => "11100111100010000000000000000000", --stw
-- 0 => "11101101000000000000000000000000", --ldi
-- 1 => "11101101001000000000000000000000", --ldi
process(clk)
begin
if rising_edge(clk) then
- -- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ --data_out <= ram(to_integer(UNSIGNED(rd_addr)));
case rd_addr is
when "00000000000" => data_out <= x"ed2802d0"; -- ldi r5, 0x5a;;
- when "00000000100" => data_out <= x"ed008058"; -- ldi r0, 0x100b;;
- when "00000001000" => data_out <= x"e7a80000"; -- stw r5, 0(r0);;
- when others => data_out <= x"07a80000";
+ when "00000000001" => data_out <= x"ed008058"; -- ldi r0, 0x100b;;
+ when "00000000010" => data_out <= x"e7a80000"; -- stw r5, 0(r0);;
+ when others => data_out <= "11101011000000000000000000000010";
end case;
if wr_en = '1' then
Assembler report for dt
-Thu Dec 16 16:55:03 2010
+Fri Dec 17 10:10:39 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Thu Dec 16 16:55:03 2010 ;
+; Assembler Status ; Successful - Fri Dec 17 10:10:39 2010 ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
+----------------+-----------------+
; Device ; EP1C12Q240C8 ;
; JTAG usercode ; 0xFFFFFFFF ;
-; Checksum ; 0x00162065 ;
+; Checksum ; 0x001F1EC3 ;
+----------------+-----------------+
+--------------------+-------------+
; Device ; EPCS4 ;
; JTAG usercode ; 0x00000000 ;
-; Checksum ; 0x03AC7869 ;
+; Checksum ; 0x03ACAE9A ;
; Compression Ratio ; 1 ;
+--------------------+-------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Thu Dec 16 16:55:00 2010
+ Info: Processing started: Fri Dec 17 10:10:37 2010
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dt -c dt
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 229 megabytes
- Info: Processing ended: Thu Dec 16 16:55:03 2010
- Info: Elapsed time: 00:00:03
+ Info: Peak virtual memory: 230 megabytes
+ Info: Processing ended: Fri Dec 17 10:10:39 2010
+ Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
-Thu Dec 16 16:55:06 2010
+Fri Dec 17 10:10:43 2010
Fitter report for dt
-Thu Dec 16 16:54:58 2010
+Fri Dec 17 10:10:33 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
-; Fitter Status ; Successful - Thu Dec 16 16:54:57 2010 ;
+; Fitter Status ; Successful - Fri Dec 17 10:10:33 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
-; Total logic elements ; 398 / 12,060 ( 3 % ) ;
-; Total pins ; 2 / 173 ( 1 % ) ;
+; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
+; Total pins ; 3 / 173 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
; Type ; Value ;
+---------------------+------------------------+
; Placement (by node) ; ;
-; -- Requested ; 0 / 466 ( 0.00 % ) ;
-; -- Achieved ; 0 / 466 ( 0.00 % ) ;
+; -- Requested ; 0 / 1125 ( 0.00 % ) ;
+; -- Achieved ; 0 / 1125 ( 0.00 % ) ;
; ; ;
; Routing (by net) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
-; Top ; 464 ; 0 ; N/A ; Source File ;
+; Top ; 1123 ; 0 ; N/A ; Source File ;
; hard_block:auto_generated_inst ; 2 ; 0 ; N/A ; Source File ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in /homes/burban/calu/dt/dt.pin.
-
-
-+-------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+---------------------------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+---------------------------------------------+
-; Total logic elements ; 398 / 12,060 ( 3 % ) ;
-; -- Combinational with no register ; 257 ;
-; -- Register only ; 12 ;
-; -- Combinational with a register ; 129 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 105 ;
-; -- 3 input functions ; 195 ;
-; -- 2 input functions ; 80 ;
-; -- 1 input functions ; 4 ;
-; -- 0 input functions ; 2 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 298 ;
-; -- arithmetic mode ; 100 ;
-; -- qfbk mode ; 35 ;
-; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 44 ;
-; -- asynchronous clear/load mode ; 0 ;
-; ; ;
-; Total registers ; 141 / 12,567 ( 1 % ) ;
-; Total LABs ; 48 / 1,206 ( 4 % ) ;
-; Logic elements in carry chains ; 104 ;
-; User inserted logic elements ; 0 ;
-; Virtual pins ; 0 ;
-; I/O pins ; 2 / 173 ( 1 % ) ;
-; -- Clock pins ; 1 / 2 ( 50 % ) ;
-; Global signals ; 1 ;
-; M4Ks ; 2 / 52 ( 4 % ) ;
-; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
-; Total RAM block bits ; 9,216 / 239,616 ( 4 % ) ;
-; PLLs ; 0 / 2 ( 0 % ) ;
-; Global clocks ; 1 / 8 ( 13 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; ASMI Blocks ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 1% / 1% / 1% ;
-; Peak interconnect usage (total/H/V) ; 4% / 5% / 4% ;
-; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 143 ;
-; Highest non-global fan-out signal ; decode_stage:decode_st|rtw_rec.immediate[3] ;
-; Highest non-global fan-out ; 66 ;
-; Total fan-out ; 1487 ;
-; Average fan-out ; 3.68 ;
-+---------------------------------------------+---------------------------------------------+
+The pin-out file can be found in /homes/c0726283/calu/dt/dt.pin.
+
+
++-----------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+-------------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-------------------------------------------------+
+; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
+; -- Combinational with no register ; 841 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 215 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 467 ;
+; -- 3 input functions ; 447 ;
+; -- 2 input functions ; 123 ;
+; -- 1 input functions ; 18 ;
+; -- 0 input functions ; 1 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 850 ;
+; -- arithmetic mode ; 206 ;
+; -- qfbk mode ; 77 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 84 ;
+; -- asynchronous clear/load mode ; 202 ;
+; ; ;
+; Total registers ; 215 / 12,567 ( 2 % ) ;
+; Total LABs ; 114 / 1,206 ( 9 % ) ;
+; Logic elements in carry chains ; 214 ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 3 / 173 ( 2 % ) ;
+; -- Clock pins ; 1 / 2 ( 50 % ) ;
+; Global signals ; 2 ;
+; M4Ks ; 2 / 52 ( 4 % ) ;
+; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+; Total RAM block bits ; 9,216 / 239,616 ( 4 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI Blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 5% / 5% / 5% ;
+; Peak interconnect usage (total/H/V) ; 31% / 32% / 30% ;
+; Maximum fan-out node ; sys_clk ;
+; Maximum fan-out ; 217 ;
+; Highest non-global fan-out signal ; execute_stage:exec_st|alu:alu_inst|Selector76~0 ;
+; Highest non-global fan-out ; 115 ;
+; Total fan-out ; 4170 ;
+; Average fan-out ; 3.92 ;
++---------------------------------------------+-------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
+---------------------------------------------+--------------------+--------------------------------+
; Difficulty Clustering Region ; Low ; Low ;
; ; ; ;
-; Total logic elements ; 398 ; 0 ;
-; -- Combinational with no register ; 257 ; 0 ;
-; -- Register only ; 12 ; 0 ;
-; -- Combinational with a register ; 129 ; 0 ;
+; Total logic elements ; 1056 ; 0 ;
+; -- Combinational with no register ; 841 ; 0 ;
+; -- Register only ; 0 ; 0 ;
+; -- Combinational with a register ; 215 ; 0 ;
; ; ; ;
; Logic element usage by number of LUT inputs ; ; ;
; -- 4 input functions ; 0 ; 0 ;
; -- synchronous clear/load mode ; 0 ; 0 ;
; -- asynchronous clear/load mode ; 0 ; 0 ;
; ; ; ;
-; Total registers ; 141 / 6030 ( 2 % ) ; 0 / 6030 ( 0 % ) ;
+; Total registers ; 215 / 6030 ( 3 % ) ; 0 / 6030 ( 0 % ) ;
; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 2 ; 0 ;
+; I/O pins ; 3 ; 0 ;
; DSP block 9-bit elements ; 0 ; 0 ;
; Total memory bits ; 512 ; 0 ;
; Total RAM block bits ; 9216 ; 0 ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
-; -- Total Connections ; 1572 ; 0 ;
-; -- Registered Connections ; 590 ; 0 ;
+; -- Total Connections ; 4343 ; 0 ;
+; -- Registered Connections ; 813 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 0 ; 0 ;
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
; ; ; ;
; Partition Interface ; ; ;
-; -- Input Ports ; 1 ; 0 ;
+; -- Input Ports ; 2 ; 0 ;
; -- Output Ports ; 1 ; 0 ;
; -- Bidir Ports ; 0 ; 0 ;
; ; ; ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 143 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 217 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+; sys_res ; 42 ; 1 ; 0 ; 6 ; 0 ; 205 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
-; 1 ; 2 / 44 ( 5 % ) ; 3.3V ; -- ;
+; 1 ; 3 / 44 ( 7 % ) ; 3.3V ; -- ;
; 2 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
; 3 ; 2 / 45 ( 4 % ) ; 3.3V ; -- ;
; 4 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
; 39 ; 41 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 40 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 41 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 42 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 42 ; 53 ; 1 ; sys_res ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 43 ; 54 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 44 ; 55 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 45 ; 56 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 398 (1) ; 141 ; 512 ; 2 ; 2 ; 0 ; 257 (1) ; 12 (0) ; 129 (0) ; 104 (0) ; 35 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 43 (42) ; 42 ; 512 ; 2 ; 0 ; 0 ; 1 (0) ; 1 (1) ; 41 (41) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |core_top ; 1056 (1) ; 215 ; 512 ; 2 ; 3 ; 0 ; 841 (1) ; 0 (0) ; 215 (0) ; 214 (0) ; 77 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 103 (96) ; 72 ; 512 ; 2 ; 0 ; 0 ; 31 (24) ; 0 (0) ; 72 (72) ; 11 (11) ; 5 (5) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 191 (129) ; 34 ; 0 ; 0 ; 0 ; 0 ; 157 (95) ; 0 (0) ; 34 (34) ; 61 (0) ; 35 (35) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 62 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (30) ; 0 (0) ; 0 (0) ; 61 (29) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |fetch_stage:fetch_st| ; 28 (22) ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 (11) ; 11 (11) ; 3 (0) ; 11 (11) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |r_w_ram:instruction_ram| ; 6 (6) ; 3 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 135 (28) ; 51 ; 0 ; 0 ; 0 ; 0 ; 84 (26) ; 0 (0) ; 51 (2) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_uart:uart| ; 107 (13) ; 49 ; 0 ; 0 ; 0 ; 0 ; 58 (3) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |execute_stage:exec_st| ; 755 (145) ; 67 ; 0 ; 0 ; 0 ; 0 ; 688 (109) ; 0 (0) ; 67 (36) ; 171 (0) ; 71 (40) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 545 (224) ; 0 ; 0 ; 0 ; 0 ; 0 ; 545 (224) ; 0 (0) ; 0 (0) ; 141 (43) ; 31 (31) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |exec_op:or_inst| ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
+; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
+; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 31 (31) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
+; |fetch_stage:fetch_st| ; 33 (24) ; 17 ; 0 ; 0 ; 0 ; 0 ; 16 (13) ; 0 (0) ; 17 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 164 (52) ; 59 ; 0 ; 0 ; 0 ; 0 ; 105 (48) ; 0 (0) ; 59 (4) ; 32 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_uart:uart| ; 106 (12) ; 49 ; 0 ; 0 ; 0 ; 0 ; 57 (2) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
+; |r_w_ram:data_ram| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------+----------+---------------+---------------+-----------------------+-----+
; bus_tx ; Output ; -- ; -- ; -- ; -- ;
; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
+; sys_res ; Input ; OFF ; ON ; -- ; -- ;
+---------+----------+---------------+---------------+-----------------------+-----+
-+---------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------+-------------------+---------+
-; sys_clk ; ; ;
-+---------------------+-------------------+---------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
-; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; LC_X30_Y13_N4 ; 56 ; Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|reg.wr_en ; LC_X31_Y16_N0 ; 7 ; Write enable ; no ; -- ; -- ;
-; sys_clk ; PIN_152 ; 143 ; Clock ; yes ; Global Clock ; GCLK7 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X39_Y14_N4 ; 5 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X39_Y14_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1 ; LC_X28_Y11_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
-+--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
++---------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------------------------------------------------------------------------------+-------------------+---------+
+; sys_clk ; ; ;
+; sys_res ; ; ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0 ; 1 ; ON ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr_nxt[3]~3 ; 1 ; ON ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 1 ; ON ;
+; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
++---------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X27_Y17_N9 ; 58 ; Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X36_Y17_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X29_Y15_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
+; execute_stage:exec_st|reg.result[1]~9 ; LC_X27_Y16_N4 ; 12 ; Sync. load ; no ; -- ; -- ;
+; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load, Clock enable ; yes ; Global Clock ; GCLK3 ;
+; writeback_stage:writeback_st|Mux9~0 ; LC_X26_Y19_N7 ; 7 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X40_Y20_N6 ; 5 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X40_Y19_N5 ; 35 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X27_Y19_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|reg_we~0 ; LC_X31_Y18_N0 ; 8 ; Write enable ; no ; -- ; -- ;
++--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+------------------------------------------------------------------------+
+---------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+---------+----------+---------+----------------------+------------------+
-; sys_clk ; PIN_152 ; 143 ; Global Clock ; GCLK7 ;
+; sys_clk ; PIN_152 ; 217 ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 205 ; Global Clock ; GCLK3 ;
+---------+----------+---------+----------------------+------------------+
+-----------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+-----------------------------------------------------------------------------------+---------+
-; decode_stage:decode_st|rtw_rec.immediate[3] ; 66 ;
-; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 56 ;
+; execute_stage:exec_st|alu:alu_inst|Selector76~0 ; 115 ;
+; execute_stage:exec_st|right_operand[0]~10 ; 89 ;
+; execute_stage:exec_st|right_operand[1]~6 ; 77 ;
+; execute_stage:exec_st|right_operand[2]~4 ; 63 ;
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 58 ;
+; execute_stage:exec_st|alu:alu_inst|Selector53~0 ; 53 ;
+; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 49 ;
+; execute_stage:exec_st|right_operand[3]~8 ; 48 ;
+; decode_stage:decode_st|dec_op_inst.op_detail[2] ; 41 ;
+; execute_stage:exec_st|left_operand[13]~1 ; 40 ;
+; execute_stage:exec_st|right_operand[14]~1 ; 38 ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; 37 ;
+; execute_stage:exec_st|right_operand[14]~2 ; 37 ;
+; writeback_stage:writeback_st|wb_reg.dmem_en ; 35 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 35 ;
+; writeback_stage:writeback_st|wb_reg.dmem_write_en ; 34 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|Equal0~10 ; 34 ;
-; execute_stage:exec_st|left_operand[28]~1 ; 32 ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; 32 ;
; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
-; execute_stage:exec_st|right_operand[6]~1 ; 30 ;
-; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 29 ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
+; execute_stage:exec_st|reg.result[11]~12 ; 29 ;
+; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
+; writeback_stage:writeback_st|jump ; 25 ;
+; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 25 ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; 24 ;
+; execute_stage:exec_st|reg.result[11]~13 ; 23 ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 23 ;
+; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 21 ;
+; decode_stage:decode_st|decoder:decoder_inst|instr_s~5 ; 15 ;
+; decode_stage:decode_st|rtw_rec.imm_set ; 15 ;
+; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 13 ;
+; execute_stage:exec_st|reg.result[1]~9 ; 12 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 12 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 10 ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1 ; 8 ;
-; execute_stage:exec_st|reg.res_addr[2] ; 8 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; 7 ;
-; execute_stage:exec_st|right_operand[6]~5 ; 7 ;
-; execute_stage:exec_st|reg.wr_en ; 7 ;
-; writeback_stage:writeback_st|wb_reg.address[0] ; 7 ;
-; writeback_stage:writeback_st|wb_reg.address[1] ; 7 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 6 ;
-; execute_stage:exec_st|right_operand[6]~6 ; 6 ;
-; execute_stage:exec_st|reg.result[3] ; 6 ;
-; execute_stage:exec_st|reg.result[1] ; 6 ;
-; writeback_stage:writeback_st|Equal0~24 ; 6 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 6 ;
-; ~GND ; 5 ;
-; execute_stage:exec_st|reg.result[27] ; 5 ;
-; execute_stage:exec_st|reg.result[26] ; 5 ;
-; execute_stage:exec_st|reg.result[25] ; 5 ;
-; execute_stage:exec_st|reg.result[24] ; 5 ;
-; execute_stage:exec_st|reg.result[23] ; 5 ;
-; execute_stage:exec_st|reg.result[22] ; 5 ;
-; execute_stage:exec_st|reg.result[21] ; 5 ;
-; execute_stage:exec_st|reg.result[20] ; 5 ;
-; execute_stage:exec_st|reg.result[19] ; 5 ;
-; execute_stage:exec_st|reg.result[18] ; 5 ;
-; execute_stage:exec_st|reg.result[17] ; 5 ;
-; execute_stage:exec_st|reg.result[16] ; 5 ;
-; execute_stage:exec_st|reg.result[15] ; 5 ;
-; execute_stage:exec_st|reg.result[14] ; 5 ;
-; execute_stage:exec_st|reg.result[13] ; 5 ;
-; execute_stage:exec_st|reg.result[11] ; 5 ;
-; execute_stage:exec_st|reg.result[10] ; 5 ;
-; execute_stage:exec_st|reg.result[9] ; 5 ;
-; execute_stage:exec_st|reg.result[8] ; 5 ;
-; execute_stage:exec_st|reg.result[12] ; 5 ;
-; execute_stage:exec_st|reg.result[31] ; 5 ;
-; execute_stage:exec_st|reg.result[30] ; 5 ;
-; execute_stage:exec_st|reg.result[29] ; 5 ;
-; execute_stage:exec_st|reg.result[28] ; 5 ;
-; execute_stage:exec_st|reg.result[4] ; 5 ;
-; execute_stage:exec_st|reg.result[7] ; 5 ;
+; execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|tmp_sb~0 ; 9 ;
+; execute_stage:exec_st|left_operand[30]~56 ; 9 ;
+; execute_stage:exec_st|left_operand[29]~54 ; 9 ;
+; execute_stage:exec_st|left_operand[28]~52 ; 9 ;
+; execute_stage:exec_st|reg.res_addr[2] ; 9 ;
+; execute_stage:exec_st|reg.result[6]~21 ; 8 ;
+; execute_stage:exec_st|reg.result[25]~14 ; 8 ;
+; execute_stage:exec_st|alu:alu_inst|Selector76~1 ; 8 ;
+; execute_stage:exec_st|left_operand[27]~50 ; 8 ;
+; execute_stage:exec_st|left_operand[26]~48 ; 8 ;
+; execute_stage:exec_st|alu:alu_inst|Selector97~0 ; 8 ;
+; execute_stage:exec_st|left_operand[12]~34 ; 8 ;
+; execute_stage:exec_st|left_operand[11]~32 ; 8 ;
+; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 8 ;
+; execute_stage:exec_st|alu:alu_inst|Selector107~0 ; 8 ;
+; execute_stage:exec_st|right_operand[14]~13 ; 8 ;
+-----------------------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y16 ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y15 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y18 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y19 ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
-+----------------------------------------------------+
-; Interconnect Usage Summary ;
-+----------------------------+-----------------------+
-; Interconnect Resource Type ; Usage ;
-+----------------------------+-----------------------+
-; C4s ; 433 / 30,600 ( 1 % ) ;
-; Direct links ; 43 / 43,552 ( < 1 % ) ;
-; Global clocks ; 1 / 8 ( 13 % ) ;
-; LAB clocks ; 12 / 312 ( 4 % ) ;
-; LUT chains ; 46 / 10,854 ( < 1 % ) ;
-; Local interconnects ; 653 / 43,552 ( 1 % ) ;
-; M4K buffers ; 64 / 1,872 ( 3 % ) ;
-; R4s ; 439 / 28,560 ( 2 % ) ;
-+----------------------------+-----------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+------------------------------+
-; Number of Logic Elements (Average = 8.29) ; Number of LABs (Total = 48) ;
-+--------------------------------------------+------------------------------+
-; 1 ; 7 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 1 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 2 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 37 ;
-+--------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+------------------------------+
-; LAB-wide Signals (Average = 0.92) ; Number of LABs (Total = 48) ;
-+------------------------------------+------------------------------+
-; 1 Clock ; 39 ;
-; 1 Clock enable ; 2 ;
-; 1 Sync. load ; 2 ;
-; 2 Clock enables ; 1 ;
-+------------------------------------+------------------------------+
++-----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+------------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+------------------------+
+; C4s ; 1,397 / 30,600 ( 5 % ) ;
+; Direct links ; 137 / 43,552 ( < 1 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; LAB clocks ; 32 / 312 ( 10 % ) ;
+; LUT chains ; 146 / 10,854 ( 1 % ) ;
+; Local interconnects ; 1,899 / 43,552 ( 4 % ) ;
+; M4K buffers ; 64 / 1,872 ( 3 % ) ;
+; R4s ; 1,532 / 28,560 ( 5 % ) ;
++----------------------------+------------------------+
+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+------------------------------+
-; Number of Signals Sourced (Average = 9.10) ; Number of LABs (Total = 48) ;
-+---------------------------------------------+------------------------------+
-; 0 ; 0 ;
-; 1 ; 7 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 1 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 18 ;
-; 11 ; 4 ;
-; 12 ; 13 ;
-; 13 ; 1 ;
-; 14 ; 0 ;
-; 15 ; 1 ;
-+---------------------------------------------+------------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out (Average = 6.02) ; Number of LABs (Total = 48) ;
-+-------------------------------------------------+------------------------------+
-; 0 ; 0 ;
-; 1 ; 7 ;
-; 2 ; 1 ;
-; 3 ; 3 ;
-; 4 ; 3 ;
-; 5 ; 4 ;
-; 6 ; 14 ;
-; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 3 ;
-; 10 ; 10 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 1 ;
-+-------------------------------------------------+------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+-------------------------------+
+; Number of Logic Elements (Average = 9.26) ; Number of LABs (Total = 114) ;
++--------------------------------------------+-------------------------------+
+; 1 ; 6 ;
+; 2 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 2 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
+; 8 ; 0 ;
+; 9 ; 2 ;
+; 10 ; 101 ;
++--------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals (Average = 1.44) ; Number of LABs (Total = 114) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear ; 69 ;
+; 1 Async. load ; 2 ;
+; 1 Clock ; 72 ;
+; 1 Clock enable ; 13 ;
+; 1 Sync. clear ; 3 ;
+; 1 Sync. load ; 5 ;
++------------------------------------+-------------------------------+
+-----------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+----------------------------------------------+------------------------------+
-; Number of Distinct Inputs (Average = 12.08) ; Number of LABs (Total = 48) ;
-+----------------------------------------------+------------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 7 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 1 ;
-; 10 ; 1 ;
-; 11 ; 4 ;
-; 12 ; 0 ;
-; 13 ; 12 ;
-; 14 ; 2 ;
-; 15 ; 4 ;
-; 16 ; 0 ;
-; 17 ; 3 ;
-; 18 ; 0 ;
-; 19 ; 1 ;
-; 20 ; 3 ;
-; 21 ; 5 ;
-+----------------------------------------------+------------------------------+
+; LAB Signals Sourced ;
++---------------------------------------------+-------------------------------+
+; Number of Signals Sourced (Average = 9.97) ; Number of LABs (Total = 114) ;
++---------------------------------------------+-------------------------------+
+; 0 ; 0 ;
+; 1 ; 6 ;
+; 2 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 2 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+; 9 ; 2 ;
+; 10 ; 60 ;
+; 11 ; 21 ;
+; 12 ; 7 ;
+; 13 ; 7 ;
+; 14 ; 6 ;
++---------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out (Average = 6.84) ; Number of LABs (Total = 114) ;
++-------------------------------------------------+-------------------------------+
+; 0 ; 0 ;
+; 1 ; 6 ;
+; 2 ; 1 ;
+; 3 ; 7 ;
+; 4 ; 7 ;
+; 5 ; 14 ;
+; 6 ; 15 ;
+; 7 ; 14 ;
+; 8 ; 17 ;
+; 9 ; 10 ;
+; 10 ; 18 ;
+; 11 ; 2 ;
+; 12 ; 2 ;
+; 13 ; 1 ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs (Average = 16.04) ; Number of LABs (Total = 114) ;
++----------------------------------------------+-------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 3 ;
+; 4 ; 1 ;
+; 5 ; 2 ;
+; 6 ; 1 ;
+; 7 ; 0 ;
+; 8 ; 2 ;
+; 9 ; 0 ;
+; 10 ; 5 ;
+; 11 ; 8 ;
+; 12 ; 7 ;
+; 13 ; 3 ;
+; 14 ; 9 ;
+; 15 ; 5 ;
+; 16 ; 5 ;
+; 17 ; 6 ;
+; 18 ; 7 ;
+; 19 ; 4 ;
+; 20 ; 18 ;
+; 21 ; 16 ;
+; 22 ; 11 ;
++----------------------------------------------+-------------------------------+
+--------------------------------------------------------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Thu Dec 16 16:54:47 2010
+ Info: Processing started: Fri Dec 17 10:10:15 2010
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
Info: Selected device EP1C12Q240C8 for design "dt"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "sys_clk" to use Global clock in PIN 152
+Info: Automatically promoted some destinations of signal "sys_res" to use Global clock
+ Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|new_tx_data" may be non-global or may not use global clock
+ Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[3]~3" may be non-global or may not use global clock
+Info: Pin "sys_res" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Extra Info: Started Fast Input/Output/OE register processing
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
-Info: Fitter preparation operations ending: elapsed time is 00:00:01
+Info: Fitter preparation operations ending: elapsed time is 00:00:02
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
-Info: Fitter placement operations ending: elapsed time is 00:00:01
-Info: Estimated most critical path is memory to register delay of 18.381 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3~portb_address_reg2'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3'
- Info: 3: + IC(1.233 ns) + CELL(0.442 ns) = 5.992 ns; Loc. = LAB_X32_Y14; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[3]~61'
- Info: 4: + IC(0.757 ns) + CELL(0.590 ns) = 7.339 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|left_operand[3]~62'
- Info: 5: + IC(1.395 ns) + CELL(0.575 ns) = 9.309 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~142COUT1_190'
- Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 9.389 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~27COUT1_192'
- Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 9.997 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~30'
- Info: 8: + IC(1.387 ns) + CELL(0.292 ns) = 11.676 ns; Loc. = LAB_X30_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
- Info: 9: + IC(0.900 ns) + CELL(0.442 ns) = 13.018 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~7'
- Info: 10: + IC(0.752 ns) + CELL(0.590 ns) = 14.360 ns; Loc. = LAB_X29_Y12; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~23'
- Info: 11: + IC(0.900 ns) + CELL(0.442 ns) = 15.702 ns; Loc. = LAB_X28_Y11; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1'
- Info: 12: + IC(1.812 ns) + CELL(0.867 ns) = 18.381 ns; Loc. = LAB_X36_Y14; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
- Info: Total cell delay = 9.245 ns ( 50.30 % )
- Info: Total interconnect delay = 9.136 ns ( 49.70 % )
+Info: Fitter placement operations ending: elapsed time is 00:00:02
+Info: Estimated most critical path is memory to register delay of 20.863 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3~portb_address_reg2'
+ Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3'
+ Info: 3: + IC(1.586 ns) + CELL(0.442 ns) = 6.345 ns; Loc. = LAB_X28_Y22; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[3]~19'
+ Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 6.998 ns; Loc. = LAB_X28_Y22; Fanout = 4; COMB Node = 'execute_stage:exec_st|left_operand[3]~20'
+ Info: 5: + IC(0.117 ns) + CELL(0.590 ns) = 7.705 ns; Loc. = LAB_X28_Y22; Fanout = 8; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector104~0'
+ Info: 6: + IC(0.995 ns) + CELL(0.575 ns) = 9.275 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~2COUT1_196'
+ Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.355 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~12COUT1_198'
+ Info: 8: + IC(0.000 ns) + CELL(0.258 ns) = 9.613 ns; Loc. = LAB_X31_Y22; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~17'
+ Info: 9: + IC(0.000 ns) + CELL(0.679 ns) = 10.292 ns; Loc. = LAB_X31_Y21; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~20'
+ Info: 10: + IC(0.771 ns) + CELL(0.432 ns) = 11.495 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[6]~22COUT1_195'
+ Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 11.575 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[7]~27COUT1_197'
+ Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 11.655 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[8]~32COUT1_199'
+ Info: 13: + IC(0.000 ns) + CELL(0.608 ns) = 12.263 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[9]~5'
+ Info: 14: + IC(1.264 ns) + CELL(0.114 ns) = 13.641 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector65~0'
+ Info: 15: + IC(0.361 ns) + CELL(0.292 ns) = 14.294 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector65~1'
+ Info: 16: + IC(0.063 ns) + CELL(0.590 ns) = 14.947 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~0'
+ Info: 17: + IC(0.303 ns) + CELL(0.590 ns) = 15.840 ns; Loc. = LAB_X30_Y17; Fanout = 7; COMB Node = 'writeback_stage:writeback_st|Equal0~5'
+ Info: 18: + IC(1.093 ns) + CELL(0.590 ns) = 17.523 ns; Loc. = LAB_X27_Y19; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
+ Info: 19: + IC(0.063 ns) + CELL(0.590 ns) = 18.176 ns; Loc. = LAB_X27_Y19; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~12'
+ Info: 20: + IC(0.211 ns) + CELL(0.442 ns) = 18.829 ns; Loc. = LAB_X27_Y19; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
+ Info: 21: + IC(1.167 ns) + CELL(0.867 ns) = 20.863 ns; Loc. = LAB_X28_Y21; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
+ Info: Total cell delay = 12.806 ns ( 61.38 % )
+ Info: Total interconnect delay = 8.057 ns ( 38.62 % )
Info: Fitter routing operations beginning
-Info: Router estimated average interconnect usage is 1% of the available device resources
- Info: Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
-Info: Fitter routing operations ending: elapsed time is 00:00:01
+Info: Router estimated average interconnect usage is 4% of the available device resources
+ Info: Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
+Info: Fitter routing operations ending: elapsed time is 00:00:04
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 266 megabytes
- Info: Processing ended: Thu Dec 16 16:54:58 2010
- Info: Elapsed time: 00:00:11
- Info: Total CPU time (on all processors): 00:00:11
+ Info: Peak virtual memory: 269 megabytes
+ Info: Processing ended: Fri Dec 17 10:10:34 2010
+ Info: Elapsed time: 00:00:19
+ Info: Total CPU time (on all processors): 00:00:19
-Fitter Status : Successful - Thu Dec 16 16:54:57 2010
+Fitter Status : Successful - Fri Dec 17 10:10:33 2010
Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
Revision Name : dt
Top-level Entity Name : core_top
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
-Total logic elements : 398 / 12,060 ( 3 % )
-Total pins : 2 / 173 ( 1 % )
+Total logic elements : 1,056 / 12,060 ( 9 % )
+Total pins : 3 / 173 ( 2 % )
Total virtual pins : 0
Total memory bits : 512 / 239,616 ( < 1 % )
Total PLLs : 0 / 2 ( 0 % )
Flow report for dt
-Thu Dec 16 16:55:05 2010
+Fri Dec 17 10:10:42 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+-----------------------------------------------+
-; Flow Status ; Successful - Thu Dec 16 16:55:05 2010 ;
+; Flow Status ; Successful - Fri Dec 17 10:10:42 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
-; Total logic elements ; 398 / 12,060 ( 3 % ) ;
-; Total pins ; 2 / 173 ( 1 % ) ;
+; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
+; Total pins ; 3 / 173 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 12/16/2010 16:54:33 ;
+; Start date & time ; 12/17/2010 10:09:48 ;
; Main task ; Compilation ;
; Revision Name ; dt ;
+-------------------+---------------------+
-+--------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+-----------------------------+---------------+-------------+------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+-----------------------------+---------------+-------------+------------+
-; COMPILER_SIGNATURE_ID ; 91815333562.129251487317236 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; MISC_FILE ; /homes/burban/dt/dt.dpf ; -- ; -- ; -- ;
-; PARTITION_COLOR ; 16764057 ; -- ; core_top ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; core_top ; Top ;
-; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; core_top ; Top ;
-; TOP_LEVEL_ENTITY ; core_top ; dt ; -- ; -- ;
-+-------------------------------------+-----------------------------+---------------+-------------+------------+
++-----------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+--------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+--------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID ; 91815333562.129257698817483 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; MISC_FILE ; /homes/burban/dt/dt.dpf ; -- ; -- ; -- ;
+; MISC_FILE ; /homes/c0726283/calu/dt/dt.dpf ; -- ; -- ; -- ;
+; PARTITION_COLOR ; 16764057 ; -- ; core_top ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; core_top ; Top ;
+; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; core_top ; Top ;
+; TOP_LEVEL_ENTITY ; core_top ; dt ; -- ; -- ;
++-------------------------------------+--------------------------------+---------------+-------------+------------+
+-----------------------------------------------------------------------------------------------------------------------------+
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:10 ; 1.0 ; -- ; 00:00:09 ;
-; Fitter ; 00:00:10 ; 1.0 ; -- ; 00:00:11 ;
-; Assembler ; 00:00:03 ; 1.0 ; -- ; 00:00:02 ;
-; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; -- ; 00:00:00 ;
-; Total ; 00:00:23 ; -- ; -- ; 00:00:22 ;
+; Analysis & Synthesis ; 00:00:24 ; 1.0 ; -- ; 00:00:20 ;
+; Fitter ; 00:00:18 ; 1.0 ; -- ; 00:00:18 ;
+; Assembler ; 00:00:02 ; 1.0 ; -- ; 00:00:02 ;
+; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; -- ; 00:00:01 ;
+; Total ; 00:00:45 ; -- ; -- ; 00:00:41 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
Analysis & Synthesis report for dt
-Thu Dec 16 16:54:44 2010
+Fri Dec 17 10:10:12 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
29. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
30. altsyncram Parameter Settings by Entity Instance
31. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart"
- 32. Port Connectivity Checks: "writeback_stage:writeback_st"
- 33. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
- 34. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
- 35. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
- 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
- 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
- 38. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
- 39. Port Connectivity Checks: "execute_stage:exec_st"
- 40. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
- 41. Port Connectivity Checks: "decode_stage:decode_st"
- 42. Port Connectivity Checks: "fetch_stage:fetch_st"
- 43. Analysis & Synthesis Messages
+ 32. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
+ 33. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
+ 34. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
+ 35. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
+ 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
+ 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
+ 38. Port Connectivity Checks: "execute_stage:exec_st"
+ 39. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
+ 40. Analysis & Synthesis Messages
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Dec 16 16:54:44 2010 ;
+; Analysis & Synthesis Status ; Successful - Fri Dec 17 10:10:12 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
-; Total logic elements ; 435 ;
-; Total pins ; 2 ;
+; Total logic elements ; 1,142 ;
+; Total pins ; 3 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 ;
; Total PLLs ; 0 ;
+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
-; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/writeback_stage_b.vhd ;
-; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/writeback_stage.vhd ;
-; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/rs232_tx_arc.vhd ;
-; ../cpu/src/rs232_tx.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/rs232_tx.vhd ;
-; ../cpu/src/r_w_ram_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/r_w_ram_b.vhd ;
-; ../cpu/src/r_w_ram.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/r_w_ram.vhd ;
-; ../cpu/src/r2_w_ram_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/r2_w_ram_b.vhd ;
-; ../cpu/src/r2_w_ram.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/r2_w_ram.vhd ;
-; ../cpu/src/mem_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/mem_pkg.vhd ;
-; ../cpu/src/fetch_stage_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/fetch_stage_b.vhd ;
-; ../cpu/src/fetch_stage.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/fetch_stage.vhd ;
-; ../cpu/src/extension_uart_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_uart_pkg.vhd ;
-; ../cpu/src/extension_uart_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_uart_b.vhd ;
-; ../cpu/src/extension_uart.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_uart.vhd ;
-; ../cpu/src/extension_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_pkg.vhd ;
-; ../cpu/src/extension_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension_b.vhd ;
-; ../cpu/src/extension.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/extension.vhd ;
-; ../cpu/src/execute_stage_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/execute_stage_b.vhd ;
-; ../cpu/src/execute_stage.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/execute_stage.vhd ;
-; ../cpu/src/exec_op.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op.vhd ;
-; ../cpu/src/decoder_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/decoder_b.vhd ;
-; ../cpu/src/decoder.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/decoder.vhd ;
-; ../cpu/src/decode_stage_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/decode_stage_b.vhd ;
-; ../cpu/src/decode_stage.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/decode_stage.vhd ;
-; ../cpu/src/core_top.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/core_top.vhd ;
-; ../cpu/src/core_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/core_pkg.vhd ;
-; ../cpu/src/common_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/common_pkg.vhd ;
-; ../cpu/src/alu_pkg.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/alu_pkg.vhd ;
-; ../cpu/src/alu_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/alu_b.vhd ;
-; ../cpu/src/alu.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/alu.vhd ;
-; ../cpu/src/exec_op/xor_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/xor_op_b.vhd ;
-; ../cpu/src/exec_op/shift_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/shift_op_b.vhd ;
-; ../cpu/src/exec_op/or_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/or_op_b.vhd ;
-; ../cpu/src/exec_op/and_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/and_op_b.vhd ;
-; ../cpu/src/exec_op/add_op_b.vhd ; yes ; User VHDL File ; /homes/burban/calu/cpu/src/exec_op/add_op_b.vhd ;
+; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/writeback_stage_b.vhd ;
+; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/writeback_stage.vhd ;
+; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_tx_arc.vhd ;
+; ../cpu/src/rs232_tx.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_tx.vhd ;
+; ../cpu/src/r_w_ram_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r_w_ram_b.vhd ;
+; ../cpu/src/r_w_ram.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r_w_ram.vhd ;
+; ../cpu/src/r2_w_ram_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r2_w_ram_b.vhd ;
+; ../cpu/src/r2_w_ram.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r2_w_ram.vhd ;
+; ../cpu/src/mem_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/mem_pkg.vhd ;
+; ../cpu/src/fetch_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/fetch_stage_b.vhd ;
+; ../cpu/src/fetch_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/fetch_stage.vhd ;
+; ../cpu/src/extension_uart_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart_pkg.vhd ;
+; ../cpu/src/extension_uart_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart_b.vhd ;
+; ../cpu/src/extension_uart.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart.vhd ;
+; ../cpu/src/extension_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_pkg.vhd ;
+; ../cpu/src/extension_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_b.vhd ;
+; ../cpu/src/extension.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension.vhd ;
+; ../cpu/src/execute_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/execute_stage_b.vhd ;
+; ../cpu/src/execute_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/execute_stage.vhd ;
+; ../cpu/src/exec_op.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op.vhd ;
+; ../cpu/src/decoder_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decoder_b.vhd ;
+; ../cpu/src/decoder.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decoder.vhd ;
+; ../cpu/src/decode_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decode_stage_b.vhd ;
+; ../cpu/src/decode_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decode_stage.vhd ;
+; ../cpu/src/core_top.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/core_top.vhd ;
+; ../cpu/src/core_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/core_pkg.vhd ;
+; ../cpu/src/common_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/common_pkg.vhd ;
+; ../cpu/src/alu_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu_pkg.vhd ;
+; ../cpu/src/alu_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu_b.vhd ;
+; ../cpu/src/alu.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu.vhd ;
+; ../cpu/src/exec_op/xor_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/xor_op_b.vhd ;
+; ../cpu/src/exec_op/shift_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/shift_op_b.vhd ;
+; ../cpu/src/exec_op/or_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/or_op_b.vhd ;
+; ../cpu/src/exec_op/and_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/and_op_b.vhd ;
+; ../cpu/src/exec_op/add_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/add_op_b.vhd ;
; altsyncram.tdf ; yes ; Megafunction ; /opt/altera/10.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ;
-; db/altsyncram_emk1.tdf ; yes ; Auto-Generated Megafunction ; /homes/burban/calu/dt/db/altsyncram_emk1.tdf ;
-; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /homes/burban/calu/dt/db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
+; db/altsyncram_emk1.tdf ; yes ; Auto-Generated Megafunction ; /homes/c0726283/calu/dt/db/altsyncram_emk1.tdf ;
+; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /homes/c0726283/calu/dt/db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
-; Total logic elements ; 435 ;
-; -- Combinational with no register ; 294 ;
-; -- Register only ; 49 ;
-; -- Combinational with a register ; 92 ;
+; Total logic elements ; 1142 ;
+; -- Combinational with no register ; 927 ;
+; -- Register only ; 86 ;
+; -- Combinational with a register ; 129 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 105 ;
-; -- 3 input functions ; 195 ;
-; -- 2 input functions ; 80 ;
-; -- 1 input functions ; 4 ;
-; -- 0 input functions ; 2 ;
+; -- 4 input functions ; 467 ;
+; -- 3 input functions ; 447 ;
+; -- 2 input functions ; 123 ;
+; -- 1 input functions ; 18 ;
+; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 335 ;
-; -- arithmetic mode ; 100 ;
+; -- normal mode ; 936 ;
+; -- arithmetic mode ; 206 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 3 ;
-; -- asynchronous clear/load mode ; 0 ;
+; -- synchronous clear/load mode ; 7 ;
+; -- asynchronous clear/load mode ; 202 ;
; ; ;
-; Total registers ; 141 ;
-; Total logic cells in carry chains ; 104 ;
-; I/O pins ; 2 ;
+; Total registers ; 215 ;
+; Total logic cells in carry chains ; 214 ;
+; I/O pins ; 3 ;
; Total memory bits ; 512 ;
; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 205 ;
-; Total fan-out ; 1762 ;
-; Average fan-out ; 3.52 ;
+; Maximum fan-out ; 279 ;
+; Total fan-out ; 4453 ;
+; Average fan-out ; 3.68 ;
+---------------------------------------------+---------+
+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 435 (1) ; 141 ; 512 ; 2 ; 0 ; 294 (1) ; 49 (0) ; 92 (0) ; 104 (0) ; 0 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 43 (42) ; 42 ; 512 ; 0 ; 0 ; 1 (0) ; 35 (35) ; 7 (7) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |core_top ; 1142 (1) ; 215 ; 512 ; 3 ; 0 ; 927 (1) ; 86 (0) ; 129 (0) ; 214 (0) ; 0 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 109 (101) ; 72 ; 512 ; 0 ; 0 ; 37 (29) ; 52 (52) ; 20 (20) ; 11 (11) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 226 (164) ; 34 ; 0 ; 0 ; 0 ; 192 (130) ; 1 (1) ; 33 (33) ; 61 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 62 (30) ; 0 ; 0 ; 0 ; 0 ; 62 (30) ; 0 (0) ; 0 (0) ; 61 (29) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |fetch_stage:fetch_st| ; 29 (22) ; 14 ; 0 ; 0 ; 0 ; 15 (11) ; 12 (11) ; 2 (0) ; 11 (11) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |r_w_ram:instruction_ram| ; 7 (7) ; 3 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 2 (2) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 136 (28) ; 51 ; 0 ; 0 ; 0 ; 85 (26) ; 1 (0) ; 50 (2) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_uart:uart| ; 108 (14) ; 49 ; 0 ; 0 ; 0 ; 59 (4) ; 1 (1) ; 48 (9) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |execute_stage:exec_st| ; 826 (185) ; 67 ; 0 ; 0 ; 0 ; 759 (149) ; 20 (1) ; 47 (35) ; 171 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 576 (255) ; 0 ; 0 ; 0 ; 0 ; 576 (255) ; 0 (0) ; 0 (0) ; 141 (43) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |exec_op:or_inst| ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
+; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
+; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 34 (34) ; 19 (19) ; 12 (12) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
+; |fetch_stage:fetch_st| ; 39 (30) ; 17 ; 0 ; 0 ; 0 ; 22 (19) ; 11 (11) ; 6 (0) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 167 (53) ; 59 ; 0 ; 0 ; 0 ; 108 (49) ; 3 (1) ; 56 (3) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_uart:uart| ; 108 (14) ; 49 ; 0 ; 0 ; 0 ; 59 (4) ; 2 (2) ; 47 (8) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
+; |r_w_ram:data_ram| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+--------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-; Register name ; Reason for Removal ;
-+--------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24,26] ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0..2,5,8,10..14,16..18,20,22] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24,26] ; Stuck at VCC due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0..2,5,8,10..14,16..18,20,22] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.op_detail[1..2,5] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.brpr ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.displacement[0..2,5,8,10..31] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.saddr1[1..3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.saddr2[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.daddr[1,3] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|reg.res_addr[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|rtw_rec.immediate[2,5,7..11,13..31] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|reg.brpr ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29..30] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[31] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4,6,23,25] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3,15,19] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29..30] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[4,6,23,25] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[3,15,19] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[7] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ;
-; decode_stage:decode_st|dec_op_inst.daddr[2] ; Lost fanout ;
-; execute_stage:exec_st|reg.res_addr[0] ; Merged with execute_stage:exec_st|reg.res_addr[2] ;
-; decode_stage:decode_st|rtw_rec.immediate[0] ; Merged with decode_stage:decode_st|rtw_rec.immediate[12] ;
-; decode_stage:decode_st|rtw_rec.immediate[4] ; Merged with decode_stage:decode_st|rtw_rec.immediate[6] ;
-; decode_stage:decode_st|rtw_rec.immediate[1] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
-; decode_stage:decode_st|dec_op_inst.condition[1..2] ; Merged with decode_stage:decode_st|dec_op_inst.condition[3] ;
-; decode_stage:decode_st|dec_op_inst.displacement[7] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[9] ;
-; decode_stage:decode_st|dec_op_inst.displacement[4] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[6] ;
-; decode_stage:decode_st|dec_op_inst.saddr2[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr2[2] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[4] ; Stuck at VCC due to stuck port data_in ;
-; execute_stage:exec_st|reg.alu_jump ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.condition[0] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|rtw_rec.imm_set ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
-; decode_stage:decode_st|dec_op_inst.displacement[6] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[3] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
-; writeback_stage:writeback_st|wb_reg.dmem_write_en ; Merged with writeback_stage:writeback_st|wb_reg.dmem_en ;
-; decode_stage:decode_st|dec_op_inst.saddr1[0] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[3] ;
-; decode_stage:decode_st|dec_op_inst.prog_cnt[0..10] ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.condition[3] ; Lost fanout ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; Lost fanout ;
-; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
-; Total Number of Removed Registers = 330 ; ;
-+--------------------------------------------------------------------------------------+------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++-------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+; Register name ; Reason for Removal ;
++-------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0,2,5,8,10..14,16..18,20,22] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0,2,5,8,10..14,16..18,20,22] ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.condition[1..3] ; Stuck at VCC due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.op_detail[5] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.displacement[0,2,5,8,10..31] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.saddr1[1,3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.saddr2[1,3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|dec_op_inst.daddr[1,3] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|reg.res_addr[1,3] ; Stuck at GND due to stuck port data_in ;
+; decode_stage:decode_st|rtw_rec.immediate[5,7,9..11,13,15] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[23] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[1] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4,6] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[19] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[15] ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[23] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[1] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[4,6] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[19] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[3] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[15] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[7] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ;
+; decode_stage:decode_st|dec_op_inst.daddr[2] ; Lost fanout ;
+; execute_stage:exec_st|reg.res_addr[0] ; Merged with execute_stage:exec_st|reg.res_addr[2] ;
+; decode_stage:decode_st|rtw_rec.immediate[18,21,23..27,29..30] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
+; decode_stage:decode_st|rtw_rec.immediate[16] ; Merged with decode_stage:decode_st|rtw_rec.immediate[28] ;
+; decode_stage:decode_st|rtw_rec.immediate[20] ; Merged with decode_stage:decode_st|rtw_rec.immediate[22] ;
+; decode_stage:decode_st|rtw_rec.immediate[17] ; Merged with decode_stage:decode_st|rtw_rec.immediate[19] ;
+; decode_stage:decode_st|rtw_rec.immediate[1] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
+; decode_stage:decode_st|dec_op_inst.displacement[7] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[9] ;
+; decode_stage:decode_st|dec_op_inst.displacement[4] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[6] ;
+; decode_stage:decode_st|dec_op_inst.saddr2[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr2[2] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[1] ; Merged with decode_stage:decode_st|dec_op_inst.op_detail[2] ;
+; decode_stage:decode_st|rtw_rec.immediate[19,22,28] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
+; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; Lost fanout ;
+; decode_stage:decode_st|rtw_rec.immediate[31] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.OR_OP ;
+; decode_stage:decode_st|rtw_rec.immediate[8] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ;
+; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
+; Total Number of Removed Registers = 261 ; ;
++-------------------------------------------------------------------------------------+------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+-----------------------------------------------------------+---------------------------+------------------------------------------------------------------------------------+
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.brpr, execute_stage:exec_st|reg.brpr, ;
-; ; due to stuck port data_in ; execute_stage:exec_st|reg.alu_jump, ;
-; ; ; decode_stage:decode_st|dec_op_inst.condition[0], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry, ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1], ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0], ;
-; ; ; decode_stage:decode_st|dec_op_inst.condition[3], ;
-; ; ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.op_detail[5], ;
-; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.op_detail[1], ;
-; ; ; decode_stage:decode_st|dec_op_inst.saddr1[3], ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.op_detail[5], ;
+; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.saddr1[3], ;
; ; ; decode_stage:decode_st|dec_op_inst.saddr1[1], ;
; ; ; decode_stage:decode_st|dec_op_inst.saddr2[3], ;
; ; ; decode_stage:decode_st|dec_op_inst.saddr2[1], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[31], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[26], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[25], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[24], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[23], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[22], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[21], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[20], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[19], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[18], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[17], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[16], ;
; ; ; decode_stage:decode_st|rtw_rec.immediate[15], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[14], ;
; ; ; decode_stage:decode_st|rtw_rec.immediate[13], ;
; ; ; decode_stage:decode_st|rtw_rec.immediate[11], ;
; ; ; decode_stage:decode_st|rtw_rec.immediate[10], ;
; ; ; decode_stage:decode_st|rtw_rec.immediate[9], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[8], ;
; ; ; decode_stage:decode_st|rtw_rec.immediate[7], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[5], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[2], ;
-; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[8], ;
-; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[9], ;
-; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[10], ;
-; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[2], ;
-; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[5], ;
-; ; ; decode_stage:decode_st|dec_op_inst.prog_cnt[7] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[1] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.op_detail[2], ;
-; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.displacement[1], ;
+; ; ; decode_stage:decode_st|rtw_rec.immediate[5] ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[3], ;
+; ; due to stuck port data_in ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo, ;
; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[22] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[3], execute_stage:exec_st|reg.res_addr[3] ;
; ; due to stuck port data_in ; ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[20] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[1], execute_stage:exec_st|reg.res_addr[1] ;
; ; due to stuck port data_in ; ;
-; decode_stage:decode_st|dec_op_inst.prog_cnt[31] ; Stuck at GND ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[30] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[2] ;
; ; due to stuck port data_in ; ;
-; decode_stage:decode_st|dec_op_inst.prog_cnt[23] ; Stuck at GND ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[1] ;
; ; due to stuck port data_in ; ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[14] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[14] ;
; ; due to stuck port data_in ; ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
-; Total registers ; 141 ;
-; Number of registers using Synchronous Clear ; 1 ;
-; Number of registers using Synchronous Load ; 2 ;
-; Number of registers using Asynchronous Clear ; 0 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 13 ;
+; Total registers ; 215 ;
+; Number of registers using Synchronous Clear ; 4 ;
+; Number of registers using Synchronous Load ; 6 ;
+; Number of registers using Asynchronous Clear ; 191 ;
+; Number of registers using Asynchronous Load ; 11 ;
+; Number of registers using Clock Enable ; 44 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 2 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 2 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 2 ;
-; Total number of inverted registers = 12 ; ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 2 ;
+; decode_stage:decode_st|dec_op_inst.condition[0] ; 1 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 4 ;
+; Total number of inverted registers = 24 ; ;
+--------------------------------------------------------------------------------------+---------+
+------------------------------------------------------------+-----------------------------------------------------+------+
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
-; 3:1 ; 21 bits ; 42 LEs ; 21 LEs ; 21 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24] ;
-; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[12] ;
-; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ;
-; 18:1 ; 3 bits ; 36 LEs ; 3 LEs ; 33 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ;
-; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ;
-; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |core_top|writeback_stage:writeback_st|ext_uart.addr[1] ;
-; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|left_operand[28] ;
-; 4:1 ; 28 bits ; 56 LEs ; 56 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[2] ;
-; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[6] ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+; 3:1 ; 21 bits ; 42 LEs ; 21 LEs ; 21 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ;
+; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |core_top|decode_stage:decode_st|dec_op_inst.displacement[1] ;
+; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ;
+; 5:1 ; 14 bits ; 42 LEs ; 28 LEs ; 14 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[30] ;
+; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[21] ;
+; 18:1 ; 3 bits ; 36 LEs ; 3 LEs ; 33 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ;
+; 9:1 ; 5 bits ; 30 LEs ; 25 LEs ; 5 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[11] ;
+; 9:1 ; 13 bits ; 78 LEs ; 65 LEs ; 13 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[17] ;
+; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[6] ;
+; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[25] ;
+; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[1] ;
+; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[29] ;
+; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ;
+; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|left_operand[13] ;
+; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
+; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[7] ;
+; 4:1 ; 25 bits ; 50 LEs ; 50 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[14] ;
+; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector53 ;
+; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[2] ;
+; 5:1 ; 6 bits ; 18 LEs ; 12 LEs ; 6 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[3] ;
+; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector107 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
+----------+--------+----------+-------------------------------------------------------------------------------------+
-+----------------------------------------------------------+
-; Port Connectivity Checks: "writeback_stage:writeback_st" ;
-+-------+-------+----------+-------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-------------------------------+
-; reset ; Input ; Info ; Stuck at VCC ;
-+-------+-------+----------+-------------------------------+
-
-
+----------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst" ;
+------------------------+--------+----------+-------------------------------------------------------------------------------------+
+--------------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
-; reset ; Input ; Info ; Stuck at VCC ;
; ext_data_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------------+--------+----------+-------------------------------------------------------------------------------------+
+--------------------+--------+----------+-------------------------------------------------------------------------------------+
-+----------------------------------------------------+
-; Port Connectivity Checks: "decode_stage:decode_st" ;
-+-------+-------+----------+-------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-------------------------+
-; reset ; Input ; Info ; Stuck at VCC ;
-+-------+-------+----------+-------------------------+
-
-
-+--------------------------------------------------+
-; Port Connectivity Checks: "fetch_stage:fetch_st" ;
-+-------+-------+----------+-----------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+-----------------------+
-; reset ; Input ; Info ; Stuck at VCC ;
-+-------+-------+----------+-----------------------+
-
-
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Thu Dec 16 16:54:33 2010
+ Info: Processing started: Fri Dec 17 10:09:47 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dt -c dt
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/writeback_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/writeback_stage_b.vhd
Info: Found design unit 1: writeback_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/writeback_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/writeback_stage.vhd
Info: Found entity 1: writeback_stage
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/rw_r_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rw_r_ram_b.vhd
Info: Found design unit 1: rw_r_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/rw_r_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rw_r_ram.vhd
Info: Found entity 1: rw_r_ram
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/rs232_tx_arc.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rs232_tx_arc.vhd
Info: Found design unit 1: rs232_tx-beh
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/rs232_tx.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rs232_tx.vhd
Info: Found entity 1: rs232_tx
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/r_w_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/r_w_ram_b.vhd
Info: Found design unit 1: r_w_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/r_w_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/r_w_ram.vhd
Info: Found entity 1: r_w_ram
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/r2_w_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/r2_w_ram_b.vhd
Info: Found design unit 1: r2_w_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/r2_w_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/r2_w_ram.vhd
Info: Found entity 1: r2_w_ram
-Info: Found 3 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/pipeline_tb.vhd
+Info: Found 3 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/pipeline_tb.vhd
Info: Found design unit 1: pipeline_tb-behavior
Info: Found design unit 2: pipeline_conf_beh
Info: Found entity 1: pipeline_tb
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/mem_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/mem_pkg.vhd
Info: Found design unit 1: mem_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/fetch_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/fetch_stage_b.vhd
Info: Found design unit 1: fetch_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/fetch_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/fetch_stage.vhd
Info: Found entity 1: fetch_stage
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/extension_uart_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart_pkg.vhd
Info: Found design unit 1: extension_uart_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/extension_uart_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart_b.vhd
Info: Found design unit 1: extension_uart-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/extension_uart.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart.vhd
Info: Found entity 1: extension_uart
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/extension_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_pkg.vhd
Info: Found design unit 1: extension_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/extension_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_b.vhd
Info: Found design unit 1: extension_gpm-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/extension.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/extension.vhd
Info: Found entity 1: extension_gpm
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/execute_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/execute_stage_b.vhd
Info: Found design unit 1: execute_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/execute_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/execute_stage.vhd
Info: Found entity 1: execute_stage
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/exec_op.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/exec_op.vhd
Info: Found entity 1: exec_op
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/decoder_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/decoder_b.vhd
Info: Found design unit 1: decoder-behav_d
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/decoder.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/decoder.vhd
Info: Found entity 1: decoder
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/decode_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/decode_stage_b.vhd
Info: Found design unit 1: decode_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/decode_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/decode_stage.vhd
Info: Found entity 1: decode_stage
-Info: Found 2 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/core_top.vhd
+Info: Found 2 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/core_top.vhd
Info: Found design unit 1: core_top-behav
Info: Found entity 1: core_top
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/core_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/core_pkg.vhd
Info: Found design unit 1: core_pkg
-Info: Found 2 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/common_pkg.vhd
+Info: Found 2 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/common_pkg.vhd
Info: Found design unit 1: common_pkg
Info: Found design unit 2: common_pkg-body
-Info: Found 2 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/alu_pkg.vhd
+Info: Found 2 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/alu_pkg.vhd
Info: Found design unit 1: alu_pkg
Info: Found design unit 2: alu_pkg-body
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/alu_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/alu_b.vhd
Info: Found design unit 1: alu-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/burban/calu/cpu/src/alu.vhd
+Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/alu.vhd
Info: Found entity 1: alu
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/xor_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/xor_op_b.vhd
Info: Found design unit 1: exec_op-xor_op
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/shift_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/shift_op_b.vhd
Info: Found design unit 1: exec_op-shift_op
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/or_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/or_op_b.vhd
Info: Found design unit 1: exec_op-or_op
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/and_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/and_op_b.vhd
Info: Found design unit 1: exec_op-and_op
-Info: Found 1 design units, including 0 entities, in source file /homes/burban/calu/cpu/src/exec_op/add_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/add_op_b.vhd
Info: Found design unit 1: exec_op-add_op
Info: Elaborating entity "core_top" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(24): object "jump_result" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(25): object "jump_result" assigned a value but never read
Warning (10541): VHDL Signal Declaration warning at core_top.vhd(53): used implicit default value for signal "gpm_in_pin" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(54): object "gpm_out_pin" assigned a value but never read
Info: Elaborating entity "fetch_stage" for hierarchy "fetch_stage:fetch_st"
Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_emk1.tdf
Info: Found entity 1: altsyncram_emk1
-Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1"
-Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1" with the following parameter:
- Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
- Info: Parameter "WIDTH_A" = "32"
- Info: Parameter "WIDTHAD_A" = "4"
- Info: Parameter "NUMWORDS_A" = "16"
- Info: Parameter "WIDTH_B" = "32"
- Info: Parameter "WIDTHAD_B" = "4"
- Info: Parameter "NUMWORDS_B" = "16"
- Info: Parameter "ADDRESS_ACLR_A" = "NONE"
- Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
- Info: Parameter "ADDRESS_ACLR_B" = "NONE"
- Info: Parameter "OUTDATA_ACLR_B" = "NONE"
- Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
- Info: Parameter "INDATA_ACLR_A" = "NONE"
- Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
- Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
- Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
-Info: 132 registers lost all their fanouts during netlist optimizations. The first 132 are displayed below.
+Info: Registers with preset signals will power-up high
+Info: 117 registers lost all their fanouts during netlist optimizations. The first 117 are displayed below.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0]" lost all its fanouts during netlist optimizations.
Info: Register "decode_stage:decode_st|dec_op_inst.daddr[2]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[8]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[9]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[10]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[0]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[1]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[2]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[3]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[4]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[5]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[6]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.prog_cnt[7]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.condition[3]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP" lost all its fanouts during netlist optimizations.
Info: Register "decode_stage:decode_st|dec_op_inst.op_group.AND_OP" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.OR_OP" lost all its fanouts during netlist optimizations.
Info: Register "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.JMP_OP" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[31]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[30]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[29]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[28]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[27]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[26]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[25]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[24]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[23]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[22]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[21]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[20]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[19]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[18]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[17]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[16]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[15]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[14]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[13]" lost all its fanouts during netlist optimizations.
- Info: Register "fetch_stage:fetch_st|instr_r_addr[12]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[11]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[12]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[13]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[14]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[15]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[16]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[17]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[18]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[19]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[20]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[21]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[22]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[23]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[24]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[25]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[26]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[27]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[28]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[29]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[30]" lost all its fanouts during netlist optimizations.
+ Info: Register "fetch_stage:fetch_st|instr_r_addr[31]" lost all its fanouts during netlist optimizations.
Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM"
Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM"
Info: Generating hard_block partition "hard_block:auto_generated_inst"
-Info: Implemented 501 device resources after synthesis - the final resource count might be different
- Info: Implemented 1 input pins
+Info: Implemented 1209 device resources after synthesis - the final resource count might be different
+ Info: Implemented 2 input pins
Info: Implemented 1 output pins
- Info: Implemented 435 logic cells
+ Info: Implemented 1142 logic cells
Info: Implemented 64 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 267 megabytes
- Info: Processing ended: Thu Dec 16 16:54:44 2010
- Info: Elapsed time: 00:00:11
- Info: Total CPU time (on all processors): 00:00:10
+ Info: Processing ended: Fri Dec 17 10:10:12 2010
+ Info: Elapsed time: 00:00:25
+ Info: Total CPU time (on all processors): 00:00:21
-Analysis & Synthesis Status : Successful - Thu Dec 16 16:54:44 2010
+Analysis & Synthesis Status : Successful - Fri Dec 17 10:10:12 2010
Quartus II Version : 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition
Revision Name : dt
Top-level Entity Name : core_top
Family : Cyclone
-Total logic elements : 435
-Total pins : 2
+Total logic elements : 1,142
+Total pins : 3
Total virtual pins : 0
Total memory bits : 512
Total PLLs : 0
RESERVED_INPUT : 39 : : : : 1 :
GND : 40 : gnd : : : :
RESERVED_INPUT : 41 : : : : 1 :
-RESERVED_INPUT : 42 : : : : 1 :
+sys_res : 42 : input : 3.3-V LVCMOS : : 1 : Y
RESERVED_INPUT : 43 : : : : 1 :
RESERVED_INPUT : 44 : : : : 1 :
RESERVED_INPUT : 45 : : : : 1 :
set_location_assignment PIN_152 -to sys_clk
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
+set_location_assignment PIN_42 -to sys_res
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Classic Timing Analyzer report for dt
-Thu Dec 16 16:55:05 2010
+Fri Dec 17 10:10:42 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
5. Clock Settings Summary
6. Parallel Compilation
7. Clock Setup: 'sys_clk'
- 8. tco
- 9. Timing Analyzer Messages
+ 8. tsu
+ 9. tco
+ 10. th
+ 11. Timing Analyzer Messages
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
-; Worst-case tco ; N/A ; None ; 8.846 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
-; Clock Setup: 'sys_clk' ; N/A ; None ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
+; Worst-case tsu ; N/A ; None ; 16.692 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; -- ; sys_clk ; 0 ;
+; Worst-case tco ; N/A ; None ; 8.362 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -8.416 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; -- ; sys_clk ; 0 ;
+; Clock Setup: 'sys_clk' ; N/A ; None ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+--------------+
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
-; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
-; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
-; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
-; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
-; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
-; N/A ; 49.70 MHz ( period = 20.119 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.416 ns ;
-; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
-; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
-; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
-; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
-; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
-; N/A ; 50.36 MHz ( period = 19.856 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.162 ns ;
-; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
-; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
-; N/A ; 51.44 MHz ( period = 19.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.669 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 51.64 MHz ( period = 19.366 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.663 ns ;
-; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
-; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
-; N/A ; 52.15 MHz ( period = 19.176 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.415 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 52.35 MHz ( period = 19.103 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.409 ns ;
-; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
-; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
-; N/A ; 54.24 MHz ( period = 18.437 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.734 ns ;
-; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
-; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
-; N/A ; 55.02 MHz ( period = 18.174 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 17.480 ns ;
-; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
-; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
-; N/A ; 57.24 MHz ( period = 17.470 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.700 ns ;
-; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
-; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
-; N/A ; 58.12 MHz ( period = 17.207 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 16.446 ns ;
-; N/A ; 59.51 MHz ( period = 16.805 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.544 ns ;
-; N/A ; 59.51 MHz ( period = 16.805 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.544 ns ;
-; N/A ; 59.73 MHz ( period = 16.743 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.473 ns ;
-; N/A ; 59.73 MHz ( period = 16.743 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.473 ns ;
-; N/A ; 60.26 MHz ( period = 16.594 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.324 ns ;
-; N/A ; 60.26 MHz ( period = 16.594 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.324 ns ;
-; N/A ; 60.70 MHz ( period = 16.475 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.205 ns ;
-; N/A ; 60.70 MHz ( period = 16.475 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.205 ns ;
-; N/A ; 61.33 MHz ( period = 16.306 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 16.036 ns ;
-; N/A ; 61.33 MHz ( period = 16.306 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 16.036 ns ;
-; N/A ; 62.02 MHz ( period = 16.125 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.797 ns ;
-; N/A ; 62.17 MHz ( period = 16.085 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.815 ns ;
-; N/A ; 62.17 MHz ( period = 16.085 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.815 ns ;
-; N/A ; 62.25 MHz ( period = 16.063 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.726 ns ;
-; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
-; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
-; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
-; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
-; N/A ; 62.30 MHz ( period = 16.052 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.791 ns ;
-; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
-; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
-; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
-; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
-; N/A ; 62.54 MHz ( period = 15.990 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.720 ns ;
-; N/A ; 62.84 MHz ( period = 15.914 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.577 ns ;
-; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
-; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
-; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
-; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
-; N/A ; 63.13 MHz ( period = 15.841 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.571 ns ;
-; N/A ; 63.24 MHz ( period = 15.812 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.542 ns ;
-; N/A ; 63.24 MHz ( period = 15.812 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.542 ns ;
-; N/A ; 63.31 MHz ( period = 15.795 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.458 ns ;
-; N/A ; 63.53 MHz ( period = 15.741 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.480 ns ;
-; N/A ; 63.53 MHz ( period = 15.741 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.480 ns ;
-; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
-; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
-; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
-; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
-; N/A ; 63.61 MHz ( period = 15.722 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.452 ns ;
-; N/A ; 64.00 MHz ( period = 15.626 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.289 ns ;
-; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
-; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
-; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
-; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
-; N/A ; 64.30 MHz ( period = 15.553 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.283 ns ;
-; N/A ; 64.86 MHz ( period = 15.417 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 15.156 ns ;
-; N/A ; 64.86 MHz ( period = 15.417 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 15.156 ns ;
-; N/A ; 64.91 MHz ( period = 15.405 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 15.068 ns ;
-; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
-; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
-; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
-; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
-; N/A ; 65.22 MHz ( period = 15.332 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 15.062 ns ;
-; N/A ; 66.09 MHz ( period = 15.132 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.795 ns ;
-; N/A ; 66.12 MHz ( period = 15.123 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.862 ns ;
-; N/A ; 66.40 MHz ( period = 15.061 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.733 ns ;
-; N/A ; 66.40 MHz ( period = 15.061 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.791 ns ;
-; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
-; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
-; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
-; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
-; N/A ; 66.41 MHz ( period = 15.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.789 ns ;
-; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
-; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
-; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
-; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
-; N/A ; 66.72 MHz ( period = 14.988 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.727 ns ;
-; N/A ; 67.06 MHz ( period = 14.912 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.642 ns ;
-; N/A ; 67.32 MHz ( period = 14.854 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.593 ns ;
-; N/A ; 67.32 MHz ( period = 14.854 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.593 ns ;
-; N/A ; 67.60 MHz ( period = 14.793 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.523 ns ;
-; N/A ; 67.86 MHz ( period = 14.737 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 14.409 ns ;
-; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
-; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
-; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
-; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
-; N/A ; 68.19 MHz ( period = 14.664 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 14.403 ns ;
-; N/A ; 68.38 MHz ( period = 14.624 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.354 ns ;
-; N/A ; 68.41 MHz ( period = 14.618 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.424 ns ;
-; N/A ; 68.41 MHz ( period = 14.618 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.424 ns ;
-; N/A ; 68.73 MHz ( period = 14.549 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.288 ns ;
-; N/A ; 68.73 MHz ( period = 14.549 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.288 ns ;
-; N/A ; 68.77 MHz ( period = 14.541 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.280 ns ;
-; N/A ; 68.77 MHz ( period = 14.541 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.280 ns ;
-; N/A ; 69.24 MHz ( period = 14.443 ns ) ; decode_stage:decode_st|rtw_rec.immediate[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.182 ns ;
-; N/A ; 69.24 MHz ( period = 14.443 ns ) ; decode_stage:decode_st|rtw_rec.immediate[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.182 ns ;
-; N/A ; 69.43 MHz ( period = 14.403 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 14.133 ns ;
-; N/A ; 69.48 MHz ( period = 14.393 ns ) ; execute_stage:exec_st|reg.result[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.132 ns ;
-; N/A ; 69.48 MHz ( period = 14.393 ns ) ; execute_stage:exec_st|reg.result[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.132 ns ;
-; N/A ; 69.59 MHz ( period = 14.369 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 14.108 ns ;
-; N/A ; 69.59 MHz ( period = 14.369 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[12] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 14.108 ns ;
-; N/A ; 70.14 MHz ( period = 14.258 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.997 ns ;
-; N/A ; 70.14 MHz ( period = 14.258 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.997 ns ;
-; N/A ; 70.48 MHz ( period = 14.189 ns ) ; execute_stage:exec_st|reg.result[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.928 ns ;
-; N/A ; 70.48 MHz ( period = 14.189 ns ) ; execute_stage:exec_st|reg.result[7] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.928 ns ;
-; N/A ; 70.55 MHz ( period = 14.175 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.905 ns ;
-; N/A ; 70.55 MHz ( period = 14.175 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[1] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.905 ns ;
-; N/A ; 70.55 MHz ( period = 14.174 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.846 ns ;
-; N/A ; 70.64 MHz ( period = 14.156 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.828 ns ;
-; N/A ; 70.77 MHz ( period = 14.130 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 13.860 ns ;
-; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
-; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
-; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
-; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
-; N/A ; 70.92 MHz ( period = 14.101 ns ) ; execute_stage:exec_st|reg.result[9] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 13.840 ns ;
-; N/A ; 70.95 MHz ( period = 14.094 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.757 ns ;
-; N/A ; 71.06 MHz ( period = 14.072 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[5] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.811 ns ;
-; N/A ; 71.06 MHz ( period = 14.072 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[5] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.811 ns ;
-; N/A ; 71.13 MHz ( period = 14.059 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[7] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 13.798 ns ;
-; N/A ; 71.71 MHz ( period = 13.945 ns ) ; decode_stage:decode_st|rtw_rec.immediate[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.608 ns ;
-; N/A ; 71.73 MHz ( period = 13.942 ns ) ; decode_stage:decode_st|rtw_rec.immediate[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.681 ns ;
-; N/A ; 71.73 MHz ( period = 13.942 ns ) ; decode_stage:decode_st|rtw_rec.immediate[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.681 ns ;
-; N/A ; 71.75 MHz ( period = 13.938 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.677 ns ;
-; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
-; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
-; N/A ; 71.95 MHz ( period = 13.898 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.128 ns ;
-; N/A ; 72.07 MHz ( period = 13.875 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[10] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.614 ns ;
-; N/A ; 72.07 MHz ( period = 13.875 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[10] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.614 ns ;
-; N/A ; 72.10 MHz ( period = 13.869 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.541 ns ;
-; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
-; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
-; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
-; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
-; N/A ; 72.12 MHz ( period = 13.865 ns ) ; execute_stage:exec_st|reg.result[6] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 13.671 ns ;
-; N/A ; 72.14 MHz ( period = 13.861 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[8] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 13.533 ns ;
-; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
-; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
-; N/A ; 72.18 MHz ( period = 13.855 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[26] ; sys_clk ; sys_clk ; None ; None ; 13.094 ns ;
-; N/A ; 72.33 MHz ( period = 13.826 ns ) ; decode_stage:decode_st|dec_op_inst.displacement[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 13.489 ns ;
-; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
-; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
-; N/A ; 72.35 MHz ( period = 13.821 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 13.118 ns ;
-; N/A ; 72.47 MHz ( period = 13.799 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[13] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 13.529 ns ;
-; N/A ; 72.47 MHz ( period = 13.799 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg[13] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 13.529 ns ;
-; N/A ; 72.48 MHz ( period = 13.796 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[29] ; sys_clk ; sys_clk ; None ; None ; 13.093 ns ;
-; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
-; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
-; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
-; N/A ; 72.48 MHz ( period = 13.796 ns ) ; execute_stage:exec_st|reg.result[3] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 13.535 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 46.92 MHz ( period = 21.311 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.617 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 47.00 MHz ( period = 21.278 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.584 ns ;
+; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
+; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
+; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
+; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
+; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
+; N/A ; 48.16 MHz ( period = 20.764 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.129 ns ;
+; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
+; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
+; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
+; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
+; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
+; N/A ; 48.24 MHz ( period = 20.731 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 20.096 ns ;
+; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
+; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
+; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
+; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
+; N/A ; 48.50 MHz ( period = 20.620 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.300 ns ;
+; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
+; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
+; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
+; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
+; N/A ; 48.64 MHz ( period = 20.559 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.307 ns ;
+; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
+; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
+; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
+; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
+; N/A ; 48.82 MHz ( period = 20.485 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.224 ns ;
+; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
+; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
+; N/A ; 48.85 MHz ( period = 20.472 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.778 ns ;
+; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
+; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
+; N/A ; 48.93 MHz ( period = 20.439 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.745 ns ;
+; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
+; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
+; N/A ; 49.16 MHz ( period = 20.340 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.705 ns ;
+; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
+; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
+; N/A ; 49.24 MHz ( period = 20.307 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.672 ns ;
+; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
+; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
+; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
+; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
+; N/A ; 49.30 MHz ( period = 20.286 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.025 ns ;
+; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
+; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
+; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
+; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
+; N/A ; 49.35 MHz ( period = 20.265 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 20.004 ns ;
+; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
+; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
+; N/A ; 49.72 MHz ( period = 20.112 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.418 ns ;
+; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
+; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
+; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
+; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
+; N/A ; 49.75 MHz ( period = 20.100 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.839 ns ;
+; N/A ; 49.82 MHz ( period = 20.073 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.812 ns ;
+; N/A ; 49.82 MHz ( period = 20.073 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.812 ns ;
+; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
+; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
+; N/A ; 49.97 MHz ( period = 20.014 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.320 ns ;
+; N/A ; 49.97 MHz ( period = 20.012 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.819 ns ;
+; N/A ; 49.97 MHz ( period = 20.012 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.819 ns ;
+; N/A ; 49.98 MHz ( period = 20.008 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.688 ns ;
+; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
+; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
+; N/A ; 50.12 MHz ( period = 19.952 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.258 ns ;
+; N/A ; 50.16 MHz ( period = 19.938 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.736 ns ;
+; N/A ; 50.16 MHz ( period = 19.938 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.736 ns ;
+; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
+; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
+; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
+; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
+; N/A ; 50.54 MHz ( period = 19.786 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.525 ns ;
+; N/A ; 50.55 MHz ( period = 19.781 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.461 ns ;
+; N/A ; 50.66 MHz ( period = 19.739 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.537 ns ;
+; N/A ; 50.66 MHz ( period = 19.739 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.537 ns ;
+; N/A ; 50.71 MHz ( period = 19.720 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.468 ns ;
+; N/A ; 50.72 MHz ( period = 19.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.516 ns ;
+; N/A ; 50.72 MHz ( period = 19.718 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.516 ns ;
+; N/A ; 50.74 MHz ( period = 19.709 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.457 ns ;
+; N/A ; 50.89 MHz ( period = 19.649 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.388 ns ;
+; N/A ; 50.90 MHz ( period = 19.646 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.385 ns ;
+; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
+; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
+; N/A ; 51.01 MHz ( period = 19.603 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.909 ns ;
+; N/A ; 51.03 MHz ( period = 19.597 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 19.277 ns ;
+; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
+; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
+; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
+; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
+; N/A ; 51.05 MHz ( period = 19.589 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.337 ns ;
+; N/A ; 51.05 MHz ( period = 19.588 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.395 ns ;
+; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
+; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
+; N/A ; 51.06 MHz ( period = 19.585 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.950 ns ;
+; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
+; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
+; N/A ; 51.14 MHz ( period = 19.556 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.862 ns ;
+; N/A ; 51.14 MHz ( period = 19.553 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.351 ns ;
+; N/A ; 51.14 MHz ( period = 19.553 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.351 ns ;
+; N/A ; 51.15 MHz ( period = 19.550 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 19.230 ns ;
+; N/A ; 51.25 MHz ( period = 19.514 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.312 ns ;
+; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
+; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
+; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
+; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
+; N/A ; 51.31 MHz ( period = 19.489 ns ) ; decode_stage:decode_st|dec_op_inst.saddr2[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.228 ns ;
+; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
+; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
+; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
+; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
+; N/A ; 51.32 MHz ( period = 19.484 ns ) ; decode_stage:decode_st|dec_op_inst.saddr1[2] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 19.232 ns ;
+; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
+; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
+; N/A ; 51.36 MHz ( period = 19.471 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.777 ns ;
+; N/A ; 51.37 MHz ( period = 19.465 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 19.145 ns ;
+; N/A ; 51.42 MHz ( period = 19.447 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.186 ns ;
+; N/A ; 51.45 MHz ( period = 19.436 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.175 ns ;
+; N/A ; 51.48 MHz ( period = 19.426 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.165 ns ;
+; N/A ; 51.51 MHz ( period = 19.415 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 19.154 ns ;
+; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
+; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
+; N/A ; 51.70 MHz ( period = 19.343 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.649 ns ;
+; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
+; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
+; N/A ; 51.75 MHz ( period = 19.324 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.630 ns ;
+; N/A ; 51.77 MHz ( period = 19.315 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.113 ns ;
+; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
+; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
+; N/A ; 51.79 MHz ( period = 19.310 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; None ; None ; 18.616 ns ;
+; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
+; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
+; N/A ; 51.81 MHz ( period = 19.300 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[23] ; sys_clk ; sys_clk ; None ; None ; 18.606 ns ;
+; N/A ; 51.82 MHz ( period = 19.298 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 19.046 ns ;
+; N/A ; 51.83 MHz ( period = 19.294 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 19.092 ns ;
+; N/A ; 51.92 MHz ( period = 19.261 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ; sys_clk ; None ; None ; 19.000 ns ;
+; N/A ; 51.95 MHz ( period = 19.251 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[9] ; sys_clk ; sys_clk ; None ; None ; 18.999 ns ;
+; N/A ; 51.95 MHz ( period = 19.250 ns ) ; execute_stage:exec_st|reg.alu_jump ; execute_stage:exec_st|reg.result[20] ; sys_clk ; sys_clk ; None ; None ; 18.989 ns ;
+; N/A ; 51.98 MHz ( period = 19.239 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 19.037 ns ;
+; N/A ; 51.98 MHz ( period = 19.239 ns ) ; execute_stage:exec_st|reg.wr_en ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 19.037 ns ;
+; N/A ; 52.18 MHz ( period = 19.166 ns ) ; execute_stage:exec_st|reg.res_addr[2] ; execute_stage:exec_st|reg.result[2] ; sys_clk ; sys_clk ; None ; None ; 18.914 ns ;
+; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
+; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
+; N/A ; 52.21 MHz ( period = 19.155 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.461 ns ;
+; N/A ; 52.28 MHz ( period = 19.129 ns ) ; execute_stage:exec_st|reg.alu_jump ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ; sys_clk ; None ; None ; 18.927 ns ;
+; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
+; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
+; N/A ; 52.35 MHz ( period = 19.104 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.469 ns ;
+; N/A ; 52.36 MHz ( period = 19.098 ns ) ; decode_stage:decode_st|rtw_rec.rtw_reg2 ; execute_stage:exec_st|reg.result[6] ; sys_clk ; sys_clk ; None ; None ; 18.837 ns ;
+; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
+; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
+; N/A ; 52.44 MHz ( period = 19.071 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[1] ; sys_clk ; sys_clk ; None ; None ; 18.377 ns ;
+; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
+; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
+; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
+; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
+; N/A ; 52.49 MHz ( period = 19.051 ns ) ; execute_stage:exec_st|reg.result[15] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ; sys_clk ; None ; None ; 18.790 ns ;
+; N/A ; 52.52 MHz ( period = 19.042 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ; sys_clk ; None ; None ; 18.849 ns ;
+; N/A ; 52.52 MHz ( period = 19.042 ns ) ; execute_stage:exec_st|reg.result[26] ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ; sys_clk ; None ; None ; 18.849 ns ;
+; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
+; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
+; N/A ; 52.55 MHz ( period = 19.031 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[27] ; sys_clk ; sys_clk ; None ; None ; 18.337 ns ;
+; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
+; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
+; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2 ; execute_stage:exec_st|reg.result[24] ; sys_clk ; sys_clk ; None ; None ; 18.331 ns ;
+; N/A ; 52.56 MHz ( period = 19.025 ns ) ; decode_stage:decode_st|rtw_rec.imm_set ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.764 ns ;
+; N/A ; 52.62 MHz ( period = 19.004 ns ) ; writeback_stage:writeback_st|wb_reg.dmem_en ; execute_stage:exec_st|reg.result[31] ; sys_clk ; sys_clk ; None ; None ; 18.743 ns ;
+; N/A ; 52.62 MHz ( period = 19.003 ns ) ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg1 ; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; sys_clk ; sys_clk ; None ; None ; 18.309 ns ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
++---------------------------------------------------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+---------+------------------------------------------------------------------+----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+---------+------------------------------------------------------------------+----------+
+; N/A ; None ; 16.692 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
+; N/A ; None ; 16.689 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
+; N/A ; None ; 16.688 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
+; N/A ; None ; 16.686 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[15] ; sys_clk ;
+; N/A ; None ; 16.684 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
+; N/A ; None ; 16.683 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
+; N/A ; None ; 16.681 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
+; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
+; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
+; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
+; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
+; N/A ; None ; 15.220 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
+; N/A ; None ; 14.759 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
+; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
+; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
+; N/A ; None ; 14.741 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
+; N/A ; None ; 14.673 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
+; N/A ; None ; 14.673 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
+; N/A ; None ; 14.394 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
+; N/A ; None ; 14.381 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
+; N/A ; None ; 14.248 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
+; N/A ; None ; 13.957 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
+; N/A ; None ; 13.957 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
+; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
+; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
+; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
+; N/A ; None ; 13.781 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
+; N/A ; None ; 13.742 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
+; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
+; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
+; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
+; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
+; N/A ; None ; 13.717 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
+; N/A ; None ; 13.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
+; N/A ; None ; 13.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
+; N/A ; None ; 13.375 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
+; N/A ; None ; 13.265 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
+; N/A ; None ; 13.205 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
+; N/A ; None ; 13.126 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
+; N/A ; None ; 13.126 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
+; N/A ; None ; 12.974 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
+; N/A ; None ; 12.974 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
+; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
+; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
+; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
+; N/A ; None ; 12.948 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
+; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
+; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
+; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
+; N/A ; None ; 12.942 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
+; N/A ; None ; 12.849 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
+; N/A ; None ; 12.769 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
+; N/A ; None ; 12.542 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
+; N/A ; None ; 12.384 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
+; N/A ; None ; 12.380 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
+; N/A ; None ; 12.255 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
+; N/A ; None ; 12.236 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
+; N/A ; None ; 12.158 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
+; N/A ; None ; 12.154 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
+; N/A ; None ; 12.149 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
+; N/A ; None ; 12.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
+; N/A ; None ; 12.123 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
+; N/A ; None ; 12.033 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
+; N/A ; None ; 12.027 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
+; N/A ; None ; 11.977 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
+; N/A ; None ; 11.927 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
+; N/A ; None ; 11.914 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
+; N/A ; None ; 11.890 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
+; N/A ; None ; 11.889 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
+; N/A ; None ; 11.881 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
+; N/A ; None ; 11.764 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
+; N/A ; None ; 11.700 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
+; N/A ; None ; 11.660 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
+; N/A ; None ; 11.555 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
+; N/A ; None ; 11.555 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
+; N/A ; None ; 11.537 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
+; N/A ; None ; 11.535 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
+; N/A ; None ; 11.318 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
+; N/A ; None ; 11.315 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
+; N/A ; None ; 11.255 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
+; N/A ; None ; 11.184 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
+; N/A ; None ; 11.144 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
+; N/A ; None ; 11.127 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
+; N/A ; None ; 11.007 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
+; N/A ; None ; 10.999 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
+; N/A ; None ; 10.955 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
+; N/A ; None ; 10.830 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
+; N/A ; None ; 10.734 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
+; N/A ; None ; 10.714 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
+; N/A ; None ; 10.601 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
+; N/A ; None ; 10.573 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
+; N/A ; None ; 10.408 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
+; N/A ; None ; 10.117 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
+; N/A ; None ; 9.756 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
++-------+--------------+------------+---------+------------------------------------------------------------------+----------+
+
+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
-; N/A ; None ; 8.846 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
+; N/A ; None ; 8.362 ns ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; bus_tx ; sys_clk ;
+-------+--------------+------------+------------------------------------------------------------------------------------+--------+------------+
++----------------------------------------------------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
+; N/A ; None ; -8.416 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ;
+; N/A ; None ; -9.704 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; sys_clk ;
+; N/A ; None ; -10.065 ns ; sys_res ; execute_stage:exec_st|reg.result[31] ; sys_clk ;
+; N/A ; None ; -10.356 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[4] ; sys_clk ;
+; N/A ; None ; -10.521 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[6] ; sys_clk ;
+; N/A ; None ; -10.549 ns ; sys_res ; execute_stage:exec_st|reg.result[24] ; sys_clk ;
+; N/A ; None ; -10.662 ns ; sys_res ; execute_stage:exec_st|reg.result[14] ; sys_clk ;
+; N/A ; None ; -10.682 ns ; sys_res ; execute_stage:exec_st|reg.result[18] ; sys_clk ;
+; N/A ; None ; -10.778 ns ; sys_res ; execute_stage:exec_st|reg.result[19] ; sys_clk ;
+; N/A ; None ; -10.903 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[9] ; sys_clk ;
+; N/A ; None ; -10.947 ns ; sys_res ; execute_stage:exec_st|reg.result[5] ; sys_clk ;
+; N/A ; None ; -10.955 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[7] ; sys_clk ;
+; N/A ; None ; -11.075 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[3] ; sys_clk ;
+; N/A ; None ; -11.092 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[1] ; sys_clk ;
+; N/A ; None ; -11.132 ns ; sys_res ; execute_stage:exec_st|reg.result[12] ; sys_clk ;
+; N/A ; None ; -11.203 ns ; sys_res ; execute_stage:exec_st|reg.alu_jump ; sys_clk ;
+; N/A ; None ; -11.263 ns ; sys_res ; execute_stage:exec_st|reg.result[26] ; sys_clk ;
+; N/A ; None ; -11.266 ns ; sys_res ; execute_stage:exec_st|reg.result[22] ; sys_clk ;
+; N/A ; None ; -11.483 ns ; sys_res ; execute_stage:exec_st|reg.wr_en ; sys_clk ;
+; N/A ; None ; -11.485 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_en ; sys_clk ;
+; N/A ; None ; -11.503 ns ; sys_res ; execute_stage:exec_st|reg.result[23] ; sys_clk ;
+; N/A ; None ; -11.503 ns ; sys_res ; execute_stage:exec_st|reg.result[27] ; sys_clk ;
+; N/A ; None ; -11.608 ns ; sys_res ; execute_stage:exec_st|reg.result[10] ; sys_clk ;
+; N/A ; None ; -11.648 ns ; sys_res ; execute_stage:exec_st|reg.result[0] ; sys_clk ;
+; N/A ; None ; -11.662 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; sys_clk ;
+; N/A ; None ; -11.662 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[15] ; sys_clk ;
+; N/A ; None ; -11.663 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ; sys_clk ;
+; N/A ; None ; -11.664 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; sys_clk ;
+; N/A ; None ; -11.665 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; sys_clk ;
+; N/A ; None ; -11.712 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[5] ; sys_clk ;
+; N/A ; None ; -11.829 ns ; sys_res ; execute_stage:exec_st|reg.result[17] ; sys_clk ;
+; N/A ; None ; -11.837 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[8] ; sys_clk ;
+; N/A ; None ; -11.838 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ;
+; N/A ; None ; -11.862 ns ; sys_res ; execute_stage:exec_st|reg.result[8] ; sys_clk ;
+; N/A ; None ; -11.875 ns ; sys_res ; execute_stage:exec_st|reg.result[20] ; sys_clk ;
+; N/A ; None ; -11.925 ns ; sys_res ; execute_stage:exec_st|reg.result[16] ; sys_clk ;
+; N/A ; None ; -11.975 ns ; sys_res ; execute_stage:exec_st|reg.result[4] ; sys_clk ;
+; N/A ; None ; -11.981 ns ; sys_res ; execute_stage:exec_st|reg.result[21] ; sys_clk ;
+; N/A ; None ; -12.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ;
+; N/A ; None ; -12.071 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; sys_clk ;
+; N/A ; None ; -12.097 ns ; sys_res ; execute_stage:exec_st|reg.result[28] ; sys_clk ;
+; N/A ; None ; -12.102 ns ; sys_res ; execute_stage:exec_st|reg.result[15] ; sys_clk ;
+; N/A ; None ; -12.106 ns ; sys_res ; execute_stage:exec_st|reg.result[13] ; sys_clk ;
+; N/A ; None ; -12.184 ns ; sys_res ; execute_stage:exec_st|reg.result[29] ; sys_clk ;
+; N/A ; None ; -12.203 ns ; sys_res ; execute_stage:exec_st|reg.result[9] ; sys_clk ;
+; N/A ; None ; -12.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; sys_clk ;
+; N/A ; None ; -12.332 ns ; sys_res ; execute_stage:exec_st|reg.result[11] ; sys_clk ;
+; N/A ; None ; -12.490 ns ; sys_res ; execute_stage:exec_st|reg.result[7] ; sys_clk ;
+; N/A ; None ; -12.717 ns ; sys_res ; writeback_stage:writeback_st|wb_reg.dmem_write_en ; sys_clk ;
+; N/A ; None ; -12.797 ns ; sys_res ; execute_stage:exec_st|reg.result[25] ; sys_clk ;
+; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; sys_clk ;
+; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; sys_clk ;
+; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; sys_clk ;
+; N/A ; None ; -12.890 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; sys_clk ;
+; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; sys_clk ;
+; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; sys_clk ;
+; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; sys_clk ;
+; N/A ; None ; -12.896 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; sys_clk ;
+; N/A ; None ; -12.922 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; sys_clk ;
+; N/A ; None ; -12.922 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; sys_clk ;
+; N/A ; None ; -12.945 ns ; sys_res ; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; sys_clk ;
+; N/A ; None ; -13.074 ns ; sys_res ; execute_stage:exec_st|reg.result[3] ; sys_clk ;
+; N/A ; None ; -13.074 ns ; sys_res ; execute_stage:exec_st|reg.result[6] ; sys_clk ;
+; N/A ; None ; -13.213 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[2] ; sys_clk ;
+; N/A ; None ; -13.323 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; sys_clk ;
+; N/A ; None ; -13.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; sys_clk ;
+; N/A ; None ; -13.328 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; sys_clk ;
+; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; sys_clk ;
+; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; sys_clk ;
+; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; sys_clk ;
+; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; sys_clk ;
+; N/A ; None ; -13.665 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; sys_clk ;
+; N/A ; None ; -13.690 ns ; sys_res ; execute_stage:exec_st|reg.result[30] ; sys_clk ;
+; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; sys_clk ;
+; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; sys_clk ;
+; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; sys_clk ;
+; N/A ; None ; -13.729 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; sys_clk ;
+; N/A ; None ; -13.905 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; sys_clk ;
+; N/A ; None ; -13.905 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; sys_clk ;
+; N/A ; None ; -14.196 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; sys_clk ;
+; N/A ; None ; -14.329 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; sys_clk ;
+; N/A ; None ; -14.342 ns ; sys_res ; fetch_stage:fetch_st|instr_r_addr[0] ; sys_clk ;
+; N/A ; None ; -14.363 ns ; sys_res ; execute_stage:exec_st|reg.result[1] ; sys_clk ;
+; N/A ; None ; -14.621 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; sys_clk ;
+; N/A ; None ; -14.621 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; sys_clk ;
+; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; sys_clk ;
+; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; sys_clk ;
+; N/A ; None ; -14.689 ns ; sys_res ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; sys_clk ;
+; N/A ; None ; -15.078 ns ; sys_res ; execute_stage:exec_st|reg.result[2] ; sys_clk ;
+; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; sys_clk ;
+; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; sys_clk ;
+; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; sys_clk ;
+; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; sys_clk ;
+; N/A ; None ; -15.168 ns ; sys_res ; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; sys_clk ;
++---------------+-------------+------------+---------+------------------------------------------------------------------+----------+
+
+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Thu Dec 16 16:55:05 2010
+ Info: Processing started: Fri Dec 17 10:10:41 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dt -c dt --timing_analysis_only
Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "sys_clk" is an undefined clock
-Info: Clock "sys_clk" has Internal fmax of 49.7 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]" (period= 20.119 ns)
- Info: + Longest memory to register delay is 19.416 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y16; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a9'
- Info: 3: + IC(1.893 ns) + CELL(0.114 ns) = 6.324 ns; Loc. = LC_X27_Y12_N5; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[9]~23'
- Info: 4: + IC(0.416 ns) + CELL(0.114 ns) = 6.854 ns; Loc. = LC_X27_Y12_N2; Fanout = 6; COMB Node = 'execute_stage:exec_st|left_operand[9]~24'
- Info: 5: + IC(1.990 ns) + CELL(0.564 ns) = 9.408 ns; Loc. = LC_X28_Y13_N3; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~52'
- Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 9.586 ns; Loc. = LC_X28_Y13_N4; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~57'
- Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 9.794 ns; Loc. = LC_X28_Y13_N9; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~77'
- Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 10.473 ns; Loc. = LC_X28_Y12_N2; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~90'
- Info: 9: + IC(1.498 ns) + CELL(0.114 ns) = 12.085 ns; Loc. = LC_X32_Y12_N1; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~14'
- Info: 10: + IC(0.428 ns) + CELL(0.590 ns) = 13.103 ns; Loc. = LC_X32_Y12_N2; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~17'
- Info: 11: + IC(1.142 ns) + CELL(0.590 ns) = 14.835 ns; Loc. = LC_X29_Y12_N8; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~23'
- Info: 12: + IC(1.556 ns) + CELL(0.114 ns) = 16.505 ns; Loc. = LC_X28_Y11_N8; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1'
- Info: 13: + IC(2.044 ns) + CELL(0.867 ns) = 19.416 ns; Loc. = LC_X36_Y14_N5; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
- Info: Total cell delay = 8.449 ns ( 43.52 % )
- Info: Total interconnect delay = 10.967 ns ( 56.48 % )
- Info: - Smallest clock skew is -0.016 ns
- Info: + Shortest clock path from clock "sys_clk" to destination register is 3.178 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
- Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X36_Y14_N5; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
- Info: Total cell delay = 2.180 ns ( 68.60 % )
- Info: Total interconnect delay = 0.998 ns ( 31.40 % )
+Info: Clock "sys_clk" has Internal fmax of 46.92 MHz between source memory "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0" and destination register "writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]" (period= 21.311 ns)
+ Info: + Longest memory to register delay is 20.617 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0'
+ Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a1'
+ Info: 3: + IC(1.103 ns) + CELL(0.114 ns) = 5.534 ns; Loc. = LC_X31_Y18_N3; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[1]~3'
+ Info: 4: + IC(0.437 ns) + CELL(0.114 ns) = 6.085 ns; Loc. = LC_X31_Y18_N2; Fanout = 5; COMB Node = 'execute_stage:exec_st|left_operand[1]~4'
+ Info: 5: + IC(1.249 ns) + CELL(0.114 ns) = 7.448 ns; Loc. = LC_X31_Y22_N0; Fanout = 9; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector106~0'
+ Info: 6: + IC(0.410 ns) + CELL(0.432 ns) = 8.290 ns; Loc. = LC_X31_Y22_N5; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~152COUT1_192'
+ Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 8.370 ns; Loc. = LC_X31_Y22_N6; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~147COUT1_194'
+ Info: 8: + IC(0.000 ns) + CELL(0.608 ns) = 8.978 ns; Loc. = LC_X31_Y22_N7; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~0'
+ Info: 9: + IC(0.728 ns) + CELL(0.575 ns) = 10.281 ns; Loc. = LC_X30_Y22_N7; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[3]~2COUT1_191'
+ Info: 10: + IC(0.000 ns) + CELL(0.608 ns) = 10.889 ns; Loc. = LC_X30_Y22_N8; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[4]~10'
+ Info: 11: + IC(1.603 ns) + CELL(0.114 ns) = 12.606 ns; Loc. = LC_X32_Y21_N2; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector70~0'
+ Info: 12: + IC(1.282 ns) + CELL(0.292 ns) = 14.180 ns; Loc. = LC_X31_Y17_N0; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector70~1'
+ Info: 13: + IC(0.418 ns) + CELL(0.114 ns) = 14.712 ns; Loc. = LC_X31_Y17_N5; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~0'
+ Info: 14: + IC(0.727 ns) + CELL(0.292 ns) = 15.731 ns; Loc. = LC_X30_Y17_N6; Fanout = 7; COMB Node = 'writeback_stage:writeback_st|Equal0~5'
+ Info: 15: + IC(1.590 ns) + CELL(0.292 ns) = 17.613 ns; Loc. = LC_X27_Y19_N2; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
+ Info: 16: + IC(0.182 ns) + CELL(0.114 ns) = 17.909 ns; Loc. = LC_X27_Y19_N3; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~12'
+ Info: 17: + IC(0.431 ns) + CELL(0.114 ns) = 18.454 ns; Loc. = LC_X27_Y19_N6; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
+ Info: 18: + IC(1.296 ns) + CELL(0.867 ns) = 20.617 ns; Loc. = LC_X28_Y21_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
+ Info: Total cell delay = 9.161 ns ( 44.43 % )
+ Info: Total interconnect delay = 11.456 ns ( 55.57 % )
+ Info: - Smallest clock skew is -0.007 ns
+ Info: + Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X28_Y21_N7; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
+ Info: Total cell delay = 2.180 ns ( 68.40 % )
+ Info: Total interconnect delay = 1.007 ns ( 31.60 % )
Info: - Longest clock path from clock "sys_clk" to source memory is 3.194 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
- Info: 2: + IC(1.007 ns) + CELL(0.718 ns) = 3.194 ns; Loc. = M4K_X33_Y16; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0'
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.007 ns) + CELL(0.718 ns) = 3.194 ns; Loc. = M4K_X33_Y18; Fanout = 32; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg0'
Info: Total cell delay = 2.187 ns ( 68.47 % )
Info: Total interconnect delay = 1.007 ns ( 31.53 % )
Info: + Micro clock to output delay of source is 0.650 ns
Info: + Micro setup delay of destination is 0.037 ns
-Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 8.846 ns
- Info: + Longest clock path from clock "sys_clk" to source register is 3.178 ns
- Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 283; CLK Node = 'sys_clk'
- Info: 2: + IC(0.998 ns) + CELL(0.711 ns) = 3.178 ns; Loc. = LC_X36_Y14_N2; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
- Info: Total cell delay = 2.180 ns ( 68.60 % )
- Info: Total interconnect delay = 0.998 ns ( 31.40 % )
+Info: tsu for register "execute_stage:exec_st|reg.result[2]" (data pin = "sys_res", clock pin = "sys_clk") is 16.692 ns
+ Info: + Longest pin to register delay is 19.842 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
+ Info: 2: + IC(9.460 ns) + CELL(0.292 ns) = 11.221 ns; Loc. = LC_X37_Y17_N4; Fanout = 7; COMB Node = 'execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0'
+ Info: 3: + IC(0.771 ns) + CELL(0.114 ns) = 12.106 ns; Loc. = LC_X36_Y17_N6; Fanout = 32; COMB Node = 'execute_stage:exec_st|alu:alu_inst|calc~0'
+ Info: 4: + IC(2.560 ns) + CELL(0.114 ns) = 14.780 ns; Loc. = LC_X27_Y16_N7; Fanout = 3; COMB Node = 'execute_stage:exec_st|reg.result[1]~19'
+ Info: 5: + IC(2.407 ns) + CELL(0.442 ns) = 17.629 ns; Loc. = LC_X27_Y22_N4; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|alu_result.result[2]~8'
+ Info: 6: + IC(1.606 ns) + CELL(0.607 ns) = 19.842 ns; Loc. = LC_X32_Y22_N2; Fanout = 2; REG Node = 'execute_stage:exec_st|reg.result[2]'
+ Info: Total cell delay = 3.038 ns ( 15.31 % )
+ Info: Total interconnect delay = 16.804 ns ( 84.69 % )
+ Info: + Micro setup delay of destination is 0.037 ns
+ Info: - Shortest clock path from clock "sys_clk" to destination register is 3.187 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X32_Y22_N2; Fanout = 2; REG Node = 'execute_stage:exec_st|reg.result[2]'
+ Info: Total cell delay = 2.180 ns ( 68.40 % )
+ Info: Total interconnect delay = 1.007 ns ( 31.60 % )
+Info: tco from clock "sys_clk" to destination pin "bus_tx" through register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int" is 8.362 ns
+ Info: + Longest clock path from clock "sys_clk" to source register is 3.187 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X40_Y20_N8; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
+ Info: Total cell delay = 2.180 ns ( 68.40 % )
+ Info: Total interconnect delay = 1.007 ns ( 31.60 % )
Info: + Micro clock to output delay of source is 0.224 ns
- Info: + Longest register to pin delay is 5.444 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y14_N2; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
- Info: 2: + IC(3.320 ns) + CELL(2.124 ns) = 5.444 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
- Info: Total cell delay = 2.124 ns ( 39.02 % )
- Info: Total interconnect delay = 3.320 ns ( 60.98 % )
+ Info: + Longest register to pin delay is 4.951 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X40_Y20_N8; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int'
+ Info: 2: + IC(2.827 ns) + CELL(2.124 ns) = 4.951 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'bus_tx'
+ Info: Total cell delay = 2.124 ns ( 42.90 % )
+ Info: Total interconnect delay = 2.827 ns ( 57.10 % )
+Info: th for register "writeback_stage:writeback_st|extension_uart:uart|new_tx_data" (data pin = "sys_res", clock pin = "sys_clk") is -8.416 ns
+ Info: + Longest clock path from clock "sys_clk" to destination register is 3.187 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 357; CLK Node = 'sys_clk'
+ Info: 2: + IC(1.007 ns) + CELL(0.711 ns) = 3.187 ns; Loc. = LC_X27_Y19_N6; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|new_tx_data'
+ Info: Total cell delay = 2.180 ns ( 68.40 % )
+ Info: Total interconnect delay = 1.007 ns ( 31.60 % )
+ Info: + Micro hold delay of destination is 0.015 ns
+ Info: - Shortest pin to register delay is 11.618 ns
+ Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 205; PIN Node = 'sys_res'
+ Info: 2: + IC(9.282 ns) + CELL(0.867 ns) = 11.618 ns; Loc. = LC_X27_Y19_N6; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|new_tx_data'
+ Info: Total cell delay = 2.336 ns ( 20.11 % )
+ Info: Total interconnect delay = 9.282 ns ( 79.89 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 187 megabytes
- Info: Processing ended: Thu Dec 16 16:55:06 2010
+ Info: Peak virtual memory: 189 megabytes
+ Info: Processing ended: Fri Dec 17 10:10:42 2010
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Timing Analyzer Summary
--------------------------------------------------------------------------------------
+Type : Worst-case tsu
+Slack : N/A
+Required Time : None
+Actual Time : 16.692 ns
+From : sys_res
+To : execute_stage:exec_st|reg.result[2]
+From Clock : --
+To Clock : sys_clk
+Failed Paths : 0
+
Type : Worst-case tco
Slack : N/A
Required Time : None
-Actual Time : 8.846 ns
+Actual Time : 8.362 ns
From : writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int
To : bus_tx
From Clock : sys_clk
To Clock : --
Failed Paths : 0
+Type : Worst-case th
+Slack : N/A
+Required Time : None
+Actual Time : -8.416 ns
+From : sys_res
+To : writeback_stage:writeback_st|extension_uart:uart|new_tx_data
+From Clock : --
+To Clock : sys_clk
+Failed Paths : 0
+
Type : Clock Setup: 'sys_clk'
Slack : N/A
Required Time : None
-Actual Time : 49.70 MHz ( period = 20.119 ns )
-From : decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2
+Actual Time : 46.92 MHz ( period = 21.311 ns )
+From : decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a0~portb_address_reg2
To : writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4]
From Clock : sys_clk
To Clock : sys_clk
projects / calu.git / commitdiff