interrupt version 1
[calu.git] / cpu / sim / testcore.do
2010-12-24 Stefan Reberniginterrupt version 1
2010-12-21 Stefan Rebernigadded byte enable, tested ldi, ldb, stb
2010-12-20 Stefan Rebernigstack op
2010-12-19 Stefan Reberniguart und extension anbindung
2010-12-19 Stefan Rebernigmodelsim lauffähig
2010-12-17 Stefan Reberniginstr mem durch case, fibonacci als programm, 7seg...
2010-12-17 Stefan REBERNIGwriteback_stage: differenzieren zwischen memory und...
2010-12-17 Stefan REBERNIGuart: blinkt zwar nur am led aber des is schon net...
2010-12-11 Stefan Rebernigfibonacci tested rc1, 107 cycles, 1k2le, 57MHz
2010-12-11 Stefan Rebernigfib 1
2010-12-11 Stefan Rebernigcall/return
2010-12-11 U-Thor\Schakalbugfix: sp operation first approach.
2010-12-01 Stefan Rebernigstatic branch incl prediction rc1
2010-12-01 Manfredextension : gpm extension
2010-11-30 Manfredextension: instanziert in tb und toplvlentity sowie...
2010-11-16 Stefan Rebernig2nd forward unit - 58MHz with 31bit shift...
2010-11-15 Stefan Rebernigtest pipe 2
2010-11-15 Stefan Rebernigpipe v1
2010-11-15 Markus HofstätterFixed some bugs.
2010-11-15 Markus HofstätterMerge branch 'master' of wien.tomnetworks.com:calu
2010-11-15 Stefanadded pipe 2 reg, testbench, top_level_entity, ...
2010-11-14 Stefando file for testbench - a few test instructions added...