interrupt version 1

diff --git a/cpu/sim/testcore.do b/cpu/sim/testcore.do
index 1951c5f20c0e87f4227ff65102623a4b22cbc0ad..d847d8372e6282bd677d0d7256b67f274c730db2 100644 (file)
--- a/cpu/sim/testcore.do
+++ b/cpu/sim/testcore.do
@@ -16,6 +16,8 @@ vcom -work work ../src/core_pkg.vhd
 vcom -work work ../src/extension_uart_pkg.vhd
 vcom -work work ../src/extension_uart.vhd
 vcom -work work ../src/extension_uart_b.vhd
+vcom -work work ../src/extension_interrupt.vhd
+vcom -work work ../src/extension_interrupt_b.vhd
 vcom -work work ../src/extension_7seg_pkg.vhd
 vcom -work work ../src/extension_7seg.vhd
 vcom -work work ../src/extension_7seg_b.vhd

diff --git a/cpu/src/common_pkg.vhd b/cpu/src/common_pkg.vhd
index d111b7da6241b9698ef15d7cb092fa51364f44b3..a88336c7ec5f13f5ed8565761275a7bc2ec9be1f 100755 (executable)
--- a/cpu/src/common_pkg.vhd
+++ b/cpu/src/common_pkg.vhd
@@ -59,6 +59,7 @@ package common_pkg is
        constant HWORD_OPT : integer := 1;
        constant PUSH_OPT : integer := 1;
        constant LOW_HIGH_OPT : integer := 1;
+       constant DIRECT_JUMP_OPT : integer := 1;
        
        constant CARRY_OPT : integer := 2;
        constant BYTE_OPT : integer := 2;
@@ -74,8 +75,14 @@ package common_pkg is
        
        type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP, LDST_OP, JMP_OP, JMP_ST_OP, STACK_OP);
        subtype op_opt_t is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
+
+       type interrupt_t is (IDLE, UART);       
        
-       
+       constant UART_INT_EN_BIT : integer := 1;
+       constant GLOBAL_INT_EN_BIT : integer := 0;
+
+       constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := "00000000001"; --integer := 1;
+
        type instruction_rec is record
 
                predicates : std_logic_vector(3 downto 0);
@@ -92,7 +99,7 @@ package common_pkg is
 
                jmptype : std_logic_vector(1 downto 0);
 
-               high_low, fill, signext, bp: std_logic;
+               high_low, fill, signext, bp, int: std_logic;
 
                op_detail : op_opt_t;
                op_group : op_info_t;

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index afd50b666d4153702c1f1c91d54257f3606a4a8c..b9f9eca00e30a25ee9a2db6cd73e2fa5d2f0f355 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -26,6 +26,7 @@ package core_pkg is
                        prediction_result : in instruction_addr_t;
                        branch_prediction_bit : in std_logic;
                        alu_jump_bit : in std_logic;
+                       int_req : in interrupt_t;
 
                --Data outputs
                        instruction : out instruction_word_t;
@@ -151,7 +152,10 @@ package core_pkg is
                        sseg0 : out std_logic_vector(0 to 6);
                        sseg1 : out std_logic_vector(0 to 6);
                        sseg2 : out std_logic_vector(0 to 6);
-                       sseg3 : out std_logic_vector(0 to 6)
+                       sseg3 : out std_logic_vector(0 to 6);
+
+                       int_req : out interrupt_t
+
                );
        end component writeback_stage;
 

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index eafb605135bf9a5dcee5c06f88cfc2bb21e6b563..07da7b24afca2dc4b0a8498ff0a93a5352a8905f 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -65,6 +65,8 @@ architecture behav of core_top is
                 
                 signal sync : std_logic_vector(1 to SYNC_STAGES);
                 signal sys_res_n : std_logic;
+
+                signal int_req : interrupt_t;
                 
                 signal vers, vers_nxt : exec2wb_rec;
 begin
@@ -86,6 +88,7 @@ begin
                        prediction_result => prediction_result_pin, --: in instruction_addr_t;
                        branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+                       int_req => int_req,
 
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
@@ -148,7 +151,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3, int_req);
 
 
 syn: process(sys_clk, sys_res)

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 9bd9d8139f8a12c86d6acf56477030170d2328b4..37f6688e201885e57fb3d652cd0c097e262b7ed0 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -188,7 +188,11 @@ begin
        branch_prediction_bit <= '0';
 
        if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
-               branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt));  --both 32 bit
+               if instr_spl.int = '0' then             
+                       branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt));  --both 32 bit
+               else 
+                       branch_prediction_res <= instr_spl.immediate;
+               end if;
                branch_prediction_bit <= '1';
        end if;
 

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index d0a5070207a2c6004afad4717dd816e45fba0ba1..c51e1318ba0ee63d474a5c6799895234c3cb03a8 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -32,6 +32,7 @@ begin
        instr_s.bp := '0';
        instr_s.op_detail := (others => '0');
        instr_s.displacement := (others => '0');
+       instr_s.int := '0';
 
        instr_s.op_group := ADDSUB_OP;
 
@@ -353,7 +354,8 @@ begin
                instr_s.jmptype := instruction(3 downto 2);
                instr_s.signext := instruction(0);
                instr_s.op_detail(NO_PSW_OPT) := '1';
-               
+               instr_s.op_detail(DIRECT_JUMP_OPT) := instruction(4);
+               instr_s.int := instruction(4);
 
                if (instr_s.opcode = "10110") then
                        instr_s.op_detail(IMM_OPT) := '1';      

diff --git a/cpu/src/extension_interrupt.vhd b/cpu/src/extension_interrupt.vhd
new file mode 100644 (file)
index 0000000..84bac6f
--- /dev/null
+++ b/cpu/src/extension_interrupt.vhd
@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+
+entity extension_interrupt is
+        --some modules won't need all inputs/outputs
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic
+                       );
+       port(
+               --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+               -- general extension interface                  
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t;
+               -- Input
+                       uart_int : in std_logic;
+               -- Ouput
+                       int_req : out interrupt_t
+               );
+ end extension_interrupt;
+

diff --git a/cpu/src/extension_interrupt_b.vhd b/cpu/src/extension_interrupt_b.vhd
new file mode 100644 (file)
index 0000000..c49c3dd
--- /dev/null
+++ b/cpu/src/extension_interrupt_b.vhd
@@ -0,0 +1,133 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+
+architecture behav of extension_interrupt is
+
+signal w1_st_co, w1_st_co_nxt, w2_int_config, w2_int_config_nxt : gp_register_t;
+
+begin
+
+syn : process (clk, reset)
+begin
+   if (reset = RESET_VALUE) then
+                       w1_st_co <= (others=>'0');
+                       w2_int_config(31 downto 0) <= (others=>'0');
+                       -- todo mit einer konstante versehen
+
+       elsif rising_edge(clk) then            
+                       w1_st_co <= w1_st_co_nxt;
+                       w2_int_config <= w2_int_config_nxt;
+   end if;
+end process syn;
+
+-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
+
+gwriten : process (ext_reg,w1_st_co,w2_int_config)
+
+variable tmp_data  : gp_register_t;
+
+begin
+
+       w1_st_co_nxt <= w1_st_co;
+       w2_int_config_nxt <= w2_int_config;
+
+       if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
+               tmp_data := (others =>'0');                     
+               if ext_reg.byte_en(0) = '1' then
+                       tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
+               end if;
+               if ext_reg.byte_en(1) = '1' then
+                       tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
+               end if;
+               if ext_reg.byte_en(2) = '1' then
+                       tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
+               end if;
+               if ext_reg.byte_en(3) = '1' then
+                       tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
+               end if;
+
+               case ext_reg.addr(1 downto 0) is
+               when "00" => 
+                       w1_st_co_nxt <= tmp_data;
+               when "01" =>
+                       w2_int_config_nxt <= tmp_data;
+               when others => null;
+               end case;
+       end if;
+       
+end process gwriten;
+
+gread : process (clk,ext_reg,w1_st_co,w2_int_config)
+
+variable tmp_data  : gp_register_t;
+
+begin
+
+       if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
+               case ext_reg.addr(1 downto 0) is
+               when "00" => 
+                       tmp_data := (others =>'0');                     
+                       if ext_reg.byte_en(0) = '1' then
+                               tmp_data(byte_t'range) := w1_st_co(byte_t'range);
+                       end if;
+                       if ext_reg.byte_en(1) = '1' then
+                               tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(2) = '1' then
+                               tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(3) = '1' then
+                               tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       data_out <= tmp_data;
+               when "01" =>
+                       tmp_data := (others =>'0');                     
+                       if ext_reg.byte_en(0) = '1' then
+                               tmp_data(byte_t'range) := w2_int_config(byte_t'range);
+                       end if;
+                       if ext_reg.byte_en(1) = '1' then
+                               tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_int_config((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(2) = '1' then
+                               tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_int_config((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(3) = '1' then
+                               tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_int_config((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       data_out <= tmp_data;
+               when others => data_out <= (others => '0');
+               end case;
+       else
+               data_out  <= (others=>'0');             
+       end if;
+end process gread;
+
+
+-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
+
+-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
+
+dataprocess : process (w2_int_config, uart_int)
+
+begin
+
+       int_req <= IDLE;
+
+       if (w2_int_config(GLOBAL_INT_EN_BIT) = '1') then
+               if (w2_int_config(UART_INT_EN_BIT) = '1' and uart_int = '1') then
+                       int_req <= UART;
+               end if;
+       end if;
+
+end process dataprocess;
+
+
+
+-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
+
+end behav;
+

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
index c61266cebcea3344414de7088e0a060a344c43eb..ba3921f1c3aa0909494aad3c4ecd0b6a52072fe5 100644 (file)
--- a/cpu/src/extension_pkg.vhd
+++ b/cpu/src/extension_pkg.vhd
@@ -40,6 +40,7 @@ constant EXT_TIMER_ADDR:  ext_addrid_t := x"FFFFFFC";
 constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
 -- constant EXT_UART_ADDR:   ext_addrid_t := x"FFFFFFE";
 constant EXT_UART_ADDR:   ext_addrid_t := x"0000200";
+constant EXT_INT_ADDR:   ext_addrid_t := x"0000202";
 constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
 
 component extension_gpm is
@@ -67,6 +68,25 @@ component extension_gpm is
                );
  end component extension_gpm;
 
+component extension_interrupt is
+        --some modules won't need all inputs/outputs
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic
+                       );
+       port(
+               --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+               -- general extension interface                  
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t;
+               -- Input
+                       uart_int : in std_logic;
+               -- Ouput
+                       int_req : out interrupt_t
+               );
+ end component extension_interrupt;
 
 
 end package extension_pkg;

diff --git a/cpu/src/extension_uart.vhd b/cpu/src/extension_uart.vhd
index e928ad0c165910c80bb1a906370c9e9005989384..f5931646ca09555a8dba1bd8a4d3f90efd1df54d 100644 (file)
--- a/cpu/src/extension_uart.vhd
+++ b/cpu/src/extension_uart.vhd
@@ -20,6 +20,8 @@ entity extension_uart is
                -- general extension interface                  
                        ext_reg  : in extmod_rec;
                        data_out : out gp_register_t;
+
+                       uart_int : out std_logic;
                -- Input
                        bus_rx : in std_logic;
                -- Ouput

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 2eda02bcd7b6a8390d20386d14c472b0d4c67a82..66112759340f978bfaedab5dbe7e38e21697c0d9 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -16,6 +16,8 @@ signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, t
 signal         bd_rate : baud_rate_l;
 signal rx_data : std_logic_vector(7 downto 0);
 
+signal uart_int_nxt : std_logic;
+
 signal uart_data_read, uart_data_read_nxt : std_logic;
 
 begin
@@ -75,6 +77,7 @@ begin
                        tx_rdy_int <= '0';
                        new_tx_data <= '0';
                        uart_data_read <= '0';
+                       uart_int <= '0';
 
        elsif rising_edge(clk) then            
                        w1_st_co <= w1_st_co_nxt;
@@ -84,6 +87,7 @@ begin
                        new_tx_data <= new_tx_data_nxt;
                        tx_rdy_int <= tx_rdy;
                        uart_data_read <= uart_data_read_nxt;
+                       uart_int <= uart_int_nxt;
    end if;
 end process syn;
 
@@ -94,7 +98,7 @@ gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_r
 variable tmp_data  : gp_register_t;
 
 begin
-
+               uart_int_nxt <= '0';
                w1_st_co_nxt <= w1_st_co;
                w2_uart_config_nxt <= w2_uart_config;
                w3_uart_send_nxt <= w3_uart_send;
@@ -136,6 +140,7 @@ begin
        if new_bus_rx = '1' then
                w4_uart_receive_nxt(7 downto 0) <= rx_data;
                w1_st_co_nxt(17) <= '1';
+               uart_int_nxt <= '1';
        end if;
        
        if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index c7fd32f1093aee6af8222c5cb3e018f67256e4f7..2a4ca4b1ca2e24c187e0dfab761902dccefeab6b 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -37,6 +37,8 @@ constant CLK_PER_BAUD : integer := 434;
                -- general extension interface                  
                        ext_reg  : in extmod_rec;
                        data_out : out gp_register_t;
+
+                       uart_int : out std_logic;
                -- Input
                        bus_rx : in std_logic;
                -- Ouput

diff --git a/cpu/src/fetch_stage.vhd b/cpu/src/fetch_stage.vhd
index e77cfbf90ef8d5ae3ff14c3d451bd715baa0f6c6..3165d933ee6303e6d5b2288cccbad403c72a171d 100644 (file)
--- a/cpu/src/fetch_stage.vhd
+++ b/cpu/src/fetch_stage.vhd
@@ -24,6 +24,7 @@ entity fetch_stage is
                        prediction_result : in instruction_addr_t;
                        branch_prediction_bit : in std_logic;
                        alu_jump_bit : in std_logic;
+                       int_req : in interrupt_t;
 
                --Data outputs
                        instruction : out instruction_word_t;

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index cdc6dc6a018f58b578a1759ccd5a110b462af13c..3f4650da12cc6b8c8ef2ce71c795f718453a7032 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -61,7 +61,7 @@ begin
 end process; 
 
 
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom)
+asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
 
 begin
 
@@ -93,6 +93,19 @@ begin
                instr_r_addr_nxt <= prediction_result;
        end if; 
 
+       case int_req is
+               when UART =>
+                       instruction(31 downto 0) <= (others => '0');
+                       instruction(31 downto 28) <= "1110";
+                       instruction(27 downto 23) <= "10110";
+                       instruction(PHYS_INSTR_ADDR_WIDTH + 7 - 1 downto 7) <= UART_INT_VECTOR;
+                       instruction(6 downto 4) <= "001";
+                       instruction(3 downto 2) <= "01";
+                       instruction(1 downto 0) <= "10";
+ 
+               when others => null;
+       end case;
+
 end process;
 
 prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index e396a6bd78f74079dde3c37d25edb765f2c4b735..de276a8fc8f305a9cdb46437ca626d3b1a484eb1 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -59,7 +59,7 @@ architecture behavior of pipeline_tb is
                 signal cycle_cnt : integer;
 
                signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
-
+               signal int_req_pin : interrupt_t;
 
 begin
 
@@ -98,7 +98,8 @@ begin
 
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
-                       prog_cnt => prog_cnt
+                       prog_cnt => prog_cnt,
+                       int_req => int_req_pin
                );      
 
        decode_st : decode_stage
@@ -137,7 +138,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3, int_req_pin);
 
 
 

diff --git a/cpu/src/rom_b.vhd b/cpu/src/rom_b.vhd
index df24abcb72c5cf3cd9fccd6ef29068f462cbc37c..2bce93deacc07e2cf8ac1c6e0c1dfbe76b9897d9 100644 (file)
--- a/cpu/src/rom_b.vhd
+++ b/cpu/src/rom_b.vhd
@@ -97,6 +97,7 @@ begin
 --1;00000024;07990000;stwnz r3, 0(r2);;;
 --1;00000028;eb7ffb01;br 0;;;
 
+--uart test:
 
                                when "0000000" => data_out <= x"ed010058";
                                when "0000001" => data_out <= x"ed090060";
@@ -109,7 +110,8 @@ begin
                                when "0001000" => data_out <= x"07980000";
                                when "0001001" => data_out <= x"07990000";
                                when "0001010" => data_out <= x"eb7ffb81";
-                               
+
+-------------------------------------------                            
                                                        
 --                             when "00000000000" => data_out <= x"ed000000";
 --                             when "00000000001" => data_out <= x"ed080008";
@@ -122,8 +124,10 @@ begin
 --                             when "00000001000" => data_out <= x"e7280004";
 --                     --      when "00000001001" => data_out <= x"eb7ffb81";
 
-                               
-                               when others => data_out <= "11101011000000000000000000000010";
+--                             when "0000000" => data_out <= x"eb000181";
+--                             when "0000001" => data_out <= x"F0000000";
+--                             when "0000010" => data_out <= x"eb000008";
+--                             when others => data_out <= "11101011000000000000000000000010";
 
                        end case;
                end if;

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 956ba51312add5b47655ea9aca1f00d10d3222cd..d4d669c5d936f708e2ddf00b0c9fbb08800720d5 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -42,7 +42,10 @@ entity writeback_stage is
                        sseg0 : out std_logic_vector(0 to 6);
                        sseg1 : out std_logic_vector(0 to 6);
                        sseg2 : out std_logic_vector(0 to 6);
-                       sseg3 : out std_logic_vector(0 to 6)
+                       sseg3 : out std_logic_vector(0 to 6);
+
+                       int_req : out interrupt_t
+
                );
                
 end writeback_stage;

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index a64906b8f96cd936f6f95a03548918ab9926458f..a4d30f68d535f108d39bb58c490176808e26fd3c 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -17,8 +17,12 @@ signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
-signal ext_uart,ext_timer,ext_gpmp,ext_7seg :  extmod_rec;
-signal ext_uart_out, ext_timer_out, ext_gpmp_out : gp_register_t;
+signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int :  extmod_rec;
+signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out : gp_register_t;
+
+--signal int_req : interrupt_t;
+signal uart_int : std_logic;
+
 
 signal sel_nxt, dmem_we, ext_anysel : std_logic;
 
@@ -53,6 +57,7 @@ uart : extension_uart
                        reset,
                        ext_uart,
                        ext_uart_out,
+                       uart_int,
                        bus_rx,
                        bus_tx
                );
@@ -70,6 +75,22 @@ sseg : extension_7seg
                sseg2,
                sseg3
                );
+
+interrupt : extension_interrupt
+       generic map(
+               RESET_VALUE
+               )
+       port map(
+               clk,
+               reset,
+               ext_int,
+               ext_int_out,
+
+               uart_int,
+
+               int_req
+
+               );
        
 syn: process(clk, reset)
 
@@ -282,32 +303,54 @@ begin
   ext_7seg.sel <='0';
   ext_timer.sel <='0';
   ext_gpmp.sel <='0';
+  ext_int.sel <= '0';
   
   ext_uart.wr_en <= wr_en;
   ext_7seg.wr_en <= wr_en;
   ext_timer.wr_en <= wr_en;
   ext_gpmp.wr_en <= wr_en;
-  
+  ext_int.wr_en <= wr_en;  
+
   ext_uart.byte_en <= byte_en;
   ext_7seg.byte_en <= byte_en;
   ext_timer.byte_en <= byte_en;
   ext_gpmp.byte_en <= byte_en;
-  
+  ext_int.byte_en <= byte_en;  
+
   ext_uart.addr <= addr;
   ext_7seg.addr <= addr;
   ext_timer.addr <= addr;
   ext_gpmp.addr <= addr;
+  ext_int.addr <= addr;
 
   ext_uart.data <= data;
   ext_7seg.data <= data;
   ext_timer.data <= data;
   ext_gpmp.data <= data;
+  ext_int.data <= data;
+
    -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
  case addrid is
     when EXT_UART_ADDR => 
        ext_uart.sel <= enable;
                ext_anysel <= enable;
 
+--             ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+--             ext_uart.data <= ram_data;
+--             ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+--             case wb_reg_nxt.address(1 downto 0) is
+--                             when "00" => ext_uart.byte_en <= "0001";
+--                             when "01" => ext_uart.byte_en <= "0010";
+--                             when "10" => ext_uart.byte_en <= "0100";
+--                             --when "11" => ext_uart.byte_en <= "1000";
+--                             when "11" => ext_uart.byte_en <= "1111";
+--                             when others => null;
+--                     end case;
+
+    when EXT_INT_ADDR => 
+       ext_int.sel <= enable;
+               ext_anysel <= enable;
+
 --             ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
 --             ext_uart.data <= ram_data;
 --             ext_uart.addr <= wb_reg_nxt.address(31 downto 2);

diff --git a/transcript b/transcript
index fb6bf88ef9c64976bc40a25755d5720674e59963..f43f4eaee30d1aa178e0b5f67b55ae280fd16a40 100644 (file)
--- a/transcript
+++ b/transcript
@@ -1,9 +1,12 @@
+pwd
+# /home/stefan/processor/calu
 cd cpu/sim
 # reading modelsim.ini
 ls
 # modelsim.ini
 # testcore1.do
 # testcore.do
+# transcript
 # vsim.wlf
 # wave.do
 # work
@@ -31,75 +34,14 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package mem_pkg
-# -- Compiling entity r2_w_ram
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Loading package mem_pkg
-# -- Compiling architecture behaviour of r2_w_ram
-# -- Loading entity r2_w_ram
-# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Compiling entity rom
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Loading package mem_pkg
-# -- Compiling architecture behaviour of rom
-# -- Loading entity rom
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Compiling package extension_pkg
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Compiling package common_pkg
-# -- Compiling package body common_pkg
-# -- Loading package common_pkg
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Loading package common_pkg
-# ** Error: (vcom-13) Recompile work.extension_pkg because work.common_pkg has changed.
-# ** Error: ../src/core_pkg.vhd(7): (vcom-1195) Cannot find expanded name "work.extension_pkg".
-# ** Error: ../src/core_pkg.vhd(7): Unknown expanded name.
-# ** Error: ../src/core_pkg.vhd(9): VHDL Compiler exiting
-# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
-# Error in macro ./testcore.do line 13
-# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
-#     while executing
-# "vcom -work work ../src/core_pkg.vhd"
-do testcore.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Modifying modelsim.ini
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Compiling package mem_pkg
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Compiling entity r_w_ram
+# -- Compiling entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package mem_pkg
-# -- Compiling architecture behaviour of r_w_ram
-# -- Loading entity r_w_ram
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -138,82 +80,67 @@ do testcore.do
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
-# ** Error: (vcom-13) Recompile work.extension_pkg because work.common_pkg has changed.
-# ** Error: ../src/core_pkg.vhd(7): (vcom-1195) Cannot find expanded name "work.extension_pkg".
-# ** Error: ../src/core_pkg.vhd(7): Unknown expanded name.
-# ** Error: ../src/core_pkg.vhd(9): VHDL Compiler exiting
-# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
-# Error in macro ./testcore.do line 12
-# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
-#     while executing
-# "vcom -work work ../src/core_pkg.vhd"
-do testcore.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Modifying modelsim.ini
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Compiling package mem_pkg
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Compiling entity r_w_ram
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Loading package mem_pkg
-# -- Compiling architecture behaviour of r_w_ram
-# -- Loading entity r_w_ram
+# -- Compiling package extension_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package mem_pkg
-# -- Compiling entity r2_w_ram
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package mem_pkg
-# -- Compiling architecture behaviour of r2_w_ram
-# -- Loading entity r2_w_ram
-# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Compiling entity rom
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
 # -- Loading package mem_pkg
-# -- Compiling architecture behaviour of rom
-# -- Loading entity rom
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Compiling package common_pkg
-# -- Compiling package body common_pkg
 # -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
-# ** Error: (vcom-13) Recompile work.extension_pkg because work.common_pkg has changed.
-# ** Error: ../src/core_pkg.vhd(7): (vcom-1195) Cannot find expanded name "work.extension_pkg".
-# ** Error: ../src/core_pkg.vhd(7): Unknown expanded name.
-# ** Error: ../src/core_pkg.vhd(9): VHDL Compiler exiting
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# ** Error: ../src/extension_interrupt_b.vhd(64): (vcom-1136) Unknown identifier "w2_uart_config".
+# ** Error: ../src/extension_interrupt_b.vhd(64): Expression is not a signal.
+# ** Error: ../src/extension_interrupt_b.vhd(64): (vcom-1136) Unknown identifier "w3_uart_send".
+# ** Error: ../src/extension_interrupt_b.vhd(64): Expression is not a signal.
+# ** Error: ../src/extension_interrupt_b.vhd(64): (vcom-1136) Unknown identifier "w4_uart_receive".
+# ** Error: ../src/extension_interrupt_b.vhd(64): Expression is not a signal.
+# ** Error: ../src/extension_interrupt_b.vhd(132): VHDL Compiler exiting
 # ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
-# Error in macro ./testcore.do line 12
+# Error in macro ./testcore.do line 20
 # /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
 #     while executing
-# "vcom -work work ../src/core_pkg.vhd"
+# "vcom -work work ../src/extension_interrupt_b.vhd"
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -238,6 +165,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -312,6 +251,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -398,174 +352,172 @@ do testcore.do
 # -- Loading package core_pkg
 # -- Compiling architecture behav_d of decoder
 # -- Loading entity decoder
+# ** Error: ../src/decoder_b.vhd(35): (vcom-1312) Unknown record element "int" for selected name prefix "instr_s" of record type "work.common_pkg.instruction_rec".
+# ** Error: ../src/decoder_b.vhd(358): (vcom-1312) Unknown record element "int" for selected name prefix "instr_s" of record type "work.common_pkg.instruction_rec".
+# ** Error: ../src/decoder_b.vhd(437): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 30
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/decoder_b.vhd"
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling entity fetch_stage
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
 # -- Loading package mem_pkg
-# -- Compiling architecture behav of fetch_stage
-# -- Loading entity fetch_stage
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling entity decode_stage
+# -- Compiling entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package mem_pkg
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling architecture behav of decode_stage
-# -- Loading entity decode_stage
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Compiling package alu_pkg
-# -- Compiling package body alu_pkg
-# -- Loading package alu_pkg
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Compiling package extension_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity exec_op
+# -- Compiling entity rom
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture add_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
 # -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture and_op of exec_op
-# -- Loading entity exec_op
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture or_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling package extension_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture xor_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling package core_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture shift_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling package extension_uart_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity alu
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture behaviour of alu
-# -- Loading entity alu
-# -- Loading entity exec_op
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
-# -- Compiling package extension_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Compiling entity extension_gpm
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Loading package mem_pkg
-# -- Compiling architecture behav of extension_gpm
-# -- Loading entity extension_gpm
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity execute_stage
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture behav of execute_stage
-# -- Loading entity execute_stage
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
 # -- Loading package numeric_std
 # -- Loading package common_pkg
-# -- Compiling entity writeback_stage
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -573,83 +525,60 @@ do testcore.do
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
 # -- Loading package core_pkg
-# -- Loading package mem_pkg
 # -- Loading package extension_uart_pkg
-# -- Loading package extension_7seg_pkg
-# -- Compiling architecture behav of writeback_stage
-# -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
 # -- Loading package core_pkg
-# -- Compiling entity pipeline_tb
-# -- Compiling architecture behavior of pipeline_tb
-# -- Compiling configuration pipeline_conf_beh
-# -- Loading entity pipeline_tb
-# -- Loading architecture behavior of pipeline_tb
-# -- Loading entity fetch_stage
-# -- Loading entity decode_stage
-# -- Loading package alu_pkg
-# -- Loading entity execute_stage
-# -- Loading entity writeback_stage
-# vsim -t ns work.pipeline_conf_beh 
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.common_pkg(body)
-# Loading work.extension_pkg
-# Loading work.core_pkg
-# Loading work.alu_pkg(body)
-# Loading work.pipeline_conf_beh
-# Loading work.pipeline_tb(behavior)
-# Loading work.mem_pkg
-# Loading work.fetch_stage(behav)
-# Loading work.r_w_ram(behaviour)
-# Loading work.decode_stage(behav)
-# Loading work.r2_w_ram(behaviour)
-# Loading work.decoder(behav_d)
-# Loading work.execute_stage(behav)
-# Loading work.alu(behaviour)
-# Loading work.exec_op(add_op)
-# Loading work.exec_op(and_op)
-# Loading work.exec_op(or_op)
-# Loading work.exec_op(xor_op)
-# Loading work.exec_op(shift_op)
-# Loading work.extension_gpm(behav)
-# Loading work.extension_uart_pkg
-# Loading work.extension_7seg_pkg(body)
-# Loading work.writeback_stage(behav)
-# Loading work.extension_uart(behav)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading work.rs232_tx(beh)
-# Loading work.rs232_rx(beh)
-# Loading work.extension_7seg(behav)
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# ** Error: ../src/decoder_b.vhd(35): (vcom-1312) Unknown record element "int" for selected name prefix "instr_s" of record type "work.common_pkg.instruction_rec".
+# ** Error: ../src/decoder_b.vhd(358): (vcom-1312) Unknown record element "int" for selected name prefix "instr_s" of record type "work.common_pkg.instruction_rec".
+# ** Error: ../src/decoder_b.vhd(437): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 30
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/decoder_b.vhd"
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -674,6 +603,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -748,6 +689,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -852,156 +808,171 @@ do testcore.do
 # -- Loading package mem_pkg
 # -- Compiling architecture behav of fetch_stage
 # -- Loading entity fetch_stage
+# ** Error: ../src/fetch_stage_b.vhd(100): Illegal type conversion from std.standard.integer to ieee.numeric_std.unsigned (numeric to array).
+# ** Error: ../src/fetch_stage_b.vhd(113): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 32
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/fetch_stage_b.vhd"
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling entity decode_stage
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package mem_pkg
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling architecture behav of decode_stage
-# -- Loading entity decode_stage
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Compiling package alu_pkg
-# -- Compiling package body alu_pkg
-# -- Loading package alu_pkg
+# -- Compiling entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Compiling package extension_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture add_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
 # -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture and_op of exec_op
-# -- Loading entity exec_op
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture or_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling package extension_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture xor_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling package core_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture shift_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling package extension_uart_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity alu
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture behaviour of alu
-# -- Loading entity alu
-# -- Loading entity exec_op
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
-# -- Compiling package extension_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Compiling entity extension_gpm
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Loading package mem_pkg
-# -- Compiling architecture behav of extension_gpm
-# -- Loading entity extension_gpm
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity execute_stage
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture behav of execute_stage
-# -- Loading entity execute_stage
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
 # -- Loading package numeric_std
 # -- Loading package common_pkg
-# -- Compiling entity writeback_stage
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -1009,84 +980,77 @@ do testcore.do
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
 # -- Loading package core_pkg
-# -- Loading package mem_pkg
 # -- Loading package extension_uart_pkg
-# -- Loading package extension_7seg_pkg
-# -- Compiling architecture behav of writeback_stage
-# -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
 # -- Loading package core_pkg
-# -- Compiling entity pipeline_tb
-# -- Compiling architecture behavior of pipeline_tb
-# -- Compiling configuration pipeline_conf_beh
-# -- Loading entity pipeline_tb
-# -- Loading architecture behavior of pipeline_tb
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
 # -- Loading entity fetch_stage
-# -- Loading entity decode_stage
-# -- Loading package alu_pkg
-# -- Loading entity execute_stage
-# -- Loading entity writeback_stage
-# vsim -t ns work.pipeline_conf_beh 
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.common_pkg(body)
-# Loading work.extension_pkg
-# Loading work.core_pkg
-# Loading work.alu_pkg(body)
-# Loading work.pipeline_conf_beh
-# Loading work.pipeline_tb(behavior)
-# Loading work.mem_pkg
-# Loading work.fetch_stage(behav)
-# Loading work.rom(behaviour)
-# Loading work.decode_stage(behav)
-# Loading work.r2_w_ram(behaviour)
-# Loading work.decoder(behav_d)
-# Loading work.execute_stage(behav)
-# Loading work.alu(behaviour)
-# Loading work.exec_op(add_op)
-# Loading work.exec_op(and_op)
-# Loading work.exec_op(or_op)
-# Loading work.exec_op(xor_op)
-# Loading work.exec_op(shift_op)
-# Loading work.extension_gpm(behav)
-# Loading work.extension_uart_pkg
-# Loading work.extension_7seg_pkg(body)
-# Loading work.writeback_stage(behav)
-# Loading work.r_w_ram(behaviour)
-# Loading work.extension_uart(behav)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading work.rs232_tx(beh)
-# Loading work.rs232_rx(beh)
-# Loading work.extension_7seg(behav)
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+# ** Error: ../src/fetch_stage_b.vhd(100): Illegal type conversion from std.standard.integer to ieee.std_logic_1164.std_logic_vector (numeric to array).
+# ** Error: ../src/fetch_stage_b.vhd(113): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 32
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/fetch_stage_b.vhd"
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -1111,6 +1075,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -1185,6 +1161,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -1289,241 +1280,154 @@ do testcore.do
 # -- Loading package mem_pkg
 # -- Compiling architecture behav of fetch_stage
 # -- Loading entity fetch_stage
+# ** Error: ../src/fetch_stage_b.vhd(100): No feasible entries for subprogram "to_unsigned".
+# ** Error: ../src/fetch_stage_b.vhd(100): Illegal type conversion to ieee.std_logic_1164.std_logic_vector (operand type is not known).
+# ** Error: ../src/fetch_stage_b.vhd(113): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 32
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/fetch_stage_b.vhd"
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling entity decode_stage
+# -- Compiling package mem_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package mem_pkg
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling architecture behav of decode_stage
-# -- Loading entity decode_stage
+# -- Compiling entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Compiling package alu_pkg
-# -- Compiling package body alu_pkg
-# -- Loading package alu_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Compiling package extension_pkg
+# -- Compiling entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture add_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture and_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture or_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling entity rom
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture xor_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture shift_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling package common_pkg
+# ** Error: ../src/common_pkg.vhd(84): (vcom-1272) Length of expected is 12; length of actual is 11.
+# ** Error: ../src/common_pkg.vhd(173): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 13
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/common_pkg.vhd"
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity alu
+# -- Compiling package mem_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture behaviour of alu
-# -- Loading entity alu
-# -- Loading entity exec_op
+# -- Compiling entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Compiling package extension_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Compiling entity extension_gpm
+# -- Compiling entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
 # -- Loading package mem_pkg
-# -- Compiling architecture behav of extension_gpm
-# -- Loading entity extension_gpm
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity execute_stage
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture behav of execute_stage
-# -- Loading entity execute_stage
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Compiling entity writeback_stage
+# -- Compiling entity rom
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
 # -- Loading package mem_pkg
-# -- Loading package extension_uart_pkg
-# -- Loading package extension_7seg_pkg
-# -- Compiling architecture behav of writeback_stage
-# -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling entity pipeline_tb
-# -- Compiling architecture behavior of pipeline_tb
-# -- Compiling configuration pipeline_conf_beh
-# -- Loading entity pipeline_tb
-# -- Loading architecture behavior of pipeline_tb
-# -- Loading entity fetch_stage
-# -- Loading entity decode_stage
-# -- Loading package alu_pkg
-# -- Loading entity execute_stage
-# -- Loading entity writeback_stage
-# vsim -t ns work.pipeline_conf_beh 
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.common_pkg(body)
-# Loading work.extension_pkg
-# Loading work.core_pkg
-# Loading work.alu_pkg(body)
-# Loading work.pipeline_conf_beh
-# Loading work.pipeline_tb(behavior)
-# Loading work.mem_pkg
-# Loading work.fetch_stage(behav)
-# Loading work.rom(behaviour)
-# Loading work.decode_stage(behav)
-# Loading work.r2_w_ram(behaviour)
-# Loading work.decoder(behav_d)
-# Loading work.execute_stage(behav)
-# Loading work.alu(behaviour)
-# Loading work.exec_op(add_op)
-# Loading work.exec_op(and_op)
-# Loading work.exec_op(or_op)
-# Loading work.exec_op(xor_op)
-# Loading work.exec_op(shift_op)
-# Loading work.extension_gpm(behav)
-# Loading work.extension_uart_pkg
-# Loading work.extension_7seg_pkg(body)
-# Loading work.writeback_stage(behav)
-# Loading work.r_w_ram(behaviour)
-# Loading work.extension_uart(behav)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading work.rs232_tx(beh)
-# Loading work.rs232_rx(beh)
-# Loading work.extension_7seg(behav)
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+# -- Compiling package common_pkg
+# ** Error: ../src/common_pkg.vhd(84): (vcom-1272) Length of expected is 12; length of actual is 11.
+# ** Error: ../src/common_pkg.vhd(173): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 13
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/common_pkg.vhd"
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -1548,6 +1452,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -1622,6 +1538,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -1726,6 +1657,7 @@ do testcore.do
 # -- Loading package mem_pkg
 # -- Compiling architecture behav of fetch_stage
 # -- Loading entity fetch_stage
+# ** Warning: [14] ../src/fetch_stage_b.vhd(100): (vcom-1272) Length of expected is 16; length of actual is 11.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -1888,79 +1820,18 @@ do testcore.do
 # -- Loading package extension_7seg_pkg
 # -- Compiling architecture behav of writeback_stage
 # -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
-# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling entity pipeline_tb
-# -- Compiling architecture behavior of pipeline_tb
-# -- Compiling configuration pipeline_conf_beh
-# -- Loading entity pipeline_tb
-# -- Loading architecture behavior of pipeline_tb
-# -- Loading entity fetch_stage
-# -- Loading entity decode_stage
-# -- Loading package alu_pkg
-# -- Loading entity execute_stage
-# -- Loading entity writeback_stage
-# vsim -t ns work.pipeline_conf_beh 
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.common_pkg(body)
-# Loading work.extension_pkg
-# Loading work.core_pkg
-# Loading work.alu_pkg(body)
-# Loading work.pipeline_conf_beh
-# Loading work.pipeline_tb(behavior)
-# Loading work.mem_pkg
-# Loading work.fetch_stage(behav)
-# Loading work.rom(behaviour)
-# Loading work.decode_stage(behav)
-# Loading work.r2_w_ram(behaviour)
-# Loading work.decoder(behav_d)
-# Loading work.execute_stage(behav)
-# Loading work.alu(behaviour)
-# Loading work.exec_op(add_op)
-# Loading work.exec_op(and_op)
-# Loading work.exec_op(or_op)
-# Loading work.exec_op(xor_op)
-# Loading work.exec_op(shift_op)
-# Loading work.extension_gpm(behav)
-# Loading work.extension_uart_pkg
-# Loading work.extension_7seg_pkg(body)
-# Loading work.writeback_stage(behav)
-# Loading work.r_w_ram(behaviour)
-# Loading work.extension_uart(behav)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading work.rs232_tx(beh)
-# Loading work.rs232_rx(beh)
-# Loading work.extension_7seg(behav)
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+# ** Error: ../src/writeback_stage_b.vhd(91): Cannot assign to object "int_req" of mode IN.
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# ** Error: ../src/writeback_stage_b.vhd(417): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 62
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/writeback_stage_b.vhd"
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -1985,6 +1856,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -2059,6 +1942,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -2163,6 +2061,7 @@ do testcore.do
 # -- Loading package mem_pkg
 # -- Compiling architecture behav of fetch_stage
 # -- Loading entity fetch_stage
+# ** Warning: [14] ../src/fetch_stage_b.vhd(100): (vcom-1272) Length of expected is 16; length of actual is 11.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -2325,10 +2224,11 @@ do testcore.do
 # -- Loading package extension_7seg_pkg
 # -- Compiling architecture behav of writeback_stage
 # -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -2338,66 +2238,13 @@ do testcore.do
 # -- Loading package core_pkg
 # -- Compiling entity pipeline_tb
 # -- Compiling architecture behavior of pipeline_tb
-# -- Compiling configuration pipeline_conf_beh
-# -- Loading entity pipeline_tb
-# -- Loading architecture behavior of pipeline_tb
-# -- Loading entity fetch_stage
-# -- Loading entity decode_stage
-# -- Loading package alu_pkg
-# -- Loading entity execute_stage
-# -- Loading entity writeback_stage
-# vsim -t ns work.pipeline_conf_beh 
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.common_pkg(body)
-# Loading work.extension_pkg
-# Loading work.core_pkg
-# Loading work.alu_pkg(body)
-# Loading work.pipeline_conf_beh
-# Loading work.pipeline_tb(behavior)
-# Loading work.mem_pkg
-# Loading work.fetch_stage(behav)
-# Loading work.rom(behaviour)
-# Loading work.decode_stage(behav)
-# Loading work.r2_w_ram(behaviour)
-# Loading work.decoder(behav_d)
-# Loading work.execute_stage(behav)
-# Loading work.alu(behaviour)
-# Loading work.exec_op(add_op)
-# Loading work.exec_op(and_op)
-# Loading work.exec_op(or_op)
-# Loading work.exec_op(xor_op)
-# Loading work.exec_op(shift_op)
-# Loading work.extension_gpm(behav)
-# Loading work.extension_uart_pkg
-# Loading work.extension_7seg_pkg(body)
-# Loading work.writeback_stage(behav)
-# Loading work.r_w_ram(behaviour)
-# Loading work.extension_uart(behav)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading work.rs232_tx(beh)
-# Loading work.rs232_rx(beh)
-# Loading work.extension_7seg(behav)
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
-# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
-#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+# ** Error: ../src/pipeline_tb.vhd(102): (vcom-1035) Formal port "int_req" has OPEN or no actual associated with it.
+# ** Error: ../src/pipeline_tb.vhd(223): VHDL Compiler exiting
+# ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+# Error in macro ./testcore.do line 64
+# /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
+#     while executing
+# "vcom -work work ../src/pipeline_tb.vhd"
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -2422,16 +2269,28 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package mem_pkg
-# -- Compiling entity r2_w_ram
+# -- Compiling entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package mem_pkg
-# -- Compiling architecture behaviour of r2_w_ram
-# -- Loading entity r2_w_ram
-# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -2496,6 +2355,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -2600,6 +2474,7 @@ do testcore.do
 # -- Loading package mem_pkg
 # -- Compiling architecture behav of fetch_stage
 # -- Loading entity fetch_stage
+# ** Warning: [14] ../src/fetch_stage_b.vhd(100): (vcom-1272) Length of expected is 16; length of actual is 11.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -2762,10 +2637,11 @@ do testcore.do
 # -- Loading package extension_7seg_pkg
 # -- Compiling architecture behav of writeback_stage
 # -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -2795,6 +2671,7 @@ do testcore.do
 # Loading work.pipeline_tb(behavior)
 # Loading work.mem_pkg
 # Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
 # Loading work.rom(behaviour)
 # Loading work.decode_stage(behav)
 # Loading work.r2_w_ram(behaviour)
@@ -2810,13 +2687,14 @@ do testcore.do
 # Loading work.extension_uart_pkg
 # Loading work.extension_7seg_pkg(body)
 # Loading work.writeback_stage(behav)
-# Loading work.r_w_ram(behaviour)
+# Loading work.r_w_ram_be(behaviour)
 # Loading work.extension_uart(behav)
 # Loading ieee.std_logic_arith(body)
 # Loading ieee.std_logic_unsigned(body)
 # Loading work.rs232_tx(beh)
 # Loading work.rs232_rx(beh)
 # Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
 #    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
@@ -2859,6 +2737,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -2933,6 +2823,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -2995,30 +2900,762 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package extension_uart_pkg
-# -- Loading package core_pkg
-# -- Compiling architecture beh of rs232_rx
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading entity rs232_rx
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# ** Warning: [14] ../src/fetch_stage_b.vhd(100): (vcom-1272) Length of expected is 16; length of actual is 11.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling entity writeback_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
+# -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh 
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
+run
+restart
+run
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+restart
+run
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+restart
+run
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+run -continue
+run
+restart
+run
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+run
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
+# -- Loading package common_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# ** Warning: [14] ../src/fetch_stage_b.vhd(100): (vcom-1272) Length of expected is 16; length of actual is 11.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling entity decoder
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package mem_pkg
 # -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package core_pkg
-# -- Compiling architecture behav_d of decoder
-# -- Loading entity decoder
+# -- Compiling entity writeback_stage
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -3026,7 +3663,16 @@ do testcore.do
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
 # -- Loading package core_pkg
-# -- Compiling entity fetch_stage
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -3034,9 +3680,120 @@ do testcore.do
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
 # -- Loading package core_pkg
-# -- Loading package mem_pkg
-# -- Compiling architecture behav of fetch_stage
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
 # -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh 
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+run
+run
+run
+run
+run
+run
+run
+# ** Fatal: (vsim-3420) Array lengths do not match. Left is 16 (22 downto 7). Right is 11 (10 downto 0).
+#    Time: 104840 ns  Iteration: 3  Process: /pipeline_tb/fetch_st/asyn File: ../src/fetch_stage_b.vhd
+# Fatal error in Process asyn at ../src/fetch_stage_b.vhd line 100
+# 
+# HDL call sequence:
+# Stopped at ../src/fetch_stage_b.vhd 100 Process asyn
+# 
+run
+# Cannot continue because of fatal error.
+# HDL call sequence:
+# Stopped at ../src/fetch_stage_b.vhd 100 Process asyn
+# 
+run
+# Cannot continue because of fatal error.
+# HDL call sequence:
+# Stopped at ../src/fetch_stage_b.vhd 100 Process asyn
+# 
+run
+# Cannot continue because of fatal error.
+# HDL call sequence:
+# Stopped at ../src/fetch_stage_b.vhd 100 Process asyn
+# 
+run
+# Cannot continue because of fatal error.
+# HDL call sequence:
+# Stopped at ../src/fetch_stage_b.vhd 100 Process asyn
+# 
+run
+# Cannot continue because of fatal error.
+# HDL call sequence:
+# Stopped at ../src/fetch_stage_b.vhd 100 Process asyn
+# 
+run
+# Cannot continue because of fatal error.
+# HDL call sequence:
+# Stopped at ../src/fetch_stage_b.vhd 100 Process asyn
+# 
+run
+# Cannot continue because of fatal error.
+# HDL call sequence:
+# Stopped at ../src/fetch_stage_b.vhd 100 Process asyn
+# 
+vcom -reportprogress 300 -work work /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -3044,110 +3801,127 @@ do testcore.do
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
 # -- Loading package core_pkg
-# -- Compiling entity decode_stage
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# ** Error: /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(101): (vcom-1136) Unknown identifier "physical_instr_addr_width".
+# ** Error: /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(101): Bad expression in left bound of range expression.
+# ** Error: /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(101): Type error in range expression.
+# ** Error: /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(114): VHDL Compiler exiting
+vcom -reportprogress 300 -work work /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package mem_pkg
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
 # -- Loading package core_pkg
-# -- Compiling architecture behav of decode_stage
-# -- Loading entity decode_stage
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# ** Warning: [3] /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(101): (vcom-1246) Range 5 downto 7 is null.
+# ** Warning: [14] /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(101): (vcom-1272) Length of expected is 0; length of actual is 11.
+vcom -reportprogress 300 -work work /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
-# -- Compiling package alu_pkg
-# -- Compiling package body alu_pkg
-# -- Loading package alu_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+restart
+# Loading work.fetch_stage(behav)
+run
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 1  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 3  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 4  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+#    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+run
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Compiling package extension_pkg
+# -- Compiling package mem_pkg
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity exec_op
+# -- Compiling entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture add_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture and_op of exec_op
-# -- Loading entity exec_op
+# -- Compiling entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture or_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture xor_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture shift_op of exec_op
-# -- Loading entity exec_op
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling entity alu
+# -- Compiling entity rom
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
-# -- Loading package common_pkg
-# -- Loading package extension_pkg
-# -- Loading package alu_pkg
-# -- Compiling architecture behaviour of alu
-# -- Loading entity alu
-# -- Loading entity exec_op
-# ** Error: ../src/alu_b.vhd(178): No feasible entries for subprogram "to_stdlogicvector".
-# ** Error: ../src/alu_b.vhd(221): VHDL Compiler exiting
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# ** Error: ../src/rom_b.vhd(127): (vcom-1167) Index value -4 is out of std.standard.natural range 0 to 2147483647.
+# ** Error: ../src/rom_b.vhd(128): (vcom-1167) Index value -4 is out of std.standard.natural range 0 to 2147483647.
+# ** Warning: [14] ../src/rom_b.vhd(127): (vcom-1272) Length of expected is 7; length of actual is 11.
+# ** Warning: [14] ../src/rom_b.vhd(128): (vcom-1272) Length of expected is 7; length of actual is 11.
+# ** Error: ../src/rom_b.vhd(137): VHDL Compiler exiting
 # ** Error: /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
-# Error in macro ./testcore.do line 43
+# Error in macro ./testcore.do line 12
 # /opt/altera/10.0sp1/modelsim_ase/linuxaloem/vcom failed.
 #     while executing
-# "vcom -work work ../src/alu_b.vhd"
+# "vcom -work work ../src/rom_b.vhd"
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -3172,6 +3946,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -3246,6 +4032,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -3512,10 +4313,11 @@ do testcore.do
 # -- Loading package extension_7seg_pkg
 # -- Compiling architecture behav of writeback_stage
 # -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -3545,6 +4347,7 @@ do testcore.do
 # Loading work.pipeline_tb(behavior)
 # Loading work.mem_pkg
 # Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
 # Loading work.rom(behaviour)
 # Loading work.decode_stage(behav)
 # Loading work.r2_w_ram(behaviour)
@@ -3560,13 +4363,14 @@ do testcore.do
 # Loading work.extension_uart_pkg
 # Loading work.extension_7seg_pkg(body)
 # Loading work.writeback_stage(behav)
-# Loading work.r_w_ram(behaviour)
+# Loading work.r_w_ram_be(behaviour)
 # Loading work.extension_uart(behav)
 # Loading ieee.std_logic_arith(body)
 # Loading ieee.std_logic_unsigned(body)
 # Loading work.rs232_tx(beh)
 # Loading work.rs232_rx(beh)
 # Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
 #    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
@@ -3585,6 +4389,8 @@ do testcore.do
 #    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
 #    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+run
+run
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -3609,6 +4415,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -3683,6 +4501,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -3949,10 +4782,11 @@ do testcore.do
 # -- Loading package extension_7seg_pkg
 # -- Compiling architecture behav of writeback_stage
 # -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -3982,6 +4816,7 @@ do testcore.do
 # Loading work.pipeline_tb(behavior)
 # Loading work.mem_pkg
 # Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
 # Loading work.rom(behaviour)
 # Loading work.decode_stage(behav)
 # Loading work.r2_w_ram(behaviour)
@@ -3997,13 +4832,14 @@ do testcore.do
 # Loading work.extension_uart_pkg
 # Loading work.extension_7seg_pkg(body)
 # Loading work.writeback_stage(behav)
-# Loading work.r_w_ram(behaviour)
+# Loading work.r_w_ram_be(behaviour)
 # Loading work.extension_uart(behav)
 # Loading ieee.std_logic_arith(body)
 # Loading ieee.std_logic_unsigned(body)
 # Loading work.rs232_tx(beh)
 # Loading work.rs232_rx(beh)
 # Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
 #    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
@@ -4022,6 +4858,7 @@ do testcore.do
 #    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
 #    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+run
 do testcore.do
 # ** Warning: (vlib-34) Library already exists at "work".
 # Modifying modelsim.ini
@@ -4046,6 +4883,18 @@ do testcore.do
 # -- Loading package standard
 # -- Loading package std_logic_1164
 # -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
 # -- Loading package mem_pkg
 # -- Compiling entity r2_w_ram
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
@@ -4120,6 +4969,21 @@ do testcore.do
 # -- Loading package numeric_std
 # -- Loading package common_pkg
 # -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
 # -- Compiling package extension_7seg_pkg
 # -- Compiling package body extension_7seg_pkg
 # -- Loading package extension_7seg_pkg
@@ -4386,10 +5250,11 @@ do testcore.do
 # -- Loading package extension_7seg_pkg
 # -- Compiling architecture behav of writeback_stage
 # -- Loading entity writeback_stage
-# ** Warning: ../src/writeback_stage_b.vhd(298): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(314): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(332): Case choice must be a locally static expression.
-# ** Warning: ../src/writeback_stage_b.vhd(345): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
 # Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
 # -- Loading package standard
 # -- Loading package std_logic_1164
@@ -4419,6 +5284,7 @@ do testcore.do
 # Loading work.pipeline_tb(behavior)
 # Loading work.mem_pkg
 # Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
 # Loading work.rom(behaviour)
 # Loading work.decode_stage(behav)
 # Loading work.r2_w_ram(behaviour)
@@ -4434,13 +5300,14 @@ do testcore.do
 # Loading work.extension_uart_pkg
 # Loading work.extension_7seg_pkg(body)
 # Loading work.writeback_stage(behav)
-# Loading work.r_w_ram(behaviour)
+# Loading work.r_w_ram_be(behaviour)
 # Loading work.extension_uart(behav)
 # Loading ieee.std_logic_arith(body)
 # Loading ieee.std_logic_unsigned(body)
 # Loading work.rs232_tx(beh)
 # Loading work.rs232_rx(beh)
 # Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
 #    Time: 0 ns  Iteration: 0  Instance: /pipeline_tb/writeback_st
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
@@ -4459,3 +5326,4 @@ do testcore.do
 #    Time: 0 ns  Iteration: 5  Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
 # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
 #    Time: 20 ns  Iteration: 1  Instance: /pipeline_tb/writeback_st/data_ram
+run