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modelsim lauffähig
2010-12-19 Stefan Rebernigmodelsim lauffähig
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2010-12-19 Stefan Rebernigversion not running!
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2010-12-17 Stefan Rebernig7seg small changes
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2010-12-17 Stefan Rebernignochmal...
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2010-12-17 Stefan Reberniginstr mem durch case, fibonacci als programm, 7seg...
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2010-12-17 Stefan REBERNIGwriteback_stage: differenzieren zwischen memory und...
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2010-12-17 Stefan REBERNIGwb extension
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2010-12-17 Stefan REBERNIGuart: blinkt zwar nur am led aber des is schon net...
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2010-12-14 Stefan Rebernigfmax incr
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2010-12-11 Stefan Rebernigadded todo-vhdl.txt
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2010-12-11 Stefan Rebernigfibonacci die 2.
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2010-12-11 Stefan Rebernigfibonacci tested rc1, 107 cycles, 1k2le, 57MHz
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2010-12-11 Stefan Rebernigfib 1
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2010-12-11 Stefan Rebernigfib
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2010-12-11 Stefan Rebernigcall/return
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2010-12-11 Stefan Rebernigreturn - erster versuch
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2010-12-11 Stefan Rebernigdecoder for st-op
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2010-12-02 Stefan Rebernigstatic branch - small bug fix
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2010-12-01 Stefan Rebernigstatic branch - getestet, 58MHz lt quartus
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2010-12-01 Stefan Rebernigstatic branch incl prediction rc1
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2010-12-01 Stefan Rebernigstatic branch 1.0
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2010-11-29 Stefan Rebernigstw.2
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2010-11-29 Stefan Rebernigst
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2010-11-29 Stefan Rebernigdecoder add ldi
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2010-11-26 Stefan Rebernigforward unit testcases (from assignments), everything...
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2010-11-17 Stefan Rebernigkleine Änderungen
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2010-11-16 Stefan Rebernigkleinigkeit ausgebessert
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2010-11-16 Stefan Rebernig2nd forward unit - 58MHz with 31bit shift...
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2010-11-16 Stefan Rebernignop insertion added
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2010-11-15 Stefan Rebernigpipeline erste version mit 31bit shifter (kostet 7MHz...
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2010-11-15 Stefan Rebernigtest pipe 2
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2010-11-15 Stefan Rebernigpipe v1
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2010-11-15 Stefan Rebernigblub
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2010-11-15 Stefan Rebernigwriteback stage
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2010-10-18 Stefan RebernigARM up2date
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Deep Thought (softcore CPU)