Every board had a slightly different invokation, very often commented out
anyway. We could either decide that this is only to be used by developers
during bringup (and thus added manually to romstage.c and removed before
the board gets committed). This method seems to be preferred from what I
have heard on IRC / mailing list in the past.
Or, we add the ram_check() somewhere globally and allow the user to enable
it via menuconfig (possibly only if EXPERT is selected).
Either way, the current method of spreading the calls all over the place is
not really the way to go.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6115
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
56 files changed:
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977f/w83977f_early_serial.c"
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977f/w83977f_early_serial.c"
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
- /* ram_check(0, 640 * 1024); */
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0x00000000, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0x00000000, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
sdram_initialize(1, memctrl);
msr_init();
sdram_initialize(1, memctrl);
msr_init();
-
- /* Check all of memory */
- //ram_check(0x00000000, 640*1024);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
// die("After MCT init before CAR disabled.");
post_code(0x42);
// die("After MCT init before CAR disabled.");
post_code(0x42);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
msr = rdmsr(MC_CF8F_DATA);
print_debug(" \n");
#endif
msr = rdmsr(MC_CF8F_DATA);
print_debug(" \n");
#endif
-
- /* Check memory. */
- // ram_check(0x00000000, 640 * 1024);
- // ram_check(1024 * 1024, 2 * 1024 * 1024);
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
- /* ram_check(0, 640 * 1024); */
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
#include "cpu/x86/bist.h"
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
- /* ram_check(0x00000000, 0x4000); */
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
- /* ram_check(0, 640 * 1024); */
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
- /* ram_check(0, 640 * 1024); */
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
-
- /* ram_check(0, 640 * 1024); */
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc8374/pc8374_early_init.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc8374/pc8374_early_init.c"
dump_pci_device(PCI_DEV(0, 0x00, 0));
// dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
// dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-
-#if 1 // temporarily disabled
- /* Check the first 1M */
-// ram_check(0x00000000, 0x000100000);
-// ram_check(0x00000000, 0x000a0000);
-// ram_check(0x00100000, 0x01000000);
- ram_check(0x00100000, 0x00100100);
- /* check the first 1M in the 3rd Gig */
-// ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
- ram_check(0x00000000, 0x02000000);
-#endif
#if 0
dump_pci_devices();
dump_pci_device(PCI_DEV(0, 0, 0));
#if 0
dump_pci_devices();
dump_pci_device(PCI_DEV(0, 0, 0));
-
- // Check all of memory
- ram_check(0x00000000, msr.lo+(msr.hi<<32));
- // Check 16MB of memory @ 0
- ram_check(0x00000000, 0x01000000);
- // Check 16MB of memory @ 2GB
- ram_check(0x80000000, 0x81000000);
#include <arch/hlt.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <arch/hlt.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
void setup_pars(void)
#include "cpu/x86/bist.h"
void setup_pars(void)
dump_pci_device(PCI_DEV(0, 0, 0));
#endif
dump_pci_device(PCI_DEV(0, 0, 0));
#endif
-#if 0
- print_err("RAM CHECK!\n");
- // Check 16MB of memory @ 0
- ram_check(0x00000000, 0x01000000);
-#endif
-#if 0
- print_err("RAM CHECK for 32 MB!\n");
- // Check 32MB of memory @ 0
- ram_check(0x00000000, 0x02000000);
-#endif
#if 1
{
volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000;
#if 1
{
volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000;
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check all of memory */
- ram_check(0x00000000, 640*1024);
-
/* Switch from Cache as RAM to real RAM */
/* There are two ways we could think about this.
1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.
/* Switch from Cache as RAM to real RAM */
/* There are two ways we could think about this.
1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "superio/winbond/w83977f/w83977f_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977f/w83977f_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "cpu/x86/bist.h"
cs5530_enable_rom();
sdram_init();
cs5530_enable_rom();
sdram_init();
- /* ram_check(0x00000000, 640 * 1024); */
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "cpu/x86/bist.h"
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
- /* ram_check(0x00000000, 640 * 1024); */
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* ram_check(0, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc87427/pc87427.h"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc87427/pc87427.h"
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-
-#if 0 // temporarily disabled
- /* Check the first 1M */
-// ram_check(0x00000000, 0x000100000);
-// ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, 0x01000000);
- /* check the first 1M in the 3rd Gig */
- ram_check(0x30100000, 0x31000000);
-#if 0
- ram_check(0x00000000, 0x02000000);
-#endif
-
-#endif
/* dump_pci_devices(); */
/* dump_pci_device(PCI_DEV(0, 0x00, 0)); */
/* dump_bar14(PCI_DEV(0, 0x00, 0)); */
/* dump_pci_devices(); */
/* dump_pci_device(PCI_DEV(0, 0x00, 0)); */
/* dump_bar14(PCI_DEV(0, 0x00, 0)); */
-
- ram_check(0, 1024 * 1024);
#include <pc80/mc146818rtc.h>
#include "pc80/udelay_io.c"
#include <console/console.h>
#include <pc80/mc146818rtc.h>
#include "pc80/udelay_io.c"
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "northbridge/intel/i3100/raminit_ep80579.h"
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "northbridge/intel/i3100/raminit_ep80579.h"
#ifdef TRUXTON_DEBUG
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
#ifdef TRUXTON_DEBUG
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-
-#ifdef TRUXTON_DEBUG
- ram_fill(0x00000000, 0x02000000);
- ram_verify(0x00000000, 0x02000000);
-#endif
#include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#include "cpu/x86/lapic/boot_cpu.c"
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
-
- /* ram_check(0, 640 * 1024); */
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
sdram_set_spd_registers();
sdram_enable();
}
sdram_set_spd_registers();
sdram_enable();
}
-
-#if 0
- dump_pci_devices();
- dump_pci_device(PCI_DEV(0, 0, 0));
-
- // Check all of memory
- ram_check(0x00000000, msr.lo+(msr.hi<<32));
- // Check 16MB of memory @ 0
- ram_check(0x00000000, 0x01000000);
- // Check 16MB of memory @ 2GB
- ram_check(0x80000000, 0x81000000);
-#endif
outb( temp, 0x4F);
temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
print_debug_hex8(temp);print_debug("\n");
outb( temp, 0x4F);
temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
print_debug_hex8(temp);print_debug("\n");
- /* Check all of memory */
-// ram_check(0, 16384);
- ram_check(0x20000, 0x24000);
-// ram_check(0x00000000, 640*1024);
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0x00000000, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory */
- /* Enable this only if you are having questions. */
- /* ram_check(0, 640 * 1024); */
-
/* Switch from Cache as RAM to real RAM.
*
* There are two ways we could think about this.
/* Switch from Cache as RAM to real RAM.
*
* There are two ways we could think about this.
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory */
- /* Enable this only if you are having questions. */
- /* ram_check(0, 640 * 1024); */
-
/* Switch from Cache as RAM to real RAM.
*
* There are two ways we could think about this.
/* Switch from Cache as RAM to real RAM.
*
* There are two ways we could think about this.
/* Initialize memory */
sdram_initialize();
/* Initialize memory */
sdram_initialize();
-
- /* Check RAM. */
- /* ram_check(0, 640 * 1024); */
- /* ram_check(64512 * 1024, 65536 * 1024); */
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
dump_pci_device(PCI_DEV(0, 0x00, 0));
// dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
// dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-
-#if 0 // temporarily disabled
- /* Check the first 1M */
-// ram_check(0x00000000, 0x000100000);
-// ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, 0x01000000);
- /* check the first 1M in the 3rd Gig */
- ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
- ram_check(0x00000000, 0x02000000);
-#endif
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-
-#if 0 // temporarily disabled
- /* Check the first 1M */
-// ram_check(0x00000000, 0x000100000);
-// ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, 0x01000000);
- /* check the first 1M in the 3rd Gig */
- ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
- ram_check(0x00000000, 0x02000000);
-#endif
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc87427/pc87427.h"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/nsc/pc87427/pc87427.h"
dump_pci_device(PCI_DEV(0, 0x00, 0));
//dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
//dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-
-#if 0 // temporarily disabled
- /* Check the first 1M */
-// ram_check(0x00000000, 0x000100000);
-// ram_check(0x00000000, 0x000a0000);
- ram_check(0x00100000, 0x01000000);
- /* check the first 1M in the 3rd Gig */
- ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
- ram_check(0x00000000, 0x02000000);
-#endif
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
static const struct mem_controller mch[] = {
{
.node_id = 0,
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-
-#if 0 // temporarily disabled
- /* Check the first 1M */
-// ram_check(0x00000000, 0x000100000);
-// ram_check(0x00000000, 0x000a0000);
-// ram_check(0x00100000, 0x01000000);
- ram_check(0x00100000, 0x00100100);
- /* check the first 1M in the 3rd Gig */
-// ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
- ram_check(0x00000000, 0x02000000);
-#endif
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
#include "superio/winbond/w83627hf/w83627hf.h"
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
-
-#if 0 // temporarily disabled
- /* Check the first 1M */
-// ram_check(0x00000000, 0x000100000);
-// ram_check(0x00000000, 0x000a0000);
-// ram_check(0x00100000, 0x01000000);
- ram_check(0x00100000, 0x00100100);
- /* check the first 1M in the 3rd Gig */
-// ram_check(0x30100000, 0x31000000);
-#endif
-#if 0
- ram_check(0x00000000, 0x02000000);
-#endif
#include <arch/hlt.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <arch/hlt.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#define TS5300_LED_OFF outb((inb(0x77)&0xfe), 0x77)
#include "cpu/x86/bist.h"
#define TS5300_LED_OFF outb((inb(0x77)&0xfe), 0x77)
identify_system();
#endif
identify_system();
#endif
-#if 0
- // Check 32MB of memory @ 0 (very slow!)
- print_err("Checking memory:\n");
- ram_check(0x00000000, 0x000a0000);
- ram_check(0x000b0000, 0x02000000);
-#endif
-
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
- /* ram_check(0, 640 * 1024); */
#if CONFIG_LLSHELL
llshell();
#endif
#if CONFIG_LLSHELL
llshell();
#endif
- /* Check RAM. */
- /* ram_check(0, 640 * 1024); */
- /* ram_check(64512 * 1024, 65536 * 1024); */
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0x00000000, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
report_bist_failure(bist);
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
report_bist_failure(bist);
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
- /* ram_check(0, 640 * 1024); */
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/via/vt8623/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/via/vt8623/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
ddr_ram_setup((const struct mem_controller *)0);
ddr_ram_setup((const struct mem_controller *)0);
- /* Check all of memory */
-#if 0
- static const struct {
- unsigned long lo, hi;
- } check_addrs[] = {
- /* Check 16MB of memory @ 0*/
- { 0x00000000, 0x01000000 },
- };
- int i;
- for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
- ram_check(check_addrs[i].lo, check_addrs[i].hi);
- }
-#endif
-
if (bist == 0)
early_mtrr_init();
if (bist == 0)
early_mtrr_init();
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/via/cn400/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/via/cn400/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
if (bist == 0)
early_mtrr_init();
if (bist == 0)
early_mtrr_init();
-
- //ram_check(0, 640 * 1024);
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
sdram_set_registers((const struct mem_controller *) 0);
sdram_set_spd_registers((const struct mem_controller *) 0);
sdram_enable(0, (const struct mem_controller *) 0);
sdram_set_registers((const struct mem_controller *) 0);
sdram_set_spd_registers((const struct mem_controller *) 0);
sdram_enable(0, (const struct mem_controller *) 0);
-
- /* Check all of memory */
-#if 0
- ram_check(0x00000000, msr.lo);
-#endif
-#if 0
- static const struct {
- unsigned long lo, hi;
- } check_addrs[] = {
- /* Check 16MB of memory @ 0*/
- { 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
- /* Check 16MB of memory @ 2GB */
- { 0x80000000, 0x81000000 },
-#endif
- };
- int i;
- for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
- ram_check(check_addrs[i].lo, check_addrs[i].hi);
- }
-#endif
smbus_fixup(&ctrl);
report_bist_failure(bist);
ddr_ram_setup(&ctrl);
smbus_fixup(&ctrl);
report_bist_failure(bist);
ddr_ram_setup(&ctrl);
- /* ram_check(0, 640 * 1024); */
sdram_initialize(1, memctrl);
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0x00000000, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
print_err("ram setup done\n");
msr_init();
print_err("ram setup done\n");
msr_init();
-
- /* Check all of memory */
- /*ram_check(0x00000000, 640*1024);*/