libpayload: Fix OHCI some more

OHCI works when USB_DEBUG is disabled, but not, when disabled.
This is because the controller requires some more time after a
schedule has finished.

Also improve compliance with the OHCI spec.

Change-Id: I4685cc485ff9c52b489fbaa352ab889671cff876
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/365
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

remove trailing whitespace

Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Remove XIP_ROM_BASE

The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).

Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Run dos2unix on bayou and remove white space at the end of lines.

Change-Id: If13d9a49ece2699885ae3e998173d3d44507b302
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/362
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

buildgcc: Fix colors for dash

The previous fix broke buildgcc colors on MacOS X.
This uses an encoding that should be more universal.

Change-Id: I31ac6090ffb7c04784cf6566823652f229aebbb5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/361
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add support for E7505 northbridge.

Adapted from northbridge/intel/e7501 with only minor changes.
This commit provides minimal patch from e7501 and I prefer any
cosmetic clean-up to be done after initial merge.

Due the incomplete register specifications, it is safer to have
e7505 as a separate directory in case I improve it to support
wider range of memory configurations. I have no e7501 to test with.

Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/295
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix usb debug dongle support

- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
  structure from romstage doesn't work right now. This way of copying
  data from romstage to ramstage is really board/cpu specific, and is
  likely to break often. So don't do it.

Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

crossgcc: Fix colors with dash

Ubuntu (and probably other distros) have dash as /bin/sh, which
doesn't display colors by itself. If /usr/bin/printf is found, it's
used instead of the internal printf to re-enable colors.

Change-Id: I3e6d413cd0c8a46ef91821d8c07e88166de58af4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/352
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9

It is meant to be a address and not a dereference. Otherwise MTRR
is filled with code and not with the address.

This is what I hate at most on the AT&T syntax. Instead of taking
the address, it was a dereference. Not greatly visible, except
I wondered why opcode is not 0xb4 but 0xa1 and it took another
half an our to see it.

Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.

Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/360
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

inteltool: Add Intel i63xx I/O Controller Hub

Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/356
Tested-by: build bot (Jenkins)

remove usbdebug.h include from mainboard/romstage code

No romstage is supposed to use usbdebug functions/defines
directly, so remove all those includes. The usb code is now
called and setup from console code.

Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/354
Tested-by: build bot (Jenkins)

Update coreboot cross toolchain to gcc 4.6.1

- Tested on Mac OS X 10.7.1
- Tested on Ubuntu 10.04 LTS (Lucid Lynx)
- Tested on Ubuntu 11.10 (Oneiric Ocelot)

Please test on Windows and other Linux distributions

Change-Id: I132c01293fc0cff0cfb84556a93c0b8de8e57230
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/250
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>

asus/m5a88-v: Fix build

We added some new flag for certain AMD boards after support for
this board was submitted. Also integrate the mptable refactorings
that happened in the meantime.

Change-Id: I50cf50f343a740832fd1a14a2a1ef5b903315675
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/353
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>

Fix coreboot updates

The rule to prepare a new coreboot.pre1 was ignored in the
"update image" scenario because a perfectly fine file exists.
Mark it phony to fix it.

Change-Id: Ie7f8b36b71015a593958cd6e19602bad6b854320
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/351
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

w83627hf: add method to retrieve wake event source register to ASL include

Add a method WAKS to devtree.asl which returns the wake-up source register
to simplify retrieving the wake source e.g. in \_WAK.

Change-Id: Ia258f8fc9ff79b18391c55464da73863889e2255
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/297
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add ASUS M5A88-V mainboard support

it's a AMD 880+800 mainboard. I port the code
based on the AMD reference code.
update: 1.use CIMX instead of pmio
          2.fix some whitespace
          3.fix subsystemid of devicetree.cb

Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/205
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Get rid of the old romstage-as-bootblock ROM layout

This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.

This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.

Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Get rid of AUTO_XIP_ROM_BASE

That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
This works as MTRRs are fully specified by their size and any address
within the range.

Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

sb600: Implement EHCI workaround

Linux implements it itself, but older Linuxes and other systems
might not. Without this, the host controller might not respond
to drivers.

Change-Id: I4ff0e3683c02e7aa00d188428847c64c4c5d589d
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

siemens/sitemp_g1p1: Add more devices to PIR and MP table

Linux 2.4 is happier that way

Change-Id: I016609ae1e004ec856e8223893352dcdd061b291
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/346
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Clear improper use of CONFIG_CACHE_AS_RAM

Choice between printk/print_ is related to CAR, but really
depends whether we compiled with GCC or ROMCC.

Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/347
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

T60: remove redundant usbdebug_init call()

called from console code, no need to call it here.

Change-Id: I4c34f89c82cc2478db8de4e98584e69d7ab0ca82
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/350
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

copy e7501 component to e7505

Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/310
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Prevent multiple inclusions of object files and rules

This removes 54 make warnings from the build

Change-Id: I94ac9875526febe2f95334c1c3971641c1d27f8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/338
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix checksum calculation both in romstage and ramstage.

The earlier fix for CMOS checksums only fixed the function rtc_set_checksum,
which would fix the checksum, but then coreboot would no longer honor the
settings because it assumed the checksum is wrong after this.
This change fixes the remaining functions.

Change-Id: I3f52d074df29fc29ae1d940b3dcec3aa2cfc96a5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/342
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Add support for AMD IMC controller.

This patch adds support to dump SIO like interface of AMD Embedded Controller
in the SB7xx and SB8xxx southbridges. Parts of the register interface are
documented in SBxxx RRG BDG.

Change-Id: Ib2ccaa3dfe33cfa8e7cba19d8ab0798286ad2f92
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/343
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Added smbus block read/write for amd8111

Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc
Reviewed-on: http://review.coreboot.org/281
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Move linux 2.6.11 workaround to generic code

Linux 2.6.11 seems to require a certain order in CPUs listed in mptable,
so enforce it. This was only done on arima/hdama, but now is generic.
Unfortunately this is somewhat slow.

Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/280
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

X60/T60: enable AHCI mode

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Change-Id: I2166ae9ee9e7e0e431583249f015d130d15fac61
Reviewed-on: http://review.coreboot.org/341
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

i82801gx: Fix port status in AHCI mode

The code used PCI register 0x92 to enable sata ports,
which is wrong. The ICH7 documentation states:

"This register is only used in systems that do not
support AHCI. In AHCI enabled systems, bits[3:0] must
always be set (ICH7R only) / bits[2,0] must always be set
(Mobile only), and the status of the port is controlled
through AHCI memory space."

Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write
0x0f for both variants. This patch makes sata_ahci work on
my Thinkpad T60 and X60s.

Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/340
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add -Werror to xcompile's testcc

If -Werror is not specified, tests for certain compiler flags
will emit a warning, which makes the build break since we compile
with -Werror.

Change-Id: I7be56530ff9f94e5500bad226c83e47145a808d7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/336
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix libpayload speaker driver

The frequency for the PC speaker has to be specified as
1193180 / frequency according to http://wiki.osdev.org/PC_Speaker

Change-Id: Iaca9d45807e080efe834611e719b350680b5fb90
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/337
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

X60: enable Cx power saving modes

Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/331
Tested-by: build bot (Jenkins)

T60: add _CST table

Used by power management code to enable Cx powersaving modes.

Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/322
Tested-by: build bot (Jenkins)

T60: enable C4onC3 mode

It is safe to enable this setting on these Boards.

Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

T60: use ICS954309 clock driver

Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/328
Tested-by: build bot (Jenkins)

Add driver for ICS954309 clock generator

Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/327
Tested-by: build bot (Jenkins)

i82801gx: Add setting for C4onC3 mode

If this bit is set, ich7 will enter C4 mode if possible instead of
C3. See ich7 specification (LPC controller, Power management control
registers) for more details.

Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

SPEEDSTEP: write _CST tables

Change-Id: Idb4b57044808918de343d31519768d0986840f01
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/321
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

ACPI: Add function for writing _CST tables

Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/312
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

w83627hf: correct typo in ASL include, correct indexed registers and remove unneccesary _PR0 defs

Correct a typo in devtree.asl which causes AML processors to fail executing
the DSDT with AE_NO_MEMORY or (in case of acpiexec) Divide By Zero.
Also removes an superfluous item in the register IndexField and removes
unneccessary _PR0 definitions which could confuse AML processors.

Change-Id: I02cb9ce4e8f2101cfff8cec4abba7e070fd66364
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/296
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Lenovo H8: Fix h8_set_audio_mute()

Logic is inverted (if argument is true, one would expect that
mute is enabled) and the wrong bit was used (1 instead 0)

Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/334
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

X60/T60: remove superflous h8_set_audio_mute()

muting is handled by h8 code, no need to do it here.

Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

i82801gx: Add write and read/write block functions

Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/326
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Various fixes to cbfstool.

- add ntohll and htonll (as coreboot parses 64bit fields now)
- use the same byte swapping code across platforms
- detect endianess early
- fix lots of warnings
- Don't override CFLAGS in Makefile

Change-Id: Iaea02ff7a31ab6a95fd47858d0efd9af764a3e5f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/313
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

i82801gx: Don't set I/O base address to static value

Doing it this way will break all subsequent smbus calls, because
the smbus code still uses res->base, which points to the old base
address. Fix this by allocating a proper resource.

Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/325
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)

FILO: Pass LIBCONFIG_PATH variable to FILOs make

This fixes the build for HEAD/master.
Current stable will not work, because it is too old for recent corboot.

Change-Id: I9dfd5de472d4f58f07147cb9b9bb0b543f228561
Signed-off-by: Thomas Gstädtner <thomas@gstaedtner.net>
Reviewed-on: http://review.coreboot.org/311
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Allow XGCCPATH to be set on the make command line.

The xgcc toolchain may be moved by the user and passed in on the commandline. Updates the Makefile and the xcompile script.

Change-Id: I05797b2cabce39bdd7868c2515f30d34043fc8cc
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/318
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

console: support integrated 7-segment displays for POST codes

Add a configuration option POST_PORT which defaults to 0x80 and
can be redefined by boards which have integrated POST displays
on another I/O port. Change post.c to output POST codes to this
port instead of 0x80 hardcoded.

Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/221
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

SB800: Hide unused gpp ports

Add configure option SB_GPP_UNHIDE_PORTS for mainboard
to hide/unhide the unused sb800 gpp ports.
Certain gpp port should be hidden, if no device was detected and
hotplug feature is disabled for such port.
Hidden unused ports makes lspci -vvv get more accurate information under Linux.
Test on avalue/eax-785e mainboard.

Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix CMOS checksum calculation in libpayload.

Change-Id: I64ea53fa098fbcfc76e0ebd5f049a2ee3d0a1024
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/314
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Add ifdtool, utility to read / modify Intel Firmware Descriptor images

Change-Id: Ie78b97bf573d238d0dff9a663e774deb1b7dea44
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/272
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

nvramtool: Fix CMOS checksum to match coreboot (and /dev/nvram)

Change-Id: I28b0dbad36403a31be83581107f40b3ca1332dcc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/287
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Extend coreboot table entry for serial ports

Add information about memory mapped/io mapped base addresses.

and fix up libpayload to use the same structures

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb
Reviewed-on: http://review.coreboot.org/261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Remove redunancy in Kconfig

Socket Kconfig unconditionally selects CPU_INTEL_CORE.

Change-Id: I5eb7dd17047a2a031dd7345390d7f5f756055e18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/307
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

FILO: Change FILO Makefile.inc from SVN to GIT

This commit replaces the old svn checkout code for the external FILO
payload with a git checkout for the new repo on gerrit.
The stable checkout is implemented similarly to the former SVN variant,
it checks out a specific commit (same commit as svn r136 which was
checked out before).
The HEAD checkout gets the master branch from
http://review.coreboot.org/p/filo.git
In future this should probably be changed to a stable tag or repo.
It is necessary to remove the old svn checkout by hand (or run
distclean), because I did not include code to remove an existing svn
FILO checkout.

Change-Id: I08a703f3428ae7b987f7079a4901be4cf6d7e505
Signed-off-by: Thomas Gstädtner <thomas@gstaedtner.net>
Reviewed-on: http://review.coreboot.org/308
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: fix bulk transfers on OHCI controllers

Time for the brown paper bag: OHCI controllers are not happy when
told to send data, but with obviously wrong addresses. It helps
to write the addresses into the data structures.

Change-Id: Ic0967dc8939e64af119cfb89400a045a2c077171
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/306
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

sch: strip quotes around cmc.bin filename

This was mentioned several times already, how about we get it in?
It avoids cbfstool to fail because path/to/"file" doesn't work.

Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/305
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Use ntohll where appropriate.

also clean out a local copy of ntohl in yabel.

Change-Id: Iffe85a53c9ea25abeb3ac663870eb7eb4874a704
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/288
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Add macros for 64bit byte order swapping

Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/275
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

T60: Add support for Ultrabay Legacy I/O devices (40Y8122)

Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.

To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.

Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/282
Tested-by: build bot (Jenkins)

i82801dx: Replace romstage printk's

Patch is required to compile this with romcc.

Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/291
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

asrock/e350m1: Enable the superio ACPI device in devicetree.cb

This makes the power_on_after_fail NVRAM option work correctly.

Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/292
Tested-by: build bot (Jenkins)

IOAPIC: fix bitmask

APIC ID is bits 27..24, not 19..16.

Change-Id: Ib53a480bf4328901094ca2c4713e8317321962a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/299
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

sconfig: check whether component directory actually exists

and add drivers/generic/generic back (empty), since it is used by many
devicetree.cb files.

Without this patch typos in component names in devicetree.cb cause
the component to be silently ignored.

Change-Id: I3cfca2725816f0cd7d72139ae53af815009e8ab4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/270
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Drop eh_frame instead of moving it into the image.

That's what SeaBIOS does, too, and it works just fine.

Change-Id: I3e17c15848aca86f775fc86f4ad906c820625887
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/269
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

I945: replace #if defined() by #if

config.h defines also unset config options (as "0") so #ifdef
matches both settings, which isn't what we want.

Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/293
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Append logical PME/GPIO device. Fix MPU device number.

A mainboard may require configuration of the superio pins to fully
support some features. Things like A20# gate, leds, fans, infra-red
and bootstrap jumpers may be configured and controlled through the
logical PME device.

Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/289
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Activate older Xeon P4 microcodes

As new microcode files were included, the table was not updated with
families 0f25 and 0f26.

Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/290
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix our CMOS checksum algorithm so it matches what /dev/nvram expects

Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and
BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it!

Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/279
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

rework RTC driver output to make it more consistent.

Also add a meaningful define (Not hooked up in Kconfig, that might
or might not follow)

Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/278
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

cbfstool: improve error messages

If a file can't be added by cbfstool, print the type and name of the file
in the error message.

Change-Id: I369d6f5be09ec53ee5beea2cfea65a80407f0ba3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/271
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Re-worked devicetree.cb for DL145 G1

After a lot of experimentation this commit improves some hardware
features that were not recognized or incorrectly configured before.
The only thing not tested is SCSI-option board (I dont have one).
Misleading errors in comments have been corrected.
(Note BTW that the DL145 G1 mainboard is identical to AMD Serenade
which was supported in early versions of coreboot but was dropped
for some reason.)

Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e
Reviewed-on: http://review.coreboot.org/237
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Fixes several issues with amd k8 SSDT P-state generation

First issue fixed:
For multi-socket CPU the current implementation emitted
Processor objects for cores in the first CPU only. This
commit fixes the bug by really emitting one Processor
object for each core. However, the unlikely case of mixed
CPU models is still not handled correctly.

Second issue fixed:
One loop was wrong in case a processor in the table declares
no P-states at all. The rewritten loop is safe. Some possibly
dangerous array lengths were also fixed.

Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV
according to the BKDG. The current implementation always set it
to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS.

Fourth issue: If a processor without PowerNow! support was inserted in a
system with coreboot configured with SET_FIDVID then the boot process hanged
mysteriously and very early. Apparently because init_fidvid_ap tampers with
non-existing registers. This commit fixes the bug by bailing out
from init_fidvid_ap if PowerNow! capability is missing.

Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417
Reviewed-on: http://review.coreboot.org/239
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

SMM: Move wbinvd after pmode jump

According to Rudolf Marek putting a memory instruction between
the CR0 write and the jmp in protected mode switching might hang the
machine. Move it after the jmp.

There might be a better solution for this, such as enabling the cache, as
keeping it disabled does not prevent cache poisoning attacks, so there is no
real point.

However, Intel docs say that SMM code in ASEG is always running uncached, so
we might want to consider running SMM out of TSEG instead, as well.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec
Reviewed-on: http://review.coreboot.org/283
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Tested-by: build bot (Jenkins)

use byteorder.h instead of implementing another byte swap function

Change-Id: Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/277
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

AMD CPU and chipset fixes for compilation with gcc 4.6

Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/266
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

use acpi.h include instead of manually adding acpi_slp_type.

Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/276
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

cbfs_and_run_core() is not part of the API, make it static.

It's only used in cbfs_and_run.c

Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/273
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)

reformat Makefile.bootblock.inc (>80 lines per char)

Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/274
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6

Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/268
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

Fix compilation of AMD GX2 northbridge code with gcc 4.6

Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/267
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

Fix compilation of VIA CN700 northbridge code with gcc 4.6

Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

fix compilation of intel/sch northbridge code with gcc 4.6

Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/264
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6

Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/263
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Prevent build breakage without consoles enabled

If all console types are disabled, coreboot will fail to compile because
static code is unused. This patch fixes the issue.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2
Reviewed-on: http://review.coreboot.org/260
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Load an IDT with NULL limit

Load an IDT with NULL limit to prevent the 16bit IDT being used
in protected mode before c_start.S sets up a 32bit IDT when entering
ram stage.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e
Reviewed-on: http://review.coreboot.org/259
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Fix compilation of x86emu with gcc 4.6.x

gcc 4.6 complains about unused but set variables in x86emu.
Particularly some variables are always set but only used in
debug mode, or when FPU support is enabled.

Change-Id: Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/258
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Fix native x86 option rom initialization

- Intel option roms want an initialized i8259 or they will
  throw an exception 6. This should be done in the southbridge
  code, but that is executed much later than the VGA init, so
  initialize the i8259 in src/devices/oprom/x86.c.
  In the long run this will allow getting rid of some of the
  ugly hacks in some AMD boards' romstage.c
- Don't overwrite the mode when copying mode info information back
  from 0x600.

Change-Id: Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/257
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

refactor vesa mode setting code and bootsplash code

- adds possibility to set a vesa mode without showing a bootsplash
- make bootsplash / mode setting code available in real mode.

Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/256
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Refactor option rom initialization code in coreboot.

- move int15 handler out of the generic code into the mainboard directories
  of those mainboards that actually use it.
- move vbe headers to vbe.h
- move function prototypes used in native oprom code to x86.h

Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/255
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Enable/fix compilation of i8254 code in ram stage.

Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Update "STABLE" SeaBIOS selection to release 1.6.3

1.6.3 has a lot of benefits over the previous version, the two
most important being:
 - working AHCI support
 - compiles with gcc 4.6.x

Change-Id: Ie3a4d8f2624e0aa85e48ca09da53474c085838db
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/253
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Use default table creator macro for all SSDTs

Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/262
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Fix romstage creation with gcc 4.6 and CAR targets

newer gcc versions generate ".section .text" instead of just ".text"
in their assembler output. This patch makes sure that we don't end up
with a superfluous ".section" that makes the build fail.

Add -Wno-unused-but-set-variable to CFLAGS if the flag exists.

Change-Id: I7f24c987433cc5886dde2af27498d3331cbda303
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/252
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

siemens/sitemp_g1p1: Don't mess with virtual wire settings

That function broke SMP on Linux 2.4, now it works.

Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/243
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

siemens/sitemp_g1p1: Get rid of bus_isa and bus_type

Each variable is essentially unused or incorrect.

Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/242
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

amd/sb600: Enable COM2 at all times in early setup

Otherwise with a coreboot log on COM2 (which doesn't work) the boot
process takes eons.

Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/241
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)

mptable: Refactor mptable generation some more

The last couple of lines of every mptable function were mostly
identical. Refactor into common code, a new function mptable_finalize.

Coccinelle script:
  @@
  identifier mc;
  @@
  (
  -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
  -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
  -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
  -return smp_next_mpe_entry(mc);
  +return mptable_finalize(mc);
  |
  -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
  -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
  -return smp_next_mpe_entry(mc);
  +return mptable_finalize(mc);
  )

Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/246
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>