Remove XIP_ROM_BASE

The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).

Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig
index 81070e55344126fbdf44378fda340835550a455d..abaa898b3814f971200c103fa8cae4f0f2b569d3 100755 (executable)
--- a/src/cpu/amd/agesa/family10/Kconfig
+++ b/src/cpu/amd/agesa/family10/Kconfig
@@ -40,10 +40,6 @@ config CDB
        hex
        default 0x18
 
-config XIP_ROM_BASE
-       hex
-       default 0xfff80000
-
 config XIP_ROM_SIZE
        hex
        default 0x80000

diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
index 5679396f18a64df0bdf50757f13e71a5a6d44037..c53ee57409dfeb20b9f0a13ca7c22aa62d236577 100755 (executable)
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -57,11 +57,6 @@ config CDB
        default 0x18
        depends on CPU_AMD_AGESA_FAMILY12
 
-config XIP_ROM_BASE
-       hex
-       default 0xfff80000
-       depends on CPU_AMD_AGESA_FAMILY12
-
 config XIP_ROM_SIZE
        hex
        default 0x80000

diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
index 8f3e766e6f84ce1cdd456ef85dafcdf7b2c85dc5..702270c1cc20dc91dfba52460a48321aadc46725 100644 (file)
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -57,11 +57,6 @@ config CDB
        default 0x18
        depends on CPU_AMD_AGESA_FAMILY14
 
-config XIP_ROM_BASE
-       hex
-       default 0xfff80000
-       depends on CPU_AMD_AGESA_FAMILY14
-
 config XIP_ROM_SIZE
        hex
        default 0x80000

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index b9e02f3b8fdd30e34e324a41e0031146d06b6549..955aec95146ac0a22feb76594e10281945f5baae 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -279,7 +279,7 @@ clear_fixed_var_mtrr_out:
        movl    $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
        wrmsr
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
 
        /* Enable write base caching so we can do execute in place (XIP)
         * on the flash ROM.
@@ -302,7 +302,7 @@ clear_fixed_var_mtrr_out:
 wbcache_post_fam10_setup:
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Set the default memory type and enable fixed and variable MTRRs. */
        movl    $MTRRdefType_MSR, %ecx

diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig
index c7cff14c04eb22f3626407c8a35ea9b73f84a676..ae4d45866d3426f62cd2ca7fc226f6bde16fdbfd 100644 (file)
--- a/src/cpu/amd/socket_AM2r2/Kconfig
+++ b/src/cpu/amd/socket_AM2r2/Kconfig
@@ -30,11 +30,6 @@ config CDB
        default 0x18
        depends on CPU_AMD_SOCKET_AM2R2
 
-config XIP_ROM_BASE
-       hex
-       default 0xfff80000
-       depends on CPU_AMD_SOCKET_AM2R2
-
 config XIP_ROM_SIZE
        hex
        default 0x80000

diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig
index c718eadba63bbb7f2389bbde8e6d5f5ca7fe3678..ed656f13b23b3ba9b336f92333c2e857fb2c51a9 100644 (file)
--- a/src/cpu/amd/socket_AM3/Kconfig
+++ b/src/cpu/amd/socket_AM3/Kconfig
@@ -30,11 +30,6 @@ config CDB
        default 0x18
        depends on CPU_AMD_SOCKET_AM3
 
-config XIP_ROM_BASE
-       hex
-       default 0xfff80000
-       depends on CPU_AMD_SOCKET_AM3
-
 config XIP_ROM_SIZE
        hex
        default 0x80000

diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig
index 964a59f7062820c10495fd3a1b0a31702432602f..7784a8d4dfe25aa95b0224df137934ecd43db238 100644 (file)
--- a/src/cpu/amd/socket_ASB2/Kconfig
+++ b/src/cpu/amd/socket_ASB2/Kconfig
@@ -30,11 +30,6 @@ config CDB
        default 0x18
        depends on CPU_AMD_SOCKET_ASB2
 
-config XIP_ROM_BASE
-       hex
-       default 0xfff80000
-       depends on CPU_AMD_SOCKET_ASB2
-
 config XIP_ROM_SIZE
        hex
        default 0x80000

diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
index 7ffa374962e9e80c0ab3c412ddc322813b14667c..56324dc7764dba6235d73c36307427ccbdb3129b 100644 (file)
--- a/src/cpu/amd/socket_C32/Kconfig
+++ b/src/cpu/amd/socket_C32/Kconfig
@@ -30,11 +30,6 @@ config CDB
        default 0x18
        depends on CPU_AMD_SOCKET_C32
 
-config XIP_ROM_BASE
-       hex
-       default 0xfff80000
-       depends on CPU_AMD_SOCKET_C32
-
 config XIP_ROM_SIZE
        hex
        default 0x80000

diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig
index 224059a1a16f5386ba81bfedf36ce6822037b6a1..df9856661cd3cdf698f3a0ca06367428cf8a5b2a 100644 (file)
--- a/src/cpu/amd/socket_F_1207/Kconfig
+++ b/src/cpu/amd/socket_F_1207/Kconfig
@@ -29,11 +29,6 @@ config CDB
        default 0x18
        depends on CPU_AMD_SOCKET_F_1207
 
-config XIP_ROM_BASE
-       hex
-       default 0xfff80000
-       depends on CPU_AMD_SOCKET_F_1207
-
 config XIP_ROM_SIZE
        hex
        default 0x80000

diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 26fec6e5946122794ac49b906042676e69faf41e..7742a68225e7392a30e98cb80921e33f5180ddd3 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -229,7 +229,7 @@ clear_fixed_var_mtrr_out:
        simplemask CacheSize, 0
        wrmsr
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
 
        /*
         * Enable write base caching so we can do execute in place (XIP)
@@ -250,7 +250,7 @@ clear_fixed_var_mtrr_out:
        movl    $0x0000000f, %edx
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Enable cache. */
        movl    %cr0, %eax

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 9f7ceaf247d79838d718a2995dbe79b598bac24e..eb3d650ed258b05e69044591f53fa4ed9c1afc52 100644 (file)
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -98,7 +98,7 @@ clear_mtrrs:
        orl     $(1 << 30), %eax
        movl    %eax, %cr0
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
@@ -115,7 +115,7 @@ clear_mtrrs:
        xorl    %edx, %edx
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Enable cache. */
        movl    %cr0, %eax

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 3a12cf6dd308762d41b715fe605e1da76c46bcaf..18ada2965b0afbf0fbfa71b85058ddfc7852edbc 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -98,7 +98,7 @@ clear_mtrrs:
        orl     $(1 << 30), %eax
        movl    %eax, %cr0
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
@@ -115,7 +115,7 @@ clear_mtrrs:
        movl    $0x0000000f, %edx
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Enable cache. */
        movl    %cr0, %eax

diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 2ba187271e7a30e22910e664a7c4d1027afcda1f..dfc4f3b2b9f49b1e910115ad9e653f98716310c6 100644 (file)
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -105,7 +105,7 @@ clear_mtrrs:
        orl     $(1 << 30), %eax
        movl    %eax, %cr0
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+#if CONFIG_XIP_ROM_SIZE
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
@@ -122,7 +122,7 @@ clear_mtrrs:
        movl    $0x0000000f, %edx
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Enable cache. */
        movl    %cr0, %eax

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index ad2805ea2afc44a2e03ca3b4236daf6ed3a46282..aad23690fdc9da4a41b675f40612f541cfe415e2 100644 (file)
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -240,7 +240,7 @@ testok:
        movl    $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 
-       /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
+       /* Cache XIP_ROM area to speedup coreboot code. */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
        /*

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index eed7d8f26f3233cf779e76067306c82f9e34ec4d..348f0ef92dcc18d1b03af86c39ea4a8de9b69b9d 100644 (file)
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -27,10 +27,6 @@ config TSC_CALIBRATE_WITH_IO
        bool
        default n
 
-config XIP_ROM_BASE
-       hex
-       default 0xffff0000
-
 config XIP_ROM_SIZE
        hex
        default 0x10000

diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index dc238e7a51eeb9321f58594f7870403d4b8998a8..c3b3e222f90eba54600692fadb6a62e3d1b8c25b 100644 (file)
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -45,23 +45,13 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);
 #endif
 
-/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
-#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
-# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
-#endif
-#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
-# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
-#endif
 #if !defined(CONFIG_RAMTOP)
 # error "CONFIG_RAMTOP not defined"
 #endif
 
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
+#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
 # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
 #endif
-#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
-# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
-#endif
 
 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
 # error "CONFIG_RAMTOP must be a power of 2"

diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README
index 040c24498cd8217b282ed4fa7455e6b8d874d421..485e7c852cbbba9cb410639545ef788fe732666d 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/README
+++ b/src/mainboard/supermicro/h8dmr_fam10/README
@@ -21,8 +21,3 @@ See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/
 
 Ward, 2009-09-22
 
-mansoor@iwavesystems.com said, about the last issue:
-
-  Try enabling CONFIG_XIP_ROM_BASE.  It solved the same problem for me in my board.
-
-So, that's a todo.