AMD CPU and chipset fixes for compilation with gcc 4.6

Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/266
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>

diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index bf80ef833e4067095045e59d32674fa921b436e6..2ecc0d0d601b3651f8804880703b569bcd66d1af 100644 (file)
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -16,8 +16,8 @@ static void enumerate_ht_chain(void)
        device_t dev;
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
        //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
-       unsigned real_last_unitid;
-       uint8_t real_last_pos;
+       unsigned real_last_unitid = 0;
+       uint8_t real_last_pos = 0;
        int ht_dev_num = 0; // except host_bridge
        uint8_t end_used = 0;
 #endif

diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 4d0d0259f65326498b8f7790b6e73e6562b18d22..a14adac70dd6b0e44cd3fec4e0a4487b71f087c0 100644 (file)
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -305,8 +305,8 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
 
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
        //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
-       unsigned real_last_unitid;
-       uint8_t real_last_pos;
+       unsigned real_last_unitid = 0;
+       uint8_t real_last_pos = 0;
        int ht_dev_num = 0;
        uint8_t end_used = 0;
 #endif

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 119153623490ee4007e3358ecdf602dd4931ce3a..1faed5a2e96f64673df5ecfb4d13dbddd0f0c2df 100644 (file)
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -1353,7 +1353,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
        u16 tCKproposed16x;
        u8 CLactual, CLdesired, CLT_Fail;
 
-       u8 smbaddr, byte, bytex;
+       u8 smbaddr, byte = 0, bytex = 0;
 
        CASLatLow = 0xFF;
        CASLatHigh = 0xFF;
@@ -2768,7 +2768,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat,
 static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat,
                                        u8 dct, u32 dev, u32 index_reg)
 {
-       u8 Smallest, Largest;
+       u8 Smallest = 0, Largest = 0;
        u32 val;
        u8 byte, bytex;
 

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 54fdedf08cf33418011028388371a1b7bd30302e..3e1b13d01f6fbf20168569f53c4399b4c7420604 100644 (file)
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -849,7 +849,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
        u32 value;
        u8 j;
        u32 value_test;
-       u32 value_r, value_r_test;
+       u32 value_r = 0, value_r_test = 0;
        u8 pattern, channel, BeatCnt;
        struct DCTStatStruc *ptrAddr;
 

diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index b8c7d04822f512471894a2fec3fbe072b07024e4..cf6d2dfb1a34153468a6a127628ef3ec2504a5c9 100644 (file)
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -190,7 +190,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
 {
        /* NB_InitGFXStraps */
        u32 MMIOBase, apc04, apc18, apc24, romstrap2;
-       msr_t pcie_mmio_save;
+       msr_t pcie_mmio_save = { 0, 0 };
        volatile u32 * strap;
 
        // disable processor pcie mmio, if enabled