Get rid of AUTO_XIP_ROM_BASE

That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
This works as MTRRs are fully specified by their size and any address
within the range.

Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

diff --git a/src/arch/x86/Makefile.bootblock.inc b/src/arch/x86/Makefile.bootblock.inc
index 806afea888a76f55e7c3c157471ecaef74008d4b..9787032e0fb871e99d08ada546974352865c5f73 100644 (file)
--- a/src/arch/x86/Makefile.bootblock.inc
+++ b/src/arch/x86/Makefile.bootblock.inc
@@ -76,13 +76,13 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl
 # Build the romstage
 $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld
        @printf "    LINK       $(subst $(obj)/,,$(@))\n"
-       printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" > $(obj)/location.ld
+       printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld
        $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs)
        $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin
        printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld
        $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt
        cat $(obj)/location.txt >> $(obj)/location.ld
-       printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld
+       printf ';\n' >> $(obj)/location.ld
        $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs)
        $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map
        $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 48992969f04008571cc8d9076de5823b1ddc8a8e..9d2b400f497156ce4277fe838d4ef22c3dcfa2d2 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -281,24 +281,18 @@ clear_fixed_var_mtrr_out:
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
        /* Enable write base caching so we can do execute in place (XIP)
         * on the flash ROM.
         */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
-       orl     $MTRR_TYPE_WRPROT, %eax
+       movl    copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+       orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
        movl    $MTRRphysMask_MSR(1), %ecx

diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 2310d7d9d2cc1bc31ed2b0ce599ba5752ed763c9..4ad2fce071997fa00a1f9c8d42a0f2cb08051d1d 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -231,12 +231,6 @@ clear_fixed_var_mtrr_out:
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
        /*
         * Enable write base caching so we can do execute in place (XIP)
         * on the flash ROM.
@@ -244,11 +238,11 @@ clear_fixed_var_mtrr_out:
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index da14db22ae978bc8772b70f9f6a286467731731f..b45599ac1b7ea09dc95e4b6e722165052d922030 100644 (file)
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -102,17 +102,12 @@ clear_mtrrs:
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 02de5ab50ff2f39371a1ada5c2734f8632343c6e..fa35fc9994ff74a876b1ef168b39a89dc020c91b 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -102,17 +102,12 @@ clear_mtrrs:
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 

diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 2f13d355fd31b5f9c54b6fd11963ace25f20e898..a8690112c83cdd0115080002dc9f696624c8800e 100644 (file)
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -109,17 +109,12 @@ clear_mtrrs:
        /* Enable cache for our code in Flash because we do XIP here */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 20b3220f876319181239f04c5d9831ffcdfc8ec0..d0c43c96c0c5e8b6c18fe3d4c7929d68c0de4cab 100644 (file)
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -110,12 +110,6 @@ clear_fixed_var_mtrr_out:
        movl    $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
        wrmsr
 
-#if CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
-
        /*
         * Enable write base caching so we can do execute in place (XIP)
         * on the flash ROM.
@@ -123,11 +117,11 @@ clear_fixed_var_mtrr_out:
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
        /*
-        * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
-       movl    $REAL_XIP_ROM_BASE, %eax
+       movl    copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
@@ -168,7 +162,12 @@ clear_fixed_var_mtrr_out:
        rep     stosl
 
 #ifdef CARTEST
-       movl    REAL_XIP_ROM_BASE, %esi
+       /*
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
+        * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+        */
+       movl    copy_and_run, %esi
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
        movl    %esi, %edi
        movl    $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
        rep     lodsl
@@ -244,7 +243,12 @@ testok:
        /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-       movl    $REAL_XIP_ROM_BASE, %eax
+       /*
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
+        * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+        */
+       movl    copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 

diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index dcfcccd0f3bc9e6891cee0adba377adeb9676ace..f8119d3e597abeb6e3d00800e11a85641d288576 100644 (file)
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -29,6 +29,8 @@ static void cache_lbmem(int type)
        enable_cache();
 }
 
+const int addr_det = 0;
+
 /* the fixed and variable MTTRs are power-up with random values,
  * clear them to MTRR_TYPE_UNCACHEABLE for safty.
  */
@@ -52,8 +54,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
 #if defined(CONFIG_XIP_ROM_SIZE)
        /* enable write through caching so we can do execute in place
         * on the flash rom.
+        * Determine address by calculating the XIP_ROM_SIZE sized area with
+        * XIP_ROM_SIZE alignment that contains the global variable defined above;
         */
-       set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+        unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1);
+       set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 
        /* Set the default memory type and enable fixed and variable MTRRs

diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 44a2223738061017489119e8d7ae42ceb5fde2b4..dc238e7a51eeb9321f58594f7870403d4b8998a8 100644 (file)
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -67,16 +67,4 @@ void x86_setup_fixed_mtrrs(void);
 # error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
-#if !defined (__ASSEMBLER__)
-#if defined(CONFIG_XIP_ROM_SIZE)
-# if CONFIG_TINY_BOOTBLOCK
-   extern unsigned long AUTO_XIP_ROM_BASE;
-#  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-# else
-#  define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-# endif
-#endif
-
-#endif
-
 #endif /* CPU_X86_MTRR_H */