bool
default n
-config USE_INIT
- bool
- default n
-
config ENABLE_APIC_EXT_ID
bool
default n
+++ /dev/null
-#include <build.h>
-#include <console/loglevel.h>
-
-#if CONFIG_USE_PRINTK_IN_CAR == 0
-#include "console_print.c"
-#else /* CONFIG_USE_PRINTK_IN_CAR == 1 */
-#include <console/console.h>
-#endif /* CONFIG_USE_PRINTK_IN_CAR */
-
-void console_init(void)
-{
- static const char console_test[] =
- "\r\n\r\ncoreboot-"
- COREBOOT_VERSION
- COREBOOT_EXTRA_VERSION
- " "
- COREBOOT_BUILD
- " starting...\r\n";
- print_info(console_test);
-}
-
-
-void post_code(u8 value)
-{
-#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
-#if CONFIG_SERIAL_POST==1
- print_emerg("POST: 0x");
- print_emerg_hex8(value);
- print_emerg("\r\n");
-#endif
- outb(value, 0x80);
-#endif
-}
-
-void die(const char *str)
-{
- print_emerg(str);
- do {
- hlt();
- } while(1);
-}
+++ /dev/null
-static void __console_tx_byte(unsigned char byte)
-{
- uart_tx_byte(byte);
-}
-
-static void __console_tx_nibble(unsigned nibble)
-{
- unsigned char digit;
- digit = nibble + '0';
- if (digit > '9') {
- digit += 39;
- }
- __console_tx_byte(digit);
-}
-
-static void __console_tx_char(int loglevel, unsigned char byte)
-{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
- uart_tx_byte(byte);
- }
-}
-
-static void __console_tx_hex8(int loglevel, unsigned char value)
-{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
- __console_tx_nibble((value >> 4U) & 0x0fU);
- __console_tx_nibble(value & 0x0fU);
- }
-}
-
-static void __console_tx_hex16(int loglevel, unsigned short value)
-{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
- __console_tx_nibble((value >> 12U) & 0x0fU);
- __console_tx_nibble((value >> 8U) & 0x0fU);
- __console_tx_nibble((value >> 4U) & 0x0fU);
- __console_tx_nibble(value & 0x0fU);
- }
-}
-
-static void __console_tx_hex32(int loglevel, unsigned int value)
-{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
- __console_tx_nibble((value >> 28U) & 0x0fU);
- __console_tx_nibble((value >> 24U) & 0x0fU);
- __console_tx_nibble((value >> 20U) & 0x0fU);
- __console_tx_nibble((value >> 16U) & 0x0fU);
- __console_tx_nibble((value >> 12U) & 0x0fU);
- __console_tx_nibble((value >> 8U) & 0x0fU);
- __console_tx_nibble((value >> 4U) & 0x0fU);
- __console_tx_nibble(value & 0x0fU);
- }
-}
-
-static void __console_tx_string(int loglevel, const char *str)
-{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
- unsigned char ch;
- while((ch = *str++) != '\0') {
- __console_tx_byte(ch);
- }
- }
-}
-
-#if defined (__ROMCC__)
-#define STATIC
-#else
-#define STATIC static
-#endif
-
-STATIC void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
-STATIC void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
-STATIC void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
-STATIC void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
-STATIC void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
-
-STATIC void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
-STATIC void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
-STATIC void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
-STATIC void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
-STATIC void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
-
-STATIC void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
-STATIC void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
-STATIC void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
-STATIC void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
-STATIC void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
-
-STATIC void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
-STATIC void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
-STATIC void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
-STATIC void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
-STATIC void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
-
-STATIC void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
-STATIC void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
-STATIC void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
-STATIC void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
-STATIC void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
-
-STATIC void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
-STATIC void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
-STATIC void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
-STATIC void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
-STATIC void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
-
-STATIC void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
-STATIC void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
-STATIC void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
-STATIC void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
-STATIC void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
-
-STATIC void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
-STATIC void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
-STATIC void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
-STATIC void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
-STATIC void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
-
-STATIC void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
-STATIC void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
-STATIC void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
-STATIC void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
-STATIC void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
-
driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o
driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.o
driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o
+
+$(obj)/console/console.o : $(obj)/build.h
* Bootstrap code for the INTEL
*/
-#include <arch/io.h>
#include <console/console.h>
+#include <build.h>
+#include <arch/hlt.h>
+
+#ifndef __PRE_RAM__
+#include <arch/io.h>
#include <string.h>
#include <pc80/mc146818rtc.h>
void __attribute__((noreturn)) die(const char *msg)
{
printk(BIOS_EMERG, "%s", msg);
- post_code(0xff);
- while (1); /* Halt */
+ //post_code(0xff);
+ for (;;)
+ hlt(); /* Halt */
+}
+
+#else
+
+void console_init(void)
+{
+ static const char console_test[] =
+ "\r\n\r\ncoreboot-"
+ COREBOOT_VERSION
+ COREBOOT_EXTRA_VERSION
+ " "
+ COREBOOT_BUILD
+ " starting...\r\n";
+ print_info(console_test);
+}
+
+void post_code(u8 value)
+{
+#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
+#if CONFIG_SERIAL_POST==1
+ print_emerg("POST: 0x");
+ print_emerg_hex8(value);
+ print_emerg("\r\n");
+#endif
+ outb(value, 0x80);
+#endif
}
+
+void die(const char *str)
+{
+ print_emerg(str);
+ do {
+ hlt();
+ } while(1);
+}
+#endif
extern int console_loglevel;
#endif /* !__PRE_RAM__ */
+#ifndef __ROMCC__
int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
#undef WE_CLEANED_UP_ALL_SIDE_EFFECTS
* disabling cache as ram for a maximum console log level of 6 and above while
* it worked fine without. In order to catch such issues reliably we are
* always doing a function call to do_printk with the full number of arguments.
+ * Our favorite reason to do it this way was:
+ * disable_car();
+ * printk(BIOS_DEBUG, "CAR disabled\n"); // oops, garbage stack pointer
+ * move_stack();
* This slightly increases the code size and some unprinted strings will end
* up in the final coreboot binary (most of them compressed). If you want to
* avoid this, do a
} while(0)
#endif
-#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR))
-#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR))
-#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR))
-#define print_err(STR) printk(BIOS_ERR, "%s", (STR))
-#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR))
-#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR))
-#define print_info(STR) printk(BIOS_INFO, "%s", (STR))
-#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR))
-#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR))
-
-#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH))
-#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH))
-#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH))
-#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH))
-#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH))
-#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH))
-#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH))
-#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH))
-#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH))
-
-#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX))
-#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX))
-#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX))
-#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX))
-#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX))
-#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX))
-#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX))
-#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX))
-#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX))
+#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR))
+#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR))
+#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR))
+#define print_err(STR) printk(BIOS_ERR, "%s", (STR))
+#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR))
+#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR))
+#define print_info(STR) printk(BIOS_INFO, "%s", (STR))
+#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR))
+#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR))
+
+#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH))
+#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH))
+#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH))
+#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH))
+#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH))
+#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH))
+#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH))
+#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH))
+#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH))
+
+#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX))
+#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX))
+#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX))
+#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX))
+#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX))
+#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX))
+#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX))
+#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX))
+#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX))
#define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX))
#define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX))
#define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX))
#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX))
#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX))
+#else
+/* __ROMCC__ */
+static void __console_tx_byte(unsigned char byte)
+{
+ uart_tx_byte(byte);
+}
+
+static void __console_tx_nibble(unsigned nibble)
+{
+ unsigned char digit;
+ digit = nibble + '0';
+ if (digit > '9') {
+ digit += 39;
+ }
+ __console_tx_byte(digit);
+}
+
+static void __console_tx_char(int loglevel, unsigned char byte)
+{
+ if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ uart_tx_byte(byte);
+ }
+}
+
+static void __console_tx_hex8(int loglevel, unsigned char value)
+{
+ if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ __console_tx_nibble((value >> 4U) & 0x0fU);
+ __console_tx_nibble(value & 0x0fU);
+ }
+}
+
+static void __console_tx_hex16(int loglevel, unsigned short value)
+{
+ if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ __console_tx_nibble((value >> 12U) & 0x0fU);
+ __console_tx_nibble((value >> 8U) & 0x0fU);
+ __console_tx_nibble((value >> 4U) & 0x0fU);
+ __console_tx_nibble(value & 0x0fU);
+ }
+}
+
+static void __console_tx_hex32(int loglevel, unsigned int value)
+{
+ if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ __console_tx_nibble((value >> 28U) & 0x0fU);
+ __console_tx_nibble((value >> 24U) & 0x0fU);
+ __console_tx_nibble((value >> 20U) & 0x0fU);
+ __console_tx_nibble((value >> 16U) & 0x0fU);
+ __console_tx_nibble((value >> 12U) & 0x0fU);
+ __console_tx_nibble((value >> 8U) & 0x0fU);
+ __console_tx_nibble((value >> 4U) & 0x0fU);
+ __console_tx_nibble(value & 0x0fU);
+ }
+}
+
+static void __console_tx_string(int loglevel, const char *str)
+{
+ if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ unsigned char ch;
+ while((ch = *str++) != '\0') {
+ if (ch == '\n')
+ __console_tx_byte('\r');
+ __console_tx_byte(ch);
+ }
+ }
+}
+
+#define FUNCTIONS_FOR_PRINT
+#ifdef FUNCTIONS_FOR_PRINT
+static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
+static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
+static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
+static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
+static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
+
+static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
+static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
+static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
+static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
+static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
+
+static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
+static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
+static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
+static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
+static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
+
+static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
+static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
+static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
+static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
+static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
+
+static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
+static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
+static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
+static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
+static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
+
+static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
+static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
+static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
+static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
+static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
+
+static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
+static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
+static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
+static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
+static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
+
+static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
+static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
+static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
+static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
+static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
+
+static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
+static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
+static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
+static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
+static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
+
+#else
+#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR)
+#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR)
+#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR)
+#define print_err(STR) __console_tx_string(BIOS_ERR, STR)
+#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR)
+#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR)
+#define print_info(STR) __console_tx_string(BIOS_INFO, STR)
+#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR)
+#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR)
+
+#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH)
+#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH)
+#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH)
+#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH)
+#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH)
+#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH)
+#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH)
+#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH)
+#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH)
+
+#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX)
+#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX)
+#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX)
+#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX)
+#define print_warning_hex8(HEX) __console_tx_hex8(BIOS_WARNING, HEX)
+#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX)
+#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX)
+#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX)
+#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX)
+
+#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX)
+#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX)
+#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX)
+#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX)
+#define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX)
+#define print_notice_hex16(HEX) __console_tx_hex16(BIOS_NOTICE, HEX)
+#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX)
+#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX)
+#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX)
+
+#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX)
+#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX)
+#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX)
+#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX)
+#define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX)
+#define print_notice_hex32(HEX) __console_tx_hex32(BIOS_NOTICE, HEX)
+#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX)
+#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX)
+#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX)
+#endif
+
+#endif
#endif /* CONSOLE_CONSOLE_H_ */
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#define post_code(x) outb(x, 0x80)
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#define post_code(x) outb(x, 0x80)
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "pc80/serial.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#define post_code(x) outb(x, 0x80)
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include "pc80/serial.c"
#include "./arch/i386/lib/printk_init.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/uart8250.c"
#include "console/vtxprintf.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
}
#endif
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "pc80/serial.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
#include "northbridge/intel/i82810/raminit.h"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <stdlib.h>
#include <cpu/x86/lapic.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/cn700/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#if 0
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
static const struct mem_controller mch[] = {
{
.node_id = 0,
+ /*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
+ */
/* the wiring on this part is really messed up */
/* this is my best guess so far */
.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
#include <stdlib.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include <arch/hlt.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
//#include "lib/delay.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
//#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
-
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
+#include "lib/uart8250.c"
+#include "arch/i386/lib/printk_init.c"
+#include "console/vtxprintf.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c"
#include "pc80/usbdebug_direct_serial.c"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
-
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
+#include "lib/uart8250.c"
+#include "arch/i386/lib/printk_init.c"
+#include "console/vtxprintf.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include "pc80/usbdebug_direct_serial.c"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
/* TODO: It's a PC87364 actually! */
#include "superio/nsc/pc87360/pc87360_early_serial.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83977f/w83977f_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <console/console.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG_DIRECT
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/x86/bist.h>
#include "lib/ramtest.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
static const struct mem_controller mch[] = {
{
.node_id = 0,
+ /*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
+ */
.channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
.channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
}
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/cn700/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <console/console.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG_DIRECT
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#define post_code(x) outb(x, 0x80)
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
#include "northbridge/intel/i82810/raminit.h"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-#include "arch/i386/lib/console.c"
+
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include "pc80/usbdebug_direct_serial.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if 0
static void post_code(uint8_t value) {
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include "pc80/usbdebug_direct_serial.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#if 0
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
-
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
+#include "lib/uart8250.c"
+#include "arch/i386/lib/printk_init.c"
+#include "console/vtxprintf.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include "pc80/usbdebug_direct_serial.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <arch/hlt.h>
#include "pc80/serial.c"
#include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i82830/raminit.h"
#include <console/console.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/x86/bist.h>
#if CONFIG_USBDEBUG_DIRECT
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/uart8250.c"
#include "console/vtxprintf.c"
#include "./arch/i386/lib/printk_init.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/uart8250.c"
#include "console/vtxprintf.c"
#include "./arch/i386/lib/printk_init.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
// for enable the FAN
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
#include "northbridge/intel/e7525/raminit.h"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/esb6300/esb6300_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
static const struct mem_controller mch[] = {
{
.node_id = 0,
+ /*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
+ */
.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
.channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
}
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
static const struct mem_controller mch[] = {
{
.node_id = 0,
+ /*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
+ */
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
static const struct mem_controller mch[] = {
{
.node_id = 0,
+ /*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
+ */
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
}
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
static const struct mem_controller mch[] = {
{
.node_id = 0,
+ /*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
+ */
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
}
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#define post_code(x) outb(x, 0x80)
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#define post_code(x) outb(x, 0x80)
#include <arch/hlt.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include <arch/llshell.h>
#include "pc80/serial.c"
#include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i82830/raminit.h"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
cpu_reset_x:
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
{
print_debug("Use Ram as Stack now - \r\n");
}
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#if 0
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#if 0
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#if 0
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include "pc80/usbdebug_direct_serial.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#if CONFIG_USBDEBUG_DIRECT
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
#include "pc80/usbdebug_direct_serial.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/cn700/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/vt8623/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/vx800/vx800.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
#include <string.h>
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
/* This file contains the board-special SI value for raminit.c. */
*/
unsigned v_esp;
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp));
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp=");
*/
cpu_reset = 0;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
#else
print_debug("cpu_reset = ");
else
print_debug("Use Ram as Stack now - \r\n");
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = ");
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/cn400/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <arch/hlt.h>
#include <stdlib.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/cn700/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/cx700/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
{
longjmp(end_buf, 2);
}
-#include "../../../arch/i386/lib/console.c"
+#include "console/console.c"
unsigned long log2(unsigned long x)
{
device_t dev;
unsigned where;
unsigned long reg;
- dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
+ dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + PCI_DEV(0, 0x00, 0);
where = register_values[i] & 0xff;
reg = pci_read_config32(dev, where);
reg &= register_values[i+1];
sz.side1 -= 29;
cum += (1 << sz.side1);
/* DRB = 0x60 */
- pci_write_config8(ctrl->f0, DRB + (i*2), cum);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum);
if( sz.side2 > 28) {
sz.side2 -= 29;
cum += (1 << sz.side2);
}
- pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum);
}
else {
- pci_write_config8(ctrl->f0, DRB + (i*2), cum);
- pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum);
}
}
/* set TOM top of memory 0xcc */
- pci_write_config16(ctrl->f0, TOM, cum);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), TOM, cum);
/* set TOLM top of low memory */
if(cum > 0x18) {
cum = 0x18;
}
cum <<= 11;
/* 0xc4 TOLM */
- pci_write_config16(ctrl->f0, TOLM, cum);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), TOLM, cum);
return 0;
}
}
/* 0x70 DRA */
- pci_write_config32(ctrl->f0, DRA, dra);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra);
goto out;
val_err:
static const int latency_indicies[] = { 26, 23, 9 };
/* 0x78 DRT */
- drt = pci_read_config32(ctrl->f0, DRT);
+ drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT);
drt &= 3; /* save bits 1:0 */
for(first_dimm = 0; first_dimm < 4; first_dimm++) {
}
/* 0x78 DRT */
- pci_write_config32(ctrl->f0, DRT, drt);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRT, drt);
return(cas_latency);
}
static const unsigned char fsb_conversion[4] = {3,1,3,2};
/* 0x7c DRC */
- drc = pci_read_config32(ctrl->f0, DRC);
+ drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC);
for(cnt=0; cnt < 4; cnt++) {
if (!(dimm_mask & (1 << cnt))) {
continue;
/* Set up northbridge values */
/* ODT enable */
- pci_write_config32(ctrl->f0, 0x88, 0xf0000180);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180);
/* Figure out which slots are Empty, Single, or Double sided */
for(i=0,t4=0,c2=0;i<8;i+=2) {
- c1 = pci_read_config8(ctrl->f0, DRB+i);
+ c1 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+i);
if(c1 == c2) continue;
- c2 = pci_read_config8(ctrl->f0, DRB+1+i);
+ c2 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+1+i);
if(c1 == c2)
t4 |= (1 << (i*4));
else
print_debug_hex32(data32);
print_debug("\r\n");
- pci_write_config32(ctrl->f0, 0xb0, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32);
for(dimm=0;dimm<8;dimm+=1) {
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
- pci_write_config32(ctrl->f0, DRM,
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRM,
0x00210000 | DIMM_MAP_LOGICAL);
#else
- pci_write_config32(ctrl->f0, DRM, 0x00211248);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248);
#endif
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
/* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */
for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0;
cnt<4;cnt++) {
- pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0xa0+(cnt*4), iptr[cnt]);
}
/* 0x7c DRC */
- pci_write_config32(ctrl->f0, DRC, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
/* turn the clocks on */
/* 0x8c CKDIS */
- pci_write_config16(ctrl->f0, CKDIS, 0x0000);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000);
/* 0x9a DDRCSR Take subsystem out of idle */
- data16 = pci_read_config16(ctrl->f0, DDRCSR);
+ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR);
data16 &= ~(7 << 12);
data16 |= (3 << 12); /* use dual channel lock step */
- pci_write_config16(ctrl->f0, DDRCSR, data16);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16);
/* program row size DRB */
spd_set_ram_size(ctrl, mask);
set_on_dimm_termination_enable(ctrl);
}
else { /* ddr */
- pci_write_config32(ctrl->f0, 0x88, 0xa0000000 );
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 );
}
/* receive enable calibration */
set_receive_enable(ctrl);
/* DQS */
- pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) {
write32(cnt, dqs_data[i]);
}
- pci_write_config32(ctrl->f0, 0x94, 0x3904a100 );
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 );
/* Enable refresh */
/* 0x7c DRC */
data32 = drc & ~(3 << 20); /* clear ECC mode */
- pci_write_config32(ctrl->f0, DRC, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
write32(BAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
}
/* Bring memory subsystem on line */
- data32 = pci_read_config32(ctrl->f0, 0x98);
+ data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
data32 |= (1 << 31);
- pci_write_config32(ctrl->f0, 0x98, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32);
/* wait for completion */
print_debug("Waiting for mem complete\r\n");
while(1) {
- data32 = pci_read_config32(ctrl->f0, 0x98);
+ data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
/* 0x7c DRC */
drc |= (1 << 29);
data32 = drc & ~(3 << 20); /* clear ECC mode */
- pci_write_config32(ctrl->f0, DRC, data32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32);
/* Set the ecc mode */
- pci_write_config32(ctrl->f0, DRC, drc);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc);
/* Enable memory scrubbing */
/* 0x52 MCHSCRB */
- data16 = pci_read_config16(ctrl->f0, MCHSCRB);
+ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB);
data16 &= ~0x0f;
data16 |= ((2 << 2) | (2 << 0));
- pci_write_config16(ctrl->f0, MCHSCRB, data16);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16);
/* The memory is now setup, use it */
cache_lbmem(MTRR_TYPE_WRBACK);
#define DIMM_SOCKETS 4
struct mem_controller {
unsigned node_id;
- device_t f0, f1, f2, f3;
- uint16_t channel0[DIMM_SOCKETS];
- uint16_t channel1[DIMM_SOCKETS];
+ // device_t f0, f1, f2, f3;
+ u16 channel0[DIMM_SOCKETS];
+ u16 channel1[DIMM_SOCKETS];
};
#endif /* RAMINIT_H */
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "northbridge/via/vx800/vx800.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "driving_clk_phase_data.c"
unsigned v_esp;
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)
);
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp=");
// it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy
//stack
cpu_reset = 0;
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
#else
print_debug("cpu_reset = ");
} else {
print_debug("Use Ram as Stack now - \r\n");
}
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = ");
projects / coreboot.git / commitdiff