src/mainboard/hp/dl145_g3/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #define RAMINIT_SYSINFO 1
  29
  30 #define K8_ALLOCATE_IO_RANGE 1
  31
  32 #define QRANK_DIMM_SUPPORT 1
  33
  34 #if CONFIG_LOGICAL_CPUS==1
  35 #define SET_NB_CFG_54 1
  36 #endif
  37
  38 //used by init_cpus and fidvid
  39 #define K8_SET_FIDVID 1
  40 //if we want to wait for core1 done before DQS training, set it to 0
  41 #define K8_SET_FIDVID_CORE0_ONLY 1
  42
  43 #if CONFIG_K8_REV_F_SUPPORT == 1
  44 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  45 #endif
  46
  47 #define DBGP_DEFAULT 7
  48
  49 #include <stdint.h>
  50 #include <string.h>
  51 #include <device/pci_def.h>
  52 #include <device/pci_ids.h>
  53 #include <arch/io.h>
  54 #include <device/pnp_def.h>
  55 #include <arch/romcc_io.h>
  56 #include <cpu/x86/lapic.h>
  57 #include "option_table.h"
  58 #include "pc80/mc146818rtc_early.c"
  59
  60 #include "pc80/serial.c"
  61 #include "console/console.c"
  62 #include "lib/ramtest.c"
  63
  64 #include <cpu/amd/model_fxx_rev.h>
  65
  66 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  67 #include "northbridge/amd/amdk8/raminit.h"
  68 #include "cpu/amd/model_fxx/apic_timer.c"
  69 #include "lib/delay.c"
  70
  71 #include "cpu/x86/lapic/boot_cpu.c"
  72 #include "northbridge/amd/amdk8/reset_test.c"
  73
  74 #include "superio/serverengines/pilot/pilot_early_serial.c"
  75 #include "superio/serverengines/pilot/pilot_early_init.c"
  76 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  77
  78 #include "cpu/x86/bist.h"
  79
  80 #include "northbridge/amd/amdk8/debug.c"
  81
  82 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  83
  84 #include "northbridge/amd/amdk8/setup_resource_map.c"
  85
  86 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  87 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  88
  89 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  90
  91 static void memreset_setup(void)
  92 {
  93 }
  94
  95 static void memreset(int controllers, const struct mem_controller *ctrl)
  96 {
  97 }
  98
  99 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 100 {
 101 #define SMBUS_SWITCH1 0x70
 102 #define SMBUS_SWITCH2 0x72
 103          unsigned device = (ctrl->channel0[0]) >> 8;
 104          smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
 105          smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
 106 }
 107
 108 static inline int spd_read_byte(unsigned device, unsigned address)
 109 {
 110          return smbus_read_byte(device, address);
 111 }
 112
 113 #include "northbridge/amd/amdk8/amdk8_f.h"
 114 #include "northbridge/amd/amdk8/coherent_ht.c"
 115
 116 #include "northbridge/amd/amdk8/incoherent_ht.c"
 117
 118 #include "northbridge/amd/amdk8/raminit_f.c"
 119
 120 #include "lib/generic_sdram.c"
 121
 122 //#include "resourcemap.c"
 123
 124 #include "cpu/amd/dualcore/dualcore.c"
 125
 126 //first node
 127 #define DIMM0 0x50
 128 #define DIMM1 0x51
 129 #define DIMM2 0x52
 130 #define DIMM3 0x53
 131 //second node
 132 #define DIMM4 0x54
 133 #define DIMM5 0x55
 134 #define DIMM6 0x56
 135 #define DIMM7 0x57
 136
 137 #include "cpu/amd/car/copy_and_run.c"
 138
 139 #include "cpu/amd/car/post_cache_as_ram.c"
 140
 141 #include "cpu/amd/model_fxx/init_cpus.c"
 142
 143 #include "cpu/amd/model_fxx/fidvid.c"
 144
 145 #include "northbridge/amd/amdk8/early_ht.c"
 146
 147 #if 0
 148 #include "ipmi.c"
 149
 150 static void setup_early_ipmi_serial()
 151 {
 152         unsigned char result;
 153         char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
 154         char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
 155         char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
 156         char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
 157         char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
 158
 159 //      earlydbg(0x0d);
 160         //set channel access system only
 161         ipmi_request(5,channel_access);
 162 //      earlydbg(result);
 163 /*
 164         //Set serial/modem config
 165         result=ipmi_request(6,serialmodem_conf);
 166         earlydbg(result);
 167
 168         //Set serial mux 1
 169         result=ipmi_request(4,serial_mux1);
 170         earlydbg(result);
 171
 172         //Set serial mux 2
 173         result=ipmi_request(4,serial_mux2);
 174         earlydbg(result);
 175
 176         //Set serial mux 3
 177         result=ipmi_request(4,serial_mux3);
 178         earlydbg(result);
 179 */
 180 //      earlydbg(0x0e);
 181
 182 }
 183 #endif
 184
 185 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 186 {
 187         static const uint16_t spd_addr[] = {
 188                 //first node
 189                  DIMM0, DIMM2, 0, 0,
 190                  DIMM1, DIMM3, 0, 0,
 191 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 192                 //second node
 193                 DIMM4, DIMM6, 0, 0,
 194                 DIMM5, DIMM7, 0, 0,
 195 #endif
 196
 197         };
 198
 199         struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 200
 201          int needs_reset;
 202          unsigned bsp_apicid = 0;
 203
 204          if (!cpu_init_detectedx && boot_cpu()) {
 205                  /* Nothing special needs to be done to find bus 0 */
 206                  /* Allow the HT devices to be found */
 207
 208                  enumerate_ht_chain();
 209                  bcm5785_enable_rom();
 210                  bcm5785_enable_lpc();
 211                  //enable RTC
 212                 pc87417_enable_dev(RTC_DEV);
 213          }
 214
 215          if (bist == 0) {
 216                  bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 217          }
 218
 219         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 220
 221         //setup_mp_resource_map();
 222
 223         uart_init();
 224
 225         /* Halt if there was a built in self test failure */
 226         report_bist_failure(bist);
 227
 228         console_init();
 229 //      setup_early_ipmi_serial();
 230         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 231         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 232
 233         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 234
 235 #if CONFIG_MEM_TRAIN_SEQ == 1
 236         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 237 #endif
 238         setup_coherent_ht_domain();
 239
 240         wait_all_core0_started();
 241 #if CONFIG_LOGICAL_CPUS==1
 242         // It is said that we should start core1 after all core0 launched
 243         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 244          * So here need to make sure last core0 is started, esp for two way system,
 245          * (there may be apic id conflicts in that case)
 246         */
 247         start_other_cores();
 248         wait_all_other_cores_started(bsp_apicid);
 249 #endif
 250
 251         /* it will set up chains and store link pair for optimization later */
 252         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 253         bcm5785_early_setup();
 254
 255 #if K8_SET_FIDVID == 1
 256         {
 257                 msr_t msr;
 258                 msr=rdmsr(0xc0010042);
 259                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 260         }
 261         enable_fid_change();
 262         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 263         init_fidvid_bsp(bsp_apicid);
 264         // show final fid and vid
 265         {
 266                 msr_t msr;
 267                 msr=rdmsr(0xc0010042);
 268                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 269         }
 270 #endif
 271
 272         needs_reset = optimize_link_coherent_ht();
 273         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 274
 275         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 276         if (needs_reset) {
 277                 print_info("ht reset -\r\n");
 278                 soft_reset();
 279         }
 280
 281         allow_all_aps_stop(bsp_apicid);
 282
 283         //It's the time to set ctrl in sysinfo now;
 284         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 285         enable_smbus();
 286
 287         memreset_setup();
 288         //do we need apci timer, tsc...., only debug need it for better output
 289         /* all ap stopped? */
 290 //      init_timer(); // Need to use TMICT to synconize FID/VID
 291
 292         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 293
 294         post_cache_as_ram();
 295
 296 }
 297